TW201816792A - Semiconductor memory apparatus - Google Patents

Abstract

A semiconductor memory apparatus of the invention includes: a sense amplifier, connected to a word line and a bit line for reading data from a memory element; a first switching element, connected between a first source voltage and a first power intermediate node of the sense amplifier, being conducted when driven by the sense amplifier; a second switching element, connected between a second source voltage and a second power intermediate node of the sense amplifier, being conducted when driven by the sense amplifier; and an equalizer circuit for equalizing the first and second power intermediate nodes to an equalization voltage, which is a half level between a maximum of the first power intermediate node and a minimum of the second power intermediate node. The semiconductor memory apparatus includes a control circuit that is connected with the bit line and controls a voltage of the bit line as a predetermined value based on test signals.

Description

Semiconductor memory device

The invention relates, for example, to a semiconductor memory device such as a synchronous dynamic random access memory (SDRAM).

FIG. 1 is a circuit diagram showing a configuration example of a memory circuit of a conventional SDRAM, and FIG. 2 is a timing chart showing an operation of the memory circuit of FIG. 1. In FIG. 1, a conventional memory circuit includes: memory cells MC1 and MC2 for memorizing predetermined data values; and sense amplifiers 11 and 12 which pass through a pair of bits respectively. Bit lines BLT0, BLB0, BLT1, and BLB1 are connected to the memory cells MC1, MC2, and data are sensed from the memory cells MC1, MC2.

In FIG. 1, the memory cell MC1 includes a memory capacitor Ccell1 constituting a memory element and a selective metal oxide semiconductor (MOS) transistor Q21. One end of the memory capacitor Ccell1 is connected to a source of the MOS transistor Q21 via a storage node Ns1, and the other end thereof is connected to a predetermined voltage VCP. A gate of the MOS transistor Q21 is connected to a word line WL, and a drain thereof is connected to the bit line BLB0, for example. Furthermore, the memory cell MC2 includes a memory capacitor Ccell2 constituting a memory element and a selection MOS transistor Q22. One end of the memory capacitor Ccell2 is connected to the source of the MOS transistor Q22 via a storage node Ns2, and the other end is connected to a predetermined voltage VCP. The gate of the MOS transistor Q22 is connected to the word line WL, and its drain is connected to the bit line BLB1, for example. Here, in the memory circuit of the SDRAM, a plurality of memory cells MC1 and MC2 are arranged in a grid shape in the direction of the word line WL and the direction of the bit lines BLT0, BLB0, BLT1, BLB1,....

The sense amplifier 11 is a flip-flop including a first CMOS inverter including MOS transistors Q1 and Q2 and a second CMOS inverter including MOS transistors Q3 and Q4. ). Each source of the MOS transistors Q1 and Q3 is connected to the power supply intermediate node P1. The power supply intermediate node P1 is connected to the array voltage VARAY via the MOS transistor Q5 as a switching element. The switching element is a sensing driving signal / ACT To turn on or off. Further, each source of the MOS transistors Q2 and Q4 is connected to the power supply intermediate node P2, and the power supply intermediate node P2 is grounded to the ground potential VSS via the MOS transistor Q6 as a switching element. The switching element is a sensing driving signal ACT ( Sense the driving signal / the inverting signal of ACT) to turn on or off.

The sense amplifier 12 is connected in such a manner that a third CMOS inverter including MOS transistors Q11 and Q12 and a fourth CMOS inverter including MOS transistors Q13 and Q14 constitute a flip-flop having a positive feedback loop. Each source of the MOS transistors Q11 and Q13 is connected to the power supply intermediate node P11. The power supply intermediate node P11 is connected to the array voltage VARAY via a MOS transistor Q15 as a switching element. This switching element is turned on by a sensing driving signal / ACT or disconnect. In addition, each source of the MOS transistors Q12 and Q14 is connected to the power supply intermediate node P12, and the power supply intermediate node P12 is grounded to the ground potential VSS via the MOS transistor Q16 as a switching element. The switching element is a sensing driving signal ACT ( Sense the driving signal / the inverting signal of ACT) to turn on or off.

Furthermore, the sense amplifier 11 includes an equalizer circuit 21, which includes MOS transistors Q31 to Q33. During standby, based on the equalization signal VEQ, the bit line, BLT0, BLB0 is equalized to the half-value voltage VBL of the array voltage VARAY (hereinafter referred to as the equalized voltage VBL). In addition, the sense amplifier 12 includes an equalizer circuit 22 including MOS transistors Q34 to Q36. When it is on standby, the bit line, BLT1, BLB1, etc. are equalized based on the equalization signal VEQ. Voltage VBL. The voltage VBL is connected to each of the equalizer circuits 21 and 22 via a contact 10 on a semiconductor integrated circuit. Here, the sense amplifier 11 is driven when the MOS transistors Q5, Q6, Q15, and Q16 are turned on based on the sensing drive signals ACT, / ACT.

In the sense amplifier circuit configured as described above, after the time when the equalization state is released (VEQ = L level), the selection MOS transistors Q21 and Q22 are turned on by the word line voltage VWL to select the memory cell. MC1 and MC2, and the voltages Vs1 and Vs2 of the storage nodes Ns1 and Ns2 corresponding to the data values of the memory capacitors Ccell1 and Ccell2 are transmitted to, for example, the bit lines BLB0 and BLB1 via the MOS transistors Q21 and Q22. The crystals Q5, Q6, Q15, and Q16 are turned on to activate the sense amplifiers 11, 12 so that the sense amplifiers 11, 12 amplify the bit line voltages VBLB, VBLT of the data values transmitted to the bit lines BLB0, BLB1, respectively. [Prior Art Literature]

Patent Documents: Patent Document 1: Japanese Patent Laid-Open Publication No. 2001-344995 Patent Document 2: U.S. Patent No. 6565491 Specification Patent Literature 3: Japanese Patent Laid-Open Publication No. 2007-188556 Patent Literature 4: US Patent No. 7443748 Specification Patent Document 5: Japanese Patent Laid-Open No. 11-288600

[Problems to be Solved by the Invention]

Recently, in order to reduce the chip size in order to increase the capacity and reduce the cost, the transistors used in the equalization circuit described in the prior art have also been miniaturized, and the contacts 10 connected to the equalization voltage VBL are not normally connected. There are many cases (hereinafter referred to as failure states). At this time, as shown in FIG. 2, if the equalization time of the bit line (that is, the precharge time tRP in FIG. 2) becomes long, the following occurs: natural discharge due to lack of supply of the equalization voltage VBL The change of ΔV caused by the drop of the bit line level caused by the bit line leads to poor reading. At this time, there is a problem that since the level change due to the natural discharge is the cause, a long waiting time is required, and a large amount of time is required to screen the bad condition.

An object of the present invention is to solve the above problems, and to provide a semiconductor memory device that can detect a fault state such as that the contact 10 connected to the equalized voltage VBL is not normally connected in a short time compared with the prior art. Caused by the bad condition of the equalized voltage VBL. [Means for solving problems]

A semiconductor memory device according to an embodiment of the present invention includes: a sense amplifier connected to a bit line to read data from a memory element; a first switching element connected to a predetermined first power supply voltage and the sense The first power supply intermediate node of the amplifier is turned on when the sense amplifier is driven. The second switching element is connected between a predetermined second power supply voltage and the second power supply intermediate node of the sense amplifier. The sense amplifier is turned on while driving; and an equalizer circuit that equalizes the first power intermediate node and the second power intermediate node to an equalized voltage based on the equalized signal, the equalized voltage being the first The half-value level between the maximum value of the power supply intermediate node and the minimum value of the second power supply intermediate node, the semiconductor memory device is characterized by comprising: a control circuit, the control circuit is connected to the bit line The control circuit controls a voltage of the bit line to a predetermined voltage value based on a test signal.

Furthermore, in the semiconductor memory device, the predetermined voltage value is a ground potential, and the control circuit pulls down the voltage of the bit line to a ground potential.

Furthermore, in the semiconductor memory device, the predetermined voltage value is a predetermined power supply voltage, and the control circuit pulls up the voltage of the bit line to a predetermined power supply voltage.

Furthermore, in the semiconductor memory device, the predetermined voltage value is a ground potential and a predetermined power supply voltage, and is controlled by the control circuit so that the plurality of bit lines belong to the first group. The voltage of the bit lines of the group is pulled down to the ground potential, and the voltage of the bit lines belonging to the second group among the plurality of bit lines is pulled up to the power supply voltage.

Furthermore, in the semiconductor memory device, the test signal is generated from a precharge after the equalization signal is generated to a time when the sense amplifier is driven.

Furthermore, in the semiconductor memory device, when the test signal is generated, the operation of the equalizer circuit is suspended. [Effect of the invention]

Therefore, according to the semiconductor memory device of the present invention, it is possible to detect a defective state of the equalized voltage VBL in a short time compared with the prior art, for example, due to a fault state in which the contact 10 connected to the equalized voltage VBL is not normally connected. Thereby, by reducing the test cost, it is possible to reduce the manufacturing cost and implement the exact level change, thereby improving the quality by reducing the detection omission.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same reference numerals are assigned to the same constituent elements.

In one embodiment, it is characterized in that, in order to detect a defective condition of the equalized voltage VBL caused by a fault state in which the contact 10 connected to the equalized voltage VBL is not normally connected in a short time, compared with the prior art, The electrochemical voltage VBL is changed by a method other than the fluctuation of the equivalent voltage VBL, and it does not wait for the fluctuation of the equivalent voltage VBL under a natural discharge to form a state after discharge, thereby enabling detection of a short-term malfunction. The details are described below. [Example 1]

3 is a circuit diagram showing a configuration example of a memory circuit of the SDRAM of the first embodiment. FIG. 4 is a timing chart showing an operation example of the normal state and the failure state of the memory circuit of FIG. 3.

Compared with the memory circuit of the comparative example in FIG. 1, the memory circuit of the embodiment 1 further includes a control circuit including an N-channel MOS transistor Q41 to Q44, and an equalized signal indicating an equalization. The precharge period tRP after VEQ grounds the bit lines BLB0, BLT0, BLB1, and BLT1 based on the test signal TEST.

In FIG. 3, the memory circuit of Embodiment 1 includes: memory cells MC1 and MC2 for memorizing predetermined data values; and sense amplifiers 11, 12 which pass through a pair of bit lines BLT0, BLB0, BLT1, BLB1, respectively Connected to the memory cells MC1, MC2, sensing data from the memory cells MC1, MC2; and MOS transistors Q41 to Q44, which ground the bit lines BLB0, BLT0, BLB1, BLT1 based on a test signal.

In FIG. 3, the memory cell MC1 includes a memory capacitor Ccell1 constituting a memory element and a selection MOS transistor Q21. One end of the memory capacitor Ccell1 is connected to the source of the MOS transistor Q21 via the storage node Ns1, and the other end thereof is connected to a predetermined voltage VCP. The gate of the MOS transistor Q21 is connected to the word line WL, and its drain is connected to the bit line BLB0, for example. Furthermore, the memory cell MC2 includes a memory capacitor Ccell2 constituting a memory element and a selection MOS transistor Q22. One end of the memory capacitor Ccell2 is connected to the source of the MOS transistor Q22 via a storage node Ns2, and the other end is connected to a predetermined voltage VCP. The gate of the MOS transistor Q22 is connected to the word line WL, and its drain is connected to the bit line BLB1, for example. Here, in the memory circuit of the SDRAM, a plurality of memory cells MC1 and MC2 are arranged in a grid shape in the direction of the word line WL and the direction of the bit lines BLT0, BLB0, BLT1, BLB1,....

The sense amplifier 11 is connected in such a manner that a first CMOS inverter including MOS transistors Q1 and Q2 and a second CMOS inverter including MOS transistors Q3 and Q4 constitute a flip-flop having a positive feedback loop. Each source of the MOS transistors Q1 and Q3 is connected to the power supply intermediate node P1. This power supply intermediate node P1 is connected to the array voltage VARAY via the MOS transistor Q5 as a switching element. This switching element is based on the sensing driving signal / ACT. On or off. In addition, each source of the MOS transistors Q2 and Q4 is connected to a power supply intermediate node P2. The power supply intermediate node P2 is grounded to the ground potential VSS via a MOS transistor Q6 as a switching element. The switching element is a sensing driving signal ACT ( Sense the driving signal / the inverting signal of ACT) to turn on or off.

The sense amplifier 12 is connected in such a manner that a third CMOS inverter including MOS transistors Q11 and Q12 and a fourth CMOS inverter including MOS transistors Q13 and Q14 constitute a flip-flop having a positive feedback loop. Each source of the MOS transistors Q11 and Q13 is connected to the power supply intermediate node P11. This power supply intermediate node P11 is connected to the array voltage VARAY via the MOS transistor Q15 as a switching element. This switching element is driven by a sensing driving signal / ACT. On or off. In addition, each source of the MOS transistors Q12 and Q14 is connected to a power supply intermediate node P12. The power supply intermediate node P12 is grounded to the ground potential VSS via a MOS transistor Q16 as a switching element. The switching element is a sensing driving signal ACT ( Sense the driving signal / the inverting signal of ACT) to turn on or off.

Furthermore, the sense amplifier 11 includes an equalizer circuit 21 including MOS transistors Q31 to Q33, and when on standby, based on the equalization signal VEQ, the power supply intermediate nodes P1 and P2 are equalized into the array voltage VARAY. The half-value voltage VBL. In addition, the sense amplifier 12 includes an equalizer circuit 22, which includes MOS transistors Q34 to Q36. When it is on standby, the power supply intermediate nodes P11 and P12 are equalized to an equalized voltage based on the equalized signal VEQ. VBL. The equalization voltage VBL is connected to each of the equalizer circuits 21 and 22 via a contact 10 on the semiconductor integrated circuit. Here, the sense amplifier 11 is driven when the MOS transistors Q5, Q6, Q15, and Q16 are turned on based on the sensing drive signals ACT, / ACT.

A bit line BLT0 is connected to a MOS transistor Q41 that is turned on based on the test signal TEST. Here, the test signal TEST is applied to the gate of the MOS transistor Q41, the drain of the MOS transistor Q41 is connected to the bit line BLT0, and the source of the MOS transistor Q41 is grounded. The bit line BLB0 is connected to a MOS transistor Q42 that is turned on based on the test signal TEST. Here, the test signal TEST is applied to the gate of the MOS transistor Q42, the drain of the MOS transistor Q42 is connected to the bit line BLB0, and the source of the MOS transistor Q42 is grounded.

A bit line BLT1 is connected to a MOS transistor Q43 that is turned on based on the test signal TEST. Here, the test signal TEST is applied to the gate of the MOS transistor Q43, the drain of the MOS transistor Q43 is connected to the bit line BLT1, and the source of the MOS transistor Q43 is grounded. The bit line BLB1 is connected to a MOS transistor Q44 that is turned on based on the test signal TEST. Here, the test signal TEST is applied to the gate of the MOS transistor Q44, the drain of the MOS transistor Q44 is connected to the bit line BLB1, and the source of the MOS transistor Q44 is grounded.

In the sense amplifier circuit configured as described above, after the time t4 (VEQ = L level in FIG. 4) of the equalization state is released, the selection MOS transistors Q21 and Q2 are turned on by the word line voltage VWL. The memory cells MC1 and MC2 are selected, and the voltages Vs1 and Vs2 of the storage nodes Ns1 and Ns2 corresponding to the data values of the memory capacitors Ccell1 and Ccell2 are transmitted to, for example, the bit lines BLB0 and BLB1 via the MOS transistors Q21 and Q22. Subsequently, the MOS transistors Q5, Q6, Q15, and Q16 are turned on to activate the sense amplifiers 11, 12 so that the sense amplifiers 11, 12 respectively respond to the bit line voltages VLBT, VBLB to zoom in.

In FIG. 4, the precharge period tRP is from time t1 to time t4. The MOS transistors Q41 to Q44 are turned on based on the high-level test signal TEST only from a predetermined test time from the time t2 to the time t3 after the equalization signal VEQ, thereby grounding the bit lines BLT0, BLB0, BLT1, and BLB1. . Subsequently, the test signal TEST becomes a low level, and it is as follows depending on the presence or absence of the contact 10 of the equalization voltage VBL based on the equalization signal VEQ.

(1) In the normal state, the bit line voltages VLBT and VBLB are restored to the equalized voltage VBL. After time t4, the data values can be read out from the memory cells MC1 and MC2 normally.

(2) In the abnormal state, the bit line voltages VLBT and VBLB will not return to the equalized voltage VBL. Therefore, the ground potential (101) remains unchanged and cannot be read normally from the memory cells MC1 and MC2 after time t4. Data value. Therefore, for a pair of bit lines BLT0, BLB0; BLT1, BLB1 that cause an abnormality in the equalized voltage VBL, the defective detection of the contact 10 can be achieved in a short time compared with the prior art.

In addition, as shown in FIG. 4, when the test signal TEST is at a high level, the equalization signal VEQ becomes a low level, and the operation of the equalizer circuits 21 and 22 is stopped.

As explained above, the memory circuit according to the embodiment 1 further includes a control circuit including MOS transistors Q41 to Q44, and during the precharge period tRP after the equalization signal VEQ, based on the test signal TEST. The bit lines BLB0, BLT0, BLB1, and BLT1 are grounded. Therefore, it is possible to detect a defect in the equalized voltage VBL caused by a fault state in which the contact 10 connected to the equalized voltage VBL is not normally connected in a short time compared to the prior art. situation. In addition, by reducing the test cost, it is possible to reduce manufacturing costs and implement accurate level changes, thereby improving quality by reducing detection omissions. [Example 2]

5 is a circuit diagram showing a configuration example of a memory circuit of the SDRAM of the second embodiment. Compared with the memory circuit of Embodiment 1 in FIG. 3, the memory circuit of Embodiment 2 is characterized in that it includes P-channel MOS transistors Q51 to Q54 that are turned on based on the inversion test signal / TEST instead of N-channel MOS transistors. Crystals Q41 to Q44. Differences in circuit structure are described below.

In FIG. 5, a bit line BLT0 is connected to a MOS transistor Q51 which is turned on based on the inversion test signal / TEST. Here, the inversion test signal / TEST is applied to the gate of the MOS transistor Q51, the drain of the MOS transistor Q51 is connected to the bit line BLT0, and the source of the MOS transistor Q51 is connected to the array voltage VARAY. The bit line BLB0 is connected to a MOS transistor Q52 that is turned on based on the inversion test signal / TEST. Here, the inversion test signal / TEST is applied to the gate of the MOS transistor Q52, the drain of the MOS transistor Q52 is connected to the bit line BLB0, and the source of the MOS transistor Q52 is connected to the array voltage VARAY.

A bit line BLT1 is connected to a MOS transistor Q53 that is turned on based on the inverted test signal / TEST. Here, the inversion test signal / TEST is applied to the gate of the MOS transistor Q53, the drain of the MOS transistor Q53 is connected to the bit line BLT1, and the source of the MOS transistor Q53 is connected to the array voltage VARAY. The bit line BLB1 is connected to a MOS transistor Q54 that is turned on based on the inversion test signal / TEST. Here, the inversion test signal / TEST is applied to the gate of the MOS transistor Q54, the drain of the MOS transistor Q54 is connected to the bit line BLB1, and the source of the MOS transistor Q54 is connected to the array voltage VARAY.

The memory circuit of the second embodiment configured as described above pulls the bit lines BLT0, BLB0, BLT1, and BLB1 to the array voltage VARAY based on the inversion test signal / TEST, and has the same memory as that of the first embodiment. The circuit has the same effect. In addition, the bit lines BLT0, BLB0, BLT1, and BLB1 are pulled up to the array voltage VARAY based on the inversion test signal / TEST, so that the voltages of the bit lines BLT0, BLB0, BLT1, and BLB1 do not change. [Modification]

In the memory circuits of the above embodiments, the sources of the MOS transistors Q6 and Q16 are connected to the ground potential VSS. However, the present invention is not limited to this, and may be different from the ground potential VSS and connected to the array voltage VARAY. Other low supply voltages are required.

In the above embodiments, the MOS transistors Q41 to Q44 are turned on based on the test signal TEST, so that the bit lines BLT0, BLB0, BLT1, and BLB1 are grounded. However, the present invention is not limited to this, and the bit lines can also be At least one of BLT0 and BLB0 and at least one of bit lines BLT1 and BLB1 are grounded.

In the above Embodiment 1, the bit lines BLT0, BLB0, BLT1, and BLB1 are grounded and pulled down based on the test signal TEST. In Embodiment 2, the bit lines BLT0, BLB0, BLT1, and BLT1 are based on the inversion test signal / TEST. BLB1 is pulled up to the array voltage VARAY. However, the present disclosure is not limited to this, and the voltage levels of the bit lines BLT0, BLB0, BLT1, and BLB1 may not be changed, for example, by setting to a predetermined voltage value (not limited to ground potential or array voltage VARAY (specific Power supply voltage), or the half-value voltage VBL of the array voltage VARAY, or the voltage between the ground potential and the half-value voltage VBL, the array voltage VARAY, or the voltage between the specified power supply voltage and the half-value voltage VBL) Take control. Here, the control of the predetermined voltage value may be set such that among a plurality of bit lines in the SDARM, for example, the bit lines of the first group are different from the bit lines of the second group.

In the above embodiments, the first embodiment is provided with MOS transistors Q41 to Q44, and the second embodiment is provided with MOS transistors Q51 to Q54, but the present invention is not limited to this, and one which is turned on or off based on the test signal TEST may be used. Switching elements instead of these MOS transistors.

Differences between the invention of this application and Patent Documents 1 to 5:

(1) Differences from Patent Documents 1 and 2:

Patent Documents 1 and 2 disclose a semiconductor memory device that significantly shortens the inspection time of the charge retention time characteristic inspection due to a charge leak in the direction of the bit line of the DRAM. The semiconductor memory device includes: a memory cell array formed by arranging memory cells at each intersection of a word line and a bit line pair; a plurality of sense amplifiers corresponding to each of the bit line pairs; A plurality of bit line pre-charging circuits for pre-charging and equalizing bit line pairs; and a switching circuit for normal operation and test mode, and having: a word line inactive component for The plurality of word lines are all set to an inactive state; a sense amplifier inactive component is configured to set all of the plurality of sense amplifiers to an inactive state in the specific test mode; and a bit line The potential fixing component operates in the test mode so that all the bit line pairs become the same logic level of a high level or a low level. However, in the inventions of Patent Documents 1 and 2, neither a control circuit for controlling a bit line to a predetermined voltage value based on a test signal during a precharge period tRP after an equalization signal is disclosed or taught.

(2) Differences from Patent Documents 3 and 4:

Patent Documents 3 and 4 disclose a semiconductor memory device that can detect the level of an equalizing element in an inspection step even when a plurality of equalizing elements connected to a bit line are present. malfunction. The semiconductor memory device is provided with two equalization elements, the two equalization elements are connected to the same bit line pair, and are turned on / off by the control of the control signals PDLN and PDLF. In the semiconductor memory device, during the test During the pre-charging period, one of the control signals (for example, PDLN) is set to the HIGH level, and the other (for example, PDLF) is set to the LOW level, by controlling the two equalizations individually The active and inactive elements can detect faults such as failure of the equalized element that is turned on / off by the control of the control signal. However, in the inventions of Patent Documents 3 and 4, neither a control circuit for controlling a bit line to a predetermined voltage value based on a test signal during a precharge period tRP after an equalization signal is disclosed or taught.

(3) Differences from Patent Document 5:

Patent Document 5 discloses a semiconductor memory device that shares a bit line equalization circuit with an adjacent cell array, and can effectively screen for poor equalization in a short test time. In this semiconductor memory device, the left and right cell arrays ARY-R and ARY-L share a sense amplifier circuit section S / A, a bit line pair equalization circuit section EQ, and a DQ gate circuit related to data input / output. Department of DQC. φT gates Tr1L, Tr2L, Tr1R, Tr2R are controlled to correspond to modes different from the equalization period. When the bit line potential is transferred to the selected memory cell of the cell array ARY-L (or ARY-R), The bit line potential is transferred to the bit line connected to the cell array ARY-R (or ARY-L). However, in the invention of Patent Document 5, neither a control circuit for controlling a bit line to a predetermined voltage value based on a test signal during a precharge period tRP after an equalization signal is disclosed or taught. [Industrial availability]

The semiconductor memory device of the present invention is not limited to SDRAM, and can also be applied to other types of semiconductor memory devices such as flash memory and SRAM.

10‧‧‧ contact

11, 12‧‧‧ sense amplifier

21, 22‧‧‧ equalizer circuit

101‧‧‧ ground potential

ACT, / ACT‧‧‧Sense driving signal

BLB0, BLT0, BLB1, BLT1‧‧‧bit lines

Ccell1, Ccell2‧‧‧Memory capacitor

MC1, MC2‧‧‧Memory cells

Ns1, Ns2‧‧‧Storage nodes

P1, P2, P11, P12‧‧‧ power intermediate nodes

Q1 ～ Q54‧‧‧MOS transistor

t1, t2, t3, t4‧‧‧time

TEST, / TEST‧‧‧test signal

tRP‧‧‧Precharge period

VARAY‧‧‧Array Voltage

VBL‧‧‧ equalized voltage

VBLB, VBLT‧‧‧bit line voltage

VCP‧‧‧ prescribed voltage

VEQ‧‧‧ equalized signal

Vs1, Vs2‧‧‧ Voltage

VWL‧‧‧Word line voltage

WL‧‧‧Character Line

FIG. 1 is a circuit diagram illustrating a configuration example of a memory circuit of a conventional SDRAM. FIG. 2 is a timing chart showing an operation example of a normal state and a failure state of the memory circuit of FIG. 1. 3 is a circuit diagram showing a configuration example of a memory circuit of the SDRAM of the first embodiment. FIG. 4 is a timing chart showing an operation example of a normal state and a failure state of the memory circuit of FIG. 3. 5 is a circuit diagram showing a configuration example of a memory circuit of the SDRAM of the second embodiment.

Claims (6)

A semiconductor memory device includes: a sense amplifier connected to a bit line to read data from a memory element; a first switching element connected to a predetermined first power supply voltage and a first power intermediate node of the sense amplifier Between the sense amplifiers is turned on when the sense amplifier is driven; the second switching element is connected between a predetermined second power supply voltage and a second power supply intermediate node of the sense amplifier, and is turned on when the sense amplifier is driven And an equalizer circuit that equalizes the first power intermediate node and the second power intermediate node to an equalized voltage based on an equalized signal, where the equalized voltage is a maximum value of the first power intermediate node and The half-value level between the minimum values of the second power supply intermediate nodes, the semiconductor memory device is characterized by comprising: a control circuit connected to the bit line, and based on a test signal, the bit line of the bit line is The voltage is controlled at a predetermined voltage value. The semiconductor memory device according to item 1 of the scope of patent application, wherein the predetermined voltage value is a ground potential, and the control circuit pulls down the voltage of the bit line to the ground potential. The semiconductor memory device according to item 1 of the scope of patent application, wherein the predetermined voltage value is a predetermined power supply voltage, and the control circuit pulls up the voltage of the bit line to the predetermined power supply voltage. The semiconductor memory device according to item 1 of the scope of the patent application, wherein the predetermined voltage value is a ground potential and a predetermined power supply voltage, and is controlled by the control circuit so that a plurality of bit lines belong to the first group The voltage of the bit lines of the group is pulled down to the ground potential, and the voltage of the bit lines belonging to the second group among the plurality of bit lines is pulled up to the power supply voltage. The semiconductor memory device according to item 1 of the scope of patent application, wherein the test signal is generated from a precharge after the equalization signal is generated to a time when the sense amplifier is driven. The semiconductor memory device according to item 1 of the patent application scope, wherein when the test signal is generated, the operation of the equalizer circuit is suspended.