KR100871964B1 - Test device of semiconductor device and method thereof - Google Patents

Abstract

The present invention relates to a test apparatus and method for testing semiconductor devices, in which a bit line equalization signal is forcibly disabled after a precharge command in the test of a semiconductor device to form a leak path between cell mats, A screen is displayed at an early stage. The present invention is characterized in that a first mat and a second mat which perform a read / write operation of cell data, a bit line sense amplifier which is shared by the first and second mats and which senses and amplifies cell data applied through the bit lines The bit line sense amplifier disables the bit line equalization signal after a certain time after the precharge command is applied to connect the bit line between the first mat and the second mat.

Description

Technical Field [0001] The present invention relates to a semiconductor device,

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram of a cell and a sense amplifier of a general semiconductor device; FIG.

2 is a view for explaining a repair failure of FIG. 1;

3 is a circuit diagram of a semiconductor device testing apparatus according to the present invention.

4 is an operation timing diagram relating to a method of testing a semiconductor device according to the present invention.

Description of the Related Art

10, 16: Bit line selection unit 12:

14: Amplification unit 18: Data transfer unit

The present invention relates to a test apparatus and method for testing semiconductor devices, in which a bit line equalization signal is forcibly disabled after a precharge command in the test of a semiconductor device to form a leak path between cell mats, Is an early screening technique.

As is well known, a semiconductor memory device is a semiconductor device having a plurality of unit cells and capable of storing a plurality of data. DRAM, which is most widely used among semiconductor memory devices, is a memory device capable of storing data by accumulating charges in a capacitor, and a MOS transistor serving as a capacitor and a switch forms a unit cell.

Memory devices have evolved to become more highly integrated, allowing semiconductor devices to operate at higher speeds as they evolve. Particularly, in order to highly integrate the DRAM, it is necessary to reduce the area of a cell block composed of a large number of unit cells occupying a large area.

To this end, the capacitor provided in the unit cell of the DRAM is configured to accumulate only a minimum amount of charge such that data can be held. Accordingly, since the amount of charge stored in the capacitor is very small, when a signal for holding data stored in a unit cell is outputted to the outside, it is amplified and output through a bit line sense amplifier.

On the other hand, initially, a memory cell array having an open bit line structure in which one bit line sense amplifier corresponds to one unit cell is used. However, as the DRAM is highly integrated, it has been difficult to arrange the unit cell composed of one capacitor and one MOS transistor and the bit line sense amplifier composed of four MOS transistors in correspondence with each other.

That is, in the memory cell array of the open bit line structure, the bit line (BL) connected to the bit line sense amplifier is connected to one cell block, and the bit line bar (/ BL) connected to the bit line sense amplifier is connected to the other cell block And the area occupied by the bitline sense amplifier in the memory becomes larger.

In order to solve this problem, a folded bit line structure has been proposed in which one bit line sense amplifier per two unit cells corresponds to each other. Here, the folded bit line structure is a structure in which the bit line BL and the bit line bar / BL are arranged side by side, and two unit cells are connected to one bit line sense amplifier.

1 is a schematic diagram showing a typical DRAM cell array and a sense amplifier. Here, a case where a folded bit line structure and a latch type bit line sense amplifier are used will be described as an example.

The configuration of the unit cells C1 and C2 of the DRAM is composed of one NMOS transistor T and one capacitor C adjusted by the word line WL. Here, the drain terminal of the NMOS transistor T is connected to the bit line BL, and the source terminal is connected to one electrode of the capacitor C.

One electrode of the capacitor C is defined as a storage node in which a written charge is stored. Another terminal of the capacitor C is connected to the common cell plate line, and the cell plate voltage VCP is applied through the cell plate line. The cell plate voltage is defined as a half power supply voltage (VDD). Here, the power supply voltage VDD is defined as a high operating voltage of the cell.

Both output terminals of the latch type bit line sense amplifier 1 are connected to the bit line pair BL, / BL. Then, one sense amplifier 1 senses and amplifies data on bit line pairs BL and / BL of two adjacent mat (Mat).

When the word line WL is activated and the cell data is transferred to the true bit line BL, the complement bit line / BL supplies a reference voltage REF. Conversely, when the word line WL is activated and cell data is transferred to the sub bit line / BL, the positive bit line BL supplies the reference voltage.

The upper cell array C1 and the sense amplifier 1 are connected through the NMOS transistors N1 and N2. Here, the NMOS transistors N1 and N2 are selectively activated according to the bit line selection signal BISH.

Further, the lower cell array C2 and the sense amplifier 1 are connected through the NMOS transistors N3 and N4. Here, the NMOS transistors N3 and N4 are selectively activated in accordance with the bit line selection signal BISL.

Then, upper and lower mats are distinguished according to the bit line selection signals BISH and BISL. When one of the two word lines WL is selected, the bit line select transistor of the opposite mat is turned off to reduce the bit line capacitance, thereby improving the sensing margin. Further, the pair of bit lines BL and / BL of the two mats share one sense amplifier 1.

A DRAM device having such a configuration receives a row address to enable the word line WL and then enables bit lines BL and / BL by a column select signal, thereby reading and writing data at a designated address. (not shown). That is, in a general DRAM cell structure, one word line WL is selected and enabled in the active operation, and data stored in the cell capacitor C is loaded on the bit line BL.

At this time, the potential difference between the bit line BL and the bit line bar / BL is sensed to operate the bit line sense amplifier 1. In this case, one data stored in one cell capacitor C is loaded on the bit line BL, thereby generating a potential difference between the bit line BL and the bit line bar / BL.

On the other hand, in the DRAM, if the test is performed after the first wafer is produced, a lot of failures occur. These failures are replaced with spare redundant cells and restored again. At this time, the unit for replacing the failed cells with the redundancy cells may be a mat unit, two mat units, or a bank unit.

In particular, in the case of a failure related to a row, the repair is mostly performed in a bank unit or a half bank unit. In the case of failures related to a column, most of them are repaired in matte units.

However, in the case of the fail associated with the column, if the repair is performed in the unit of the matte, the defect does not read the data of the failed column in the actual operation, but the defect itself which causes the failure is still present. Also, in a structure in which two mats share one sense amplifier 1, when a failure occurs in one mat, it affects other mats.

2 is a diagram for explaining a test result of a chip in which a fail occurs.

2 (A) shows that the first fail occurred, and (B) shows that the fail occurred in the following package state after repairing the first fail. In the wafer state, only the row and column fail occurs as shown in (A), and the repair is performed.

However, after the package, the electrical state of defects occurring on one mat is changed. As a result, the mats on the opposite sides of the sense amplifier 1 are affected, and failures are generated in the mats that have not been repaired.

To prevent this, when repairing the failures of one mat, the columns of the other mat must also be repaired at the same time. To do this, the columns of the other mat must fail in the wafer state test. By the way, when testing the column of the other mat, the bit line select transistor maintains the cut-off state. As a result, defects on one mat can not be transmitted to the other mat, making it difficult to cause failures.

SUMMARY OF THE INVENTION [0005] It is an object of the present invention to provide a semiconductor device capable of promptly displaying a potential defect of a cell mat without defects by forcibly disabling a bit line equalization signal after a precharge command in a semiconductor device to form a leakage path between cell mats have.

According to an aspect of the present invention, there is provided a semiconductor device testing apparatus including: a first mat and a second mat on which a read / write operation of cell data is performed; And a bit line sense amplifier which is shared by the first and second mats and senses and amplifies the cell data applied through the bit line, and the bit line sense amplifier outputs a bit The line equalizing signal is disabled so that the bit line between the first mat and the second mat is connected.

The semiconductor device testing method of the present invention is a semiconductor device testing apparatus including a bit line sense amplifier shared by a first mat and a second mat in which cell data read / write operations are performed, ; The bit line selection transistor connected to the first and second mats according to the precharge command is turned on; The bit line equalizing signal of the bit line sense amplifier is disabled after the precharge command is applied; And sensing a potential level of the bit line connected to the first mat and the second mat to perform a test.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a semiconductor device test apparatus according to the present invention.

The bit line sense amplifier of the present invention includes bit line selectors 10 and 16, an equalizing unit 12, an amplifying unit 14, and an output unit 18.

Here, the bit line selection unit 10 allows data to be exchanged between the equalizing unit 12 and the pair of bit lines BL and / BL connected to the first mat when the bit line selection signal BISH is activated. The bit line selection unit 16 allows data to be exchanged between the amplification unit 14 and the bit line pair BL and / BL connected to the second mat when the bit line selection signal BISL is activated.

The two cell mats are selectively connected to the amplification unit 14 in accordance with the bit line selection signals BISH and BISL. Then, two cell mats share one bit line sense amplifier. Here, the bit line selection signal BISH is an inverted signal of the bit line selection signal BISL.

The equalizing unit 12 equally equalizes the voltage between the bit line pair BL and / BL to the bit line precharge voltage VBLP level when the bit line equalizing signal BLEQ is activated. Here, the bit line precharge voltage VBLP is defined as a half power supply voltage VDD.

Further, the pull-up activation stage of the amplification section 14 is adjusted by the control signal RTO, and the pull-down activation stage is adjusted by the control signal / S. Accordingly, the amplifying unit 14 senses and amplifies data applied to the bit line pair BL and / BL.

The output unit 18 controls data input / output operations between the amplification unit 14 of the bit line sense amplifier and the data bus pair sio and siob. Then, the data of the data bus pair sio and siob is amplified and output.

The detailed circuit configuration of the present invention having such a configuration will now be described.

First, the bit line selection unit 10 includes NMOS transistors N1 and N2. The NMOS transistors N1 and N2 are connected between the first mat and the equalizing part 12, respectively, and the bit line select signal BISH is applied through the common gate terminal.

The bit line selection unit 16 includes NMOS transistors N3 and N4. The NMOS transistors N3 and N4 are connected between the second mat and the amplifying unit 14, respectively, and the bit line selection signal BISL is applied through the common gate terminal.

In addition, the equalizing unit 12 includes NMOS transistors N5 to N7. Here, the NMOS transistors N5 and N6 are connected between the bit line pair BL and / BL, and the bit line equalization signal BLEQ is applied through the common gate terminal. The bit line precharge voltage VBLP is applied to the NMOS transistors N5 and N6 through the common drain terminal. The NMOS transistor N7 is connected between the bit line pair BL and / BL, and the bit line equalization signal BLEQ is applied through the gate terminal.

When the precharge command is applied, the equalizing unit 12 activates the bit line equalizing signal BLEQ and precharges the bit line pair BL and / BL. The present invention forcibly disables the bit line equalization signal BLEQ after a predetermined time when the precharge command is applied in the test of the wafer.

Thus, the bit line pairs BL and / BL are floated in a state in which the transistors N1 to N4 of the selection units 10 and 16 are turned on. Therefore, the potential of the bit line in which a defect exists is lowered so that a failure occurs in a column test of a defect-free mat.

The amplifying unit 14 includes PMOS transistors P1 and P2 and NMOS transistors N8 and N9 connected in a cross-coupled manner. The control signal RTO is applied to the PMOS transistors P1 and P2 through the common source terminal, and the control signal / S is applied to the NMOS transistors N8 and N9 through the common source terminal.

The output section 18 includes NMOS transistors N10 and N11 and an amplifier A. [ Here, the NMOS transistors N10 and N11 are connected between the bit line pair BL and / BL and the data bus pair sio and siob, respectively. Then, amplifier A amplifies the output of data bus pair sio and siob.

4 is an operational timing diagram for a method of testing a semiconductor device according to the present invention.

First, in the precharging period t1, the voltages of the bit line pairs BL and / BL and the bit line sense amplifier control signals RTO and / S are precharged to the bit line precharge voltage VBLP. Here, the bit line pre-charge voltage is defined as a half power supply voltage (VDD), and is defined as a voltage value half of the cell high voltage (VDD).

In the present invention, if there is a defect that affects the other mat on one mat, it causes a failure of the other mat so that it can be screened early.

That is, when the word line of the first mat in which no defect exists is activated, the bit line select transistors N3 and N4 on the second mat side where the defect exists are maintained in the turned off state, so that the defect is not affected. Accordingly, when causing failures in the wafer test, the bit line select transistors N1 to N4 of both mats use the pre-charge state in which they are all open.

However, in a general pre-charge operation, the equalizing unit 12 is activated and can not properly transmit defects of the second mat to the first mat. According to the present invention, the equalizing unit 12 is forcibly disabled in the t2 period after a predetermined time in the pre-charge operation, so that defects transmitted to the first mat can be screened at the time of wafer test at the initial stage.

That is, when a predetermined time passes after the precharge command is applied, the bit line equalization signal BLEQ is disabled in the period t2. As a result, the NMOS transistors N5 to N7 are all turned off, and the bit line pair BL, / BL becomes a floating state.

In this case, the bit line pairs BL and / BL are in the floating state, and the bit line selectors 10 and 16 of both mats remain turned on. Accordingly, it is screened that the potential of the line connected to the defective cell among the bit line pair BL and / BL is dropped, so that the columnal fail can be detected.

In the present invention, the bit line equalization signal BLEQ is automatically disabled after a predetermined time after the precharge command is applied. However, the present invention is not limited to this, The bit line equalization signal BLEQ may be controlled according to the permission.

Thereafter, when an active command is applied in the period t3, charge sharing is performed. In the charge sharing period, the word line WL is activated and the cell data is loaded on the bit line pair BL, / BL. Here, the signal to which the active command is applied can be arbitrarily adjusted in the wafer test.

That is, when the word line of the first mat having no defect is activated, the bit line select transistors N3 and N4 of the second mat are turned off. However, since the potential difference between the bit line pair BL and / BL is already generated during the precharge time, even if the data is put in the cell of the mat, sensing is not properly performed, and fail occurs.

Subsequently, in the sensing and amplifying period, the control signal / S transits to the ground voltage and the control signal RTO transits to the cell high voltage VDD in order to amplify data stored in the bit line pair BL and / BL. Thus, the bit line pair BL, / BL is amplified to the cell high voltage VDD and the ground voltage.

Next, in the restoration period, data amplified in the bit line pair BL and / BL is rewritten to the cell. When the re-storing operation is completed, the pre-charge period is again entered.

In order to screen failures occurring in a mat without defects due to a defect existing in one mat, the bit line equalizing transistor is automatically turned off after a predetermined time after the precharge command is applied And the remaining operations cause a normal precharge operation to be performed.

As described above, according to the present invention, a bit line equalization signal is forcibly disabled after a precharge command in the test of a semiconductor device to form a leakage path between the cell mats, thereby promptly screening a potential defect of the cell mats without defects .

In addition, the present invention prevents a sufficiently repairable chip from failing in subsequent package testing, thereby improving the overall yield.

In addition, the present invention provides an effect that reliability can be improved by minimizing failures due to deterioration of electrical characteristics of defects generated in a mat.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. It should be seen as belonging to the scope.

Claims (7)

A first mat and a second mat on which a read / write operation of cell data is performed; And a bit line sense amplifier shared by the first mat and the second mat to sense and amplify the cell data applied through the bit line, Wherein the bit line sense amplifier disables the bit line equalization signal after a predetermined period of time after the precharge command is applied to connect the bit line between the first mat and the second mat. Device. 2. The semiconductor device test apparatus according to claim 1, wherein the bit line equalizing signal is controlled to be in a disable state by a specific command signal. 2. The method of claim 1, wherein the bit line sense amplifier An equalizing unit for equalizing the bit lines by the bit line equalization signal; An amplifier for amplifying data applied to the bit line; A first bit line selection unit connected between the first mat and the equalizing unit and controlled by a first bit line selection signal; And And a second bit line selection unit connected between the second mat and the amplification unit and controlled by a second bit line selection signal. 4. The semiconductor device according to claim 3, wherein when the precharge command is applied, the equalizing section maintains the disabled state in a state in which the first bit line selecting section and the second bit line selecting section are turned on Device. A semiconductor device testing apparatus including a bit line sense amplifier shared by a first mat and a second mat in which a read / write operation of cell data is performed, Applying a precharge command; Turning on the bit line select transistor connected to the first mat and the second mat according to the precharge command; A bit line equalization signal of the bit line sense amplifier is disabled after the precharge command is applied; And And sensing a potential level of the bit line connected to the first mat and the second mat to perform a test. 6. The method of claim 5, wherein the test is a wafer level test. 6. The method of claim 5, wherein the bit line equalization signal is controlled to a disable state by a specific command signal.

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