KR20080090683A - Test device of semiconductor device and method thereof - Google Patents

Abstract

An apparatus for testing a semiconductor device and a method thereof are provided to screen latent failure of a cell mat without a defect in advance by disabling a bit line equalizing signal after a precharge command so as to form a leakage path between cell mats in testing the semiconductor device. A first mat and a second mat perform read/write operation of cell data. A bit line sense amplifier senses and amplifies the cell data applied through a bit line by being shared by the first mat and the second mat. The bit line sense amplifier is connected to the bit line between the first mat and the second mat by disabling a bit line equalizing signal after a precharge command is applied. The bit line sense amplifier includes an equalizing part(12), an amplification part(14), a first bit line selection part(10) and a second bit line selection part(16). The equalizing part equalizes the bit line by the bit line equalizing signal. The amplification part amplifies data applied to the bit line. The first bit line selection part is controlled by a first bit line selection signal, and the second bit line selection part is controlled by a second bit line selection signal.

Description

Test device and method of a semiconductor device

1 is a schematic configuration diagram of a cell and a sense amplifier of a general semiconductor device.

FIG. 2 is a diagram for describing a repair fail of FIG. 1. FIG.

3 is a circuit diagram of a test apparatus for a semiconductor device according to the present invention.

4 is an operation timing diagram relating to a test method for a semiconductor device according to the present invention.

<Description of the symbols for the main parts of the drawings>

10,16 bit line selector 12 equalizer

14: amplification unit 18: data transmission unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus and a method of a semiconductor device, and to a potential defect of a cell mat without defects by forcibly disabling the bitline equalization signal after the precharge command during the test of the semiconductor device to form a leakage path between the cell mats. It is a technique to screen early.

As is well known, a semiconductor memory device is a semiconductor device having a plurality of unit cells and capable of storing a plurality of data. The most widely used semiconductor memory device (DRAM) is a memory device capable of storing data by accumulating charge in a capacitor, and a MOS transistor serving as a capacitor forms a unit cell.

Memory devices have evolved to become more integrated to operate at higher speeds as semiconductor technologies are developed. In particular, it is necessary to reduce the area of a cell block composed of a plurality of unit cells that occupy most of the area for high integration of the DRAM.

To this end, the capacitor provided in the unit cell of the DRAM is configured to accumulate only a minimum amount of charge such that data can be maintained. Accordingly, since the amount of charge stored in the capacitor is very small, when a signal holding data stored in the unit cell is output to the outside, the charge is amplified and output through the bit line sense amplifier.

On the other hand, a memory cell array having an open bit line structure in which one bit line sense amplifier corresponds to one unit cell was initially used. However, as the DRAM is highly integrated, there is a great difficulty in arranging a unit cell composed of one capacitor and one MOS transistor and a bit line sense amplifier composed of four MOS transistors.

That is, in the memory cell array of the open bit line structure, a cell block in which a bit line BL connected to a bit line sense amplifier is connected to one cell block and a bit line bar (/ BL) connected to the bit line sense amplifier is different In addition, the area occupied by the bit line sense amplifier in the memory is increased.

In order to solve this problem, conventionally, a folded bit line structure is proposed in which one bit line sense amplifier corresponds to two unit cells. The folded bit line structure is a structure in which the bit line BL and the bit line bar / BL are arranged side by side, and two unit cells are connected to one bit line sense amplifier.

1 is a schematic diagram illustrating a cell array and a sense amplifier of a general DRAM. Here, an example of using a folded bit line structure and a latch type bit line sense amplifier will be described.

The configuration of the unit cells C1 and C2 of the DRAM is composed of one NMOS transistor T and one capacitor C which are adjusted by the word line WL. Here, the drain terminal of the NMOS transistor T is connected to the bit line BL, and the source terminal is connected to one electrode of the capacitor C.

One electrode of the capacitor C is defined as a storage node in which a written charge is stored. Another terminal of the capacitor C is connected to the common cell plate line, and the cell plate voltage VCP is applied through the cell plate line. The cell plate voltage is defined as a half power supply voltage VDD. Here, the power supply voltage VDD is defined as a high operating voltage of the cell.

Both output terminals of the latched bit line sense amplifier 1 are connected to the bit line pair BL, / BL. Then, one sense amplifier 1 senses and amplifies data carried on bit line pairs BL and / BL of two adjacent mats.

When the word line WL is activated and cell data is transferred to the true bit line BL, the complement bit line / BL supplies a reference voltage REF. On the contrary, when the word line WL is activated and cell data is transferred to the sub bit line / BL, the positive bit line BL supplies the reference voltage.

The upper cell array C1 and the sense amplifier 1 are connected through NMOS transistors N1 and N2. Here, the NMOS transistors N1 and N2 are selectively activated according to the bit line selection signal BISH.

In addition, the lower cell array C2 and the sense amplifier 1 are connected through NMOS transistors N3 and N4. Here, the NMOS transistors N3 and N4 are selectively activated according to the bit line selection signal BISL.

The upper and lower mats are divided according to the bit line selection signals BISH and BISL. Selecting the word line WL on one of the two mats turns off the bit line selection transistors on the opposite mat, improving the sensing margin by reducing the bit line capacitance. In addition, two mat bit line pairs BL and / BL share one sense amplifier 1.

A DRAM device having such a configuration reads and writes data at a specified address by receiving a row address, enabling word line WL, and then enabling bit line BL, / BL by a column select signal. It is a memory device to write. That is, in a typical DRAM chip cell structure, one word line WL is selected and enabled during active operation, and data stored in the cell capacitor C is loaded on the bit line BL.

At this time, the bit line sense amplifier 1 operates by sensing a potential difference between the generated bit line BL and the bit line bar / BL. In this case, one data stored in one cell capacitor C is loaded on the bit line BL to generate a potential difference between the bit line BL and the bit line bar / BL.

On the other hand, in DRAM, a lot of failures occur when testing after the initial wafer is produced. These failings are replaced by redundant redundant cells and recovered again. In this case, the unit for replacing the failed cells with a redundancy cell may be a mat unit, two mat units, or a bank unit.

In particular, in the case of a fail related to a row, repair is mostly performed in units of banks or units of 1/2 bank. In the case of a fail related to a column, repairs are mostly performed in a mat unit.

By the way, in the case of a fail related to a column, if the repair is performed on a mat basis, the defect itself which causes the fail does not read data of the column in which the fail occurred during actual operation. In addition, in a structure in which two mats share one sense amplifier 1, when a mat occurs in one mat, the mat may affect another mat.

2 is a diagram for describing a test result of a chip in which a fail has occurred.

2 (A) shows that an initial fail has occurred, and (B) shows that a fail has occurred in a subsequent package state after repairing the first fail. In wafer state, as shown in (A), only row and column fail are generated and repaired.

However, after the package, the electrical state of a defect occurring in one mat is changed. As a result, the mat on the opposite side that shares the sense amplifier 1 is also affected, and a fail occurs in the non-repaired mat.

To prevent this phenomenon, when repairing a mat on one mat, the other mat's column should be repaired at the same time. To do this, the column of the other mat must be failed in the wafer state test. However, when testing the columns of the other mat, the bit line select transistor remains blocked. As a result, the defect of one mat cannot be transmitted to the other mat, which makes it difficult to cause a fail.

The present invention is to enable early screening of potential defects of a defect-free cell mat by forcibly disabling the bitline equalization signal after the precharge command during the test of the semiconductor device to form a leakage path between the cell mats. have.

In order to achieve the above object, a semiconductor device testing apparatus includes: a first mat and a second mat on which read / write operations of cell data are performed; And a bit line sense amplifier shared by the first mat and the second mat to sense and amplify the cell data applied through the bit line, wherein the bit line sense amplifier has a bit after a predetermined time has passed since the precharge command was applied. The line equalization signal is disabled so that the bit line between the first mat and the second mat is connected.

In addition, the test method of the semiconductor device of the present invention is a test device for a semiconductor device including a bit line sense amplifier shared by a first mat and a second mat on which cell data read / write operations are performed, wherein the precharge command is performed. Is applied; Turning on the bit line select transistors connected to the first mat and the second mat according to a precharge command; Disabling the bit line equalization signal of the bit line sense amplifier after the precharge command is applied; And detecting a potential level of the bit lines connected to the first mat and the second mat to perform a test.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a circuit diagram of a test apparatus for a semiconductor device according to the present invention.

The bit line sense amplifier of the present invention includes bit line selection units 10 and 16, an equalizing unit 12, an amplifier unit 14 and an output unit 18.

Here, the bit line selection unit 10 allows data exchange between the equalizing unit 12 and the bit line pair BL // BL connected to the first mat when the bit line selection signal BISH is activated. The bit line selector 16 exchanges data between the amplifier 14 and the bit line pair BL // BL connected to the second mat when the bitline select signal BISL is activated.

The two cell mats are selectively connected to the amplifier 14 according to the bit line selection signals BISH and BISL. Two cell mats share one bit line sense amplifier. Here, the bit line selection signal BISH is an inverted signal of the bit line selection signal BISL.

In addition, the equalizing unit 12 equalizes the voltage between the bit line pairs BL and / BL to the bit line precharge voltage VBLP level when the bit line equalization signal BLEQ is activated. The bit line precharge voltage VBLP is defined as a half power supply voltage VDD.

Further, the pull-up activation stage of the amplifier 14 is adjusted by the control signal RTO, and the pull-down activation stage is adjusted by the control signal / S. Accordingly, the amplifier 14 senses and amplifies data applied to the bit line pair BL // BL.

The output unit 18 controls data input / output operations between the amplifier 14 of the bit line sense amplifier and the data bus pairs sio and siob. The data of the data bus pairs sio and siob is amplified and output.

A detailed circuit configuration of the present invention having such a configuration is as follows.

First, the bit line selector 10 includes NMOS transistors N1 and N2. The NMOS transistors N1 and N2 are connected between the first mat and the equalizing unit 12, respectively, and the bit line selection signal BISH is applied through the common gate terminal.

The bit line selector 16 includes NMOS transistors N3 and N4. The NMOS transistors N3 and N4 are connected between the second mat and the amplifier 14, respectively, and the bit line selection signal BISL is applied through the common gate terminal.

In addition, the equalizing unit 12 includes NMOS transistors N5 to N7. Here, the NMOS transistors N5 and N6 are connected between the bit line pairs BL and / BL so that the bit line equalization signal BLEQ is applied through the common gate terminal. The NMOS transistors N5 and N6 receive a bit line precharge voltage VBLP through a common drain terminal. The NMOS transistor N7 is connected between the bit line pairs BL and / BL so that the bit line equalization signal BLEQ is applied through the gate terminal.

When the precharge command is applied, the equalizing unit 12 activates the bit line equalization signal BLEQ to precharge the bit line pair BL // BL. The present invention forcibly disables the bit line equalization signal BLEQ after a predetermined time when a precharge command is applied during a test of the wafer.

Accordingly, the bit line pair BL, / BL is floated while both transistors N1 to N4 of the selection units 10 and 16 are turned on. Therefore, the potential of the bit line in which the defect is present is dropped so that a failure occurs during the column test of the mat having no defect.

The amplifier 14 includes cross coupled PMOS transistors P1 and P2 and NMOS transistors N8 and N9. The control signal RTO is applied to the PMOS transistors P1 and P2 through the common source terminal, and the control signal / S is applied to the NMOS transistors N8 and N9 through the common source terminal.

The output unit 18 includes NMOS transistors N10 and N11 and amplifier A. Here, the NMOS transistors N10 and N11 are connected between the bit line pair BL // BL and the data bus pair sio and siob, respectively. The amplifier A amplifies the output of the data bus pairs sio and siob.

4 is an operation timing diagram illustrating a test method of a semiconductor device according to the present invention.

First, in the precharge period t1, the voltage of the bit line pair BL, / BL and the bit line sense amplifier control signals RTO, / S are precharged to the bit line precharge voltage VBLP. Here, the bit line precharge voltage is defined as a half power supply voltage VDD and is defined as a voltage value of half of the cell high voltage VDD.

In the present invention, if there is a defect that can affect one mat on the other mat, the other mat can be caused to fail and screen it early.

In other words, when the word line of the first mat without a defect is activated, the bit line select transistors N3 and N4 on the second mat side with the defect remain in a turn-off state, so that the defect is not transmitted. Accordingly, when failing during the wafer test, the precharge state in which the bit line select transistors N1 to N4 of both mats are opened is used.

However, during the normal precharge operation, the equalizing unit 12 is activated so that defects of the second mat cannot be properly transmitted to the first mat. In the present invention, after a predetermined time passes during the precharge operation, the equalizing unit 12 is forcibly disabled in the t2 section so that defects transferred to the first mat can be initially screened during the wafer test.

That is, when a predetermined time passes after the precharge command is applied, the bit line equalization signal BLEQ is disabled in the t2 period. As a result, all of the NMOS transistors N5 to N7 are turned off, and the bit line pair BL // BL is in a floating state.

In this case, the bit line pair BL, / BL is in a floating state, and both bit line selection units 10 and 16 of both mats are turned on. Accordingly, the potential of the line connected to the defective cell among the bit line pairs BL and / BL drops to be screened to detect the columnar failure.

Although the present invention has been described in the embodiment that the bit line equalization signal BLEQ is automatically disabled after a predetermined time after the precharge command is applied, the present invention is not limited thereto. Depending on the application, the bit line equalization signal BLEQ may be controlled.

Subsequently, when an active command is applied in the period t3, charge sharing is performed. In the charge distribution period, the word line WL is activated so that data of the cell is loaded on the bit line pair BL // BL. Here, the signal to which the active command is applied can be arbitrarily adjusted during the wafer test.

That is, when the word line of the first mat having no defect is activated, the bit line select transistors N3 and N4 of the second mat are turned off. However, a potential difference between the bit line pairs BL and / BL has already occurred during the precharge time, and thus data may not be properly sensed even when data is loaded in the cells of the mat, causing a failure.

Subsequently, in the sensing and amplification period, the control signal / S transitions to the ground voltage and the control signal RTO transitions to the cell high voltage VDD in order to amplify the data carried on the bit line pair BL // BL. As a result, the bit line pair BL, / BL is amplified to the cell high voltage VDD and the ground voltage.

Next, in the restore period, the data amplified in the bit line pair BL // BL is rewritten to the cell. When the resave operation is completed, the controller reenters the precharge section again.

The present invention automatically turns off the bitline equalization transistor after a predetermined time after the precharge command is applied, in order to prematurely screen a fail occurring in the mat where the defect does not exist due to a defect present in one mat. And the rest of the operations to perform a normal precharge operation.

As described above, the present invention forcibly disables the bit line equalization signal after the precharge command during the test of the semiconductor device to form a leakage path between the cell mats, thereby prematurely screening for potential defects of the defect-free cell mats. To help.

In addition, the present invention prevents a sufficiently repairable chip from failing in subsequent package tests to improve overall yield.

In addition, the present invention provides an effect to improve the reliability by reducing the failure due to deterioration of the electrical characteristics of the defect generated in the mat.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as being in scope.

Claims (7)

A first mat and a second mat on which read / write operations of cell data are performed; And a bit line sense amplifier configured to sense and amplify the cell data shared by the first mat and the second mat and applied through a bit line. The bit line sense amplifier may be configured to disable the bit line equalization signal after a predetermined time after the precharge command is applied, thereby connecting the bit line between the first mat and the second mat. Device. The test apparatus of claim 1, wherein the bit line equalization signal is controlled to be in a disabled state by a specific command signal. The method of claim 1, wherein the bit line sense amplifier An equalizer which equalizes the bit line by the bit line equalization signal; An amplifier for amplifying data applied to the bit line; A first bit line selector connected between the first mat and the equalizer and controlled by a first bit line select signal; And And a second bit line selector connected between the second mat and the amplifier and controlled by a second bit line select signal. 5. The apparatus of claim 4, wherein the equalizing unit maintains the disabled state when the first bit line selection unit and the second bit line selection unit are turned on when the precharge command is applied. 6. . A test apparatus for a semiconductor device comprising a bit line sense amplifier shared by a first mat and a second mat on which read / write operations of cell data are performed, Applying a precharge command; Turning on a bit line select transistor connected to the first mat and the second mat according to the precharge command; Disabling the bit line equalization signal of the bit line sense amplifier after the precharge command is applied; And And detecting a potential level of the bit line connected to the first mat and the second mat to perform a test. 6. The method of claim 5, wherein the test is a wafer level test. The test method of claim 5, wherein the bit line equalization signal is controlled to be in a disabled state by a specific command signal.

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