CN107993981B - TFT substrate and method for manufacturing the same - Google Patents
TFT substrate and method for manufacturing the same Download PDFInfo
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- CN107993981B CN107993981B CN201711178374.2A CN201711178374A CN107993981B CN 107993981 B CN107993981 B CN 107993981B CN 201711178374 A CN201711178374 A CN 201711178374A CN 107993981 B CN107993981 B CN 107993981B
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- 239000000758 substrate Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims description 20
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 134
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 131
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 239000010949 copper Substances 0.000 claims description 13
- 229910002804 graphite Inorganic materials 0.000 claims description 13
- 239000010439 graphite Substances 0.000 claims description 13
- -1 graphite alkene Chemical class 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 4
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 169
- 239000000463 material Substances 0.000 description 10
- 239000002356 single layer Substances 0.000 description 7
- 239000010408 film Substances 0.000 description 4
- 239000002041 carbon nanotube Substances 0.000 description 3
- 229910021393 carbon nanotube Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000007641 inkjet printing Methods 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000003197 catalytic effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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Abstract
A method of manufacturing a TFT substrate. First, a metal substrate is provided and a gate insulating layer is formed thereon to obtain a first primary structure. And depositing on the first primary structure to form graphene, wherein the graphene comprises a first graphene layer and a second graphene layer which are connected, the second graphene layer and part of the first graphene layer form double-layer graphene serving as an active layer, and the double-layer graphene is positioned on the gate insulating layer. An organic insulating layer is formed on the graphene. And forming a bottom gate on the organic insulating layer to obtain a second primary structure. And turning the second primary structure up and down to enable the bottom grid electrode to be positioned at the lowest layer and the metal substrate to be positioned at the uppermost layer. And etching the metal substrate to form a source electrode, a top grid electrode and a drain electrode. The source electrode and the drain electrode are connected with the first graphene layer, so that the contact resistance among the source electrode, the drain electrode and the double-layer graphene is reduced. The invention also provides a TFT substrate.
Description
Technical Field
The invention relates to the technical field of display, in particular to a TFT substrate and a manufacturing method thereof.
Background
In the active matrix display technology, each pixel is driven by a Thin Film Transistor (TFT) integrated behind the pixel, so that a screen display effect with high speed, high brightness and high contrast can be realized. A common TFT is generally composed of three Gate/Source/Drain (Gate/Source/Drain) electrodes, an insulating layer, and a semiconductor layer.
Graphene, which is the thinnest and hardest nanomaterial in the world known at present, has good electrical conductivity and controllability, mechanical properties, and thermal conductivity, and thus is one of the current research hotspots. Graphene, as a novel material with extremely thin and high conductivity, has great potential to be applied to electronic components/transistors. According to the report, the graphene thin film has very low sheet resistance (<100 Ω/□), and after doping, a two-dimensional insulating material with a broadband can be formed, so that after certain processing, the graphene can form n-type or p-type semiconductor characteristics, and can be applied to TFT devices in the display industry. However, the method has the defects of difficult adjustment of the treatment process, difficult guarantee of the performance and difficult application to TFT devices in the display industry.
Disclosure of Invention
In order to solve the foregoing problems, the present invention provides a TFT substrate and a method of manufacturing the same.
A method of manufacturing a TFT substrate, comprising the steps of:
step S101, providing a metal substrate, and forming a gate insulation layer on the metal substrate to obtain a first primary structure;
step S102, depositing on the first primary structure to form graphene, wherein the graphene comprises a first graphene layer and a second graphene layer which are connected, the second graphene layer and part of the first graphene layer form double-layer graphene serving as an active layer, and the double-layer graphene is located on the gate insulating layer;
step S103, forming an organic insulating layer on the first graphene layer and the second graphene layer;
step S104, forming a bottom grid electrode on the organic insulating layer to obtain a second primary structure;
step S105, turning the second primary structure up and down to enable the bottom grid to be located at the lowermost layer and the metal substrate to be located at the uppermost layer;
step S106, etching the metal substrate to form a source electrode, a top grid electrode and a drain electrode, wherein the source electrode and the drain electrode are connected with the first graphene layer, and the top grid electrode is connected with the grid electrode insulating layer.
Further, in the step S101, the following steps are included:
providing the metal substrate, and depositing and forming a non-pattern inorganic insulating layer on the metal substrate;
forming a patterned first photoresist layer on the inorganic insulating layer;
forming the patterned gate insulating layer through a curing process;
and stripping the first photoresist layer to form the first primary structure.
Further, in the step S106, the following steps are included: forming a patterned second photoresist layer on one surface of the metal substrate, which is far away from the gate insulation layer; etching the metal substrate to obtain the source electrode, the top grid electrode and the drain electrode; and stripping the second photoresist layer.
Further, the material of the metal substrate is copper or nickel.
Further, the material of the gate insulating layer is one of silicon dioxide, yttrium oxide and hafnium oxide.
Further, the material of the organic insulating layer is polymethyl methacrylate.
Further, in step S102, the graphene is deposited by a plasma enhanced chemical vapor deposition method.
The utility model provides a TFT base plate, its includes bottom gate, organic insulating layer, graphite alkene, gate insulation layer, source electrode, top gate and drain electrode, the bottom gate the organic insulating layer graphite alkene reaches the gate insulation layer is range upon range of setting in proper order, graphite alkene is including connecting first graphite alkene layer and the second graphite alkene layer that sets up, first graphite alkene layer is located on the organic insulating layer, first graphite alkene layer with the source electrode the drain electrode is connected, second graphite alkene layer and part first graphite alkene layer forms double-deck graphite alkene and is used as the active layer, double-deck graphite alkene presss from both sides and locates organic insulating layer with between the gate insulation layer, the top gate with the gate insulation layer is connected.
Further, the organic insulating layer forms an accommodating groove, the gate insulating layer is accommodated in the accommodating groove, and the double-layer graphene is arranged at the bottom of the accommodating groove adjacent to the organic insulating layer.
Further, the organic insulating layer includes a first surface, a second surface, a third surface, a fourth surface, and a fifth surface, which are sequentially connected to each other, the second surface, the third surface, and the fourth surface enclose the accommodating groove, a first side surface of the gate insulating layer is disposed adjacent to the third surface, the first graphene layer is connected to the first surface, the second surface, the third surface, the fourth surface, and the fifth surface, the second graphene layer is sandwiched between the third surface and the first graphene layer, the source electrode is located on the first surface, and the drain electrode is located on the fifth surface.
According to the TFT substrate and the manufacturing method thereof, the first graphene layer and the second graphene layer are arranged on the grid electrode insulating layer to form double-layer graphene serving as an active layer, and a vertical electric field is controlled through the top grid electrode and the bottom grid electrode, so that the switching function of the TFT is achieved. The source electrode and the drain electrode are connected with the double-layer graphene through the single-layer graphene, so that contact resistance between the source electrode and the active layer and between the drain electrode and the active layer can be reduced, and the performance of the TFT substrate is improved. Further, the metal substrate for depositing the graphene is reused as a raw material for manufacturing the source electrode, the top gate electrode and the drain electrode, so that the manufacturing process is simplified and the cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a cross-sectional view of a TFT substrate provided in an embodiment of the present invention.
Fig. 2 is a flowchart of a method for manufacturing a TFT substrate according to an embodiment of the present invention.
Fig. 3 is a cross-sectional view of the first preliminary structure formed in step S101 shown in fig. 2.
Fig. 4 is a sectional view of the structure formed in step S102 shown in fig. 2.
Fig. 5 is a sectional view of the structure formed in step S103 shown in fig. 2.
Fig. 6 is a sectional view of the second preliminary structure formed in step S104 shown in fig. 2.
Fig. 7 is a cross-sectional view of the second precursor structure shown in fig. 6, inverted upside down.
Fig. 8 is a flowchart of step S101 of the method of manufacturing the TFT substrate.
Fig. 9 is a sectional view of the structure formed in step S81 shown in fig. 8.
Fig. 10 is a sectional view of the structure formed in step S82 shown in fig. 8.
Fig. 11 is a sectional view of the structure formed in step S83 shown in fig. 8.
Fig. 12 is a flowchart of step S106 of the method of manufacturing the TFT substrate.
Fig. 13 is a sectional view of the structure formed in step S91 shown in fig. 12.
Fig. 14 is a sectional view of the structure formed in step S92 shown in fig. 12.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a TFT substrate 1 according to an embodiment of the present invention is shown. The TFT substrate 1 includes a bottom gate electrode 10, an organic insulating layer 20, graphene 30, a gate insulating layer 40, a source electrode 51, a top gate electrode 53, and a drain electrode 55.
Specifically, in the present embodiment, the bottom gate 10 is a carbon nanotube layer, and it is understood that the bottom gate 10 may also be a stack combination of one or more of molybdenum (Mo), aluminum (Al), and copper (Cu).
The organic insulating layer 20 is disposed on the bottom gate electrode 10. The thickness of the organic insulating layer 20 is 1 μm. The dielectric constant of the organic insulating layer 20 needs to be 3 times of the vacuum dielectric constant, for example, the material of the organic insulating layer 20 is polymethyl methacrylate.
Further, the organic insulating layer 20 includes a first surface 21, a second surface 22, a third surface 23, a fourth surface 24, and a fifth surface 25, which are sequentially connected to each other. The second surface 22, the third surface 23 and the fourth surface 24 enclose the accommodating groove 27.
The graphene 30 is disposed on the organic insulating layer 20 and away from the bottom gate 10, and is partially accommodated in the accommodating groove 27. The graphene 30 is a double-layer graphene on the third surface 23, and is a single-layer graphene on the first surface 21, the second surface 22, the fourth surface 24, and the fifth surface 25. Specifically, the graphene 30 includes a first graphene layer 35 and a second graphene layer 37 connected to the first graphene layer 35. The first graphene layer 35 is disposed on the first surface 21, the second surface 22, the third surface 23, the fourth surface 24, and the fifth surface 25. The second graphene layer 37 is connected to the first graphene layer 35. The second graphene layer 37 is sandwiched between the first graphene layer 35 and the third surface 22. The double-layer graphene serves as an active layer.
The gate insulating layer 40 is disposed on the graphene 30 and is accommodated in the accommodating groove 27. In this embodiment, the gate insulating layer 40 is a silicon dioxide insulating layer. The gate insulating layer 20 is not limited to a silicon dioxide material, and may be replaced by other inorganic insulating materials, such as yttrium oxide (Y)2O3) Hafnium oxide (HfO)2). The gate insulating layer 40 includes a first side 41 and a second side 43, which are oppositely disposed, and the first side 41 is disposed adjacent to the third surface 23 and the second graphene layer 37. In other words, the second graphene layer 37 is disposed corresponding to the first side surface 41. The double-layer graphene is disposed at the bottom of the accommodating groove 27 adjacent to the organic insulating layer 20.
The source 51 is disposed on the first graphene layer 35 and connected to the first graphene layer 35. The source electrode 51 is located above the first surface 21. The source electrode 51 is distant from the organic insulating layer 20.
The top gate electrode 53 is disposed on the gate insulating layer 40 and away from the organic insulating layer 20.
The drain electrode 55 is connected to the first graphene layer 35 and the first graphene layer 35. The drain electrode 55 is located on the fifth surface 21. The drain electrode 55 is remote from the organic insulating layer 20.
The source electrode 51 and the drain electrode 55 are connected to double-layer graphene serving as an active layer through single-layer graphene, so that contact resistance between the source electrode 51 and the active layer and between the drain electrode 55 and the active layer is reduced. In this embodiment, the source 51, the drain 55 and the top gate 53 are made of copper (Au).
Referring to fig. 2, a method for manufacturing a TFT substrate according to an embodiment of the present invention includes the following steps:
in step S101, referring to fig. 3, a metal substrate 50 is provided, and a gate insulating layer 40 is formed on the metal substrate 50, so as to obtain a first primary structure 100.
Specifically, the material of the metal substrate 50 may be used as a substrate material for depositing and preparing a graphene film, and also has a conductive property for being used as an electrode material, for example, a metal material such as copper (Cu) or nickel (Ni). In this embodiment, copper (Cu) is selected as the metal substrate, and the thickness thereof is about 1 μm (micrometer).
The gate insulating layer 40 is a silicon dioxide insulating layer. The gate insulating layer 40 is not limited to a silicon dioxide material, and may be replaced by other inorganic insulating materials, such as yttrium oxide (Y)2O3) Hafnium oxide (HfO)2). The gate insulating layer 40 includes a first side surface 41 and a second side surface 43 disposed opposite to each other, and the first side surface 41 is disposed away from the metal substrate 50.
The first primary structure 100 includes a first region 102 and a second region 103 connected to each other, the first region 102 is a region where the first side 41 is located, and the second region 103 is a remaining portion of the side of the first primary structure 100 adjacent to the first side 41.
Step S102, please refer to fig. 4, depositing graphene 30 on the first primary structure 100, where the graphene 30 includes a first graphene layer 35 and a second graphene layer 37 connected to each other, the second graphene layer 37 and a portion of the first graphene layer 35 form a double-layer graphene as an active layer, and the double-layer graphene is located on the gate insulating layer 40.
Specifically, the graphene 30 is a double-layer graphene in the first region 102, and a single-layer graphene in the second region 103. The first graphene layer 35 is formed in the first region 102 and the second region 103. The second graphene layer 37 is formed on the first region 102. The second graphene layer 37, the first graphene layer 35, and the gate insulating layer 40 are stacked in this order. In other words, double-layer graphene is formed on the first side 41 of the gate insulating layer 40.
The graphene is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD). In this embodiment, in the preparation process, by controlling parameters, due to the catalytic action of Cu, only the double-layer graphene is deposited in the first region 102, and the single-layer graphene is obtained in the second region 103.
In step S103, referring to fig. 5, an organic insulating layer 20 is formed on the first graphene layer 35 and the second graphene layer 37.
The second graphene layer 37 is sandwiched between the first graphene layer 35 and the organic insulating layer 20.
The organic insulating layer 20 is formed by solution coating and curing. The thickness of the organic insulating layer 20 is about 1 μm. The dielectric constant of the organic insulating layer 20 needs to be 3 times of the vacuum dielectric constant, for example, the material of the organic insulating layer 20 is polymethyl methacrylate.
Further, the organic insulating layer 20 includes a first surface 21, a second surface 22, a third surface 23, a fourth surface 24, and a fifth surface 25, which are sequentially connected to each other. The second surface 22, the third surface 23 and the fourth surface 24 enclose the accommodating groove 27. The graphene 30 is partially accommodated in the accommodating groove 27. The graphene 30 is a double-layer graphene on the third surface 23, and is a single-layer graphene on the first surface 21, the second surface 22, the fourth surface 24, and the fifth surface 25.
The first graphene layer 35 is disposed adjacent to the first surface 21, the second surface 22, the third surface 23, the fourth surface 24, and the fifth surface 25.
The second graphene layer 37 is sandwiched between the first graphene layer 35 and the third surface 22.
In step S104, referring to fig. 6, a bottom gate 10 is formed on the organic insulating layer 20 to obtain a second preliminary structure 200.
In this embodiment, the bottom gate 10 is a carbon nanotube layer, and the organic insulating layer 20 is formed by printing carbon nanotube ink using an inkjet printing method to obtain a patterned carbon nanotube layer.
It is understood that the bottom gate 10 may also be a stacked combination of one or more of molybdenum (Mo), aluminum (Al), and copper (Cu).
In step S105, referring to fig. 7, the second preliminary structure 200 is turned upside down, such that the bottom gate 10 is located at the lowermost layer and the metal substrate 50 is located at the uppermost layer.
Step S106, referring to fig. 1 again, the metal substrate 50 is etched to form a source 51, a top gate 53 and a drain 55, so as to obtain the TFT substrate 1, wherein the source 51 and the drain 55 are connected to the first graphene layer 35, and the top gate 53 is disposed on the second side surface 43 of the gate insulating layer 40.
The source electrode 51 is located on the first surface 21, and the drain electrode 55 is located on the fifth surface 25.
Further, in step S101, providing a metal substrate 50, and forming a gate insulating layer 40 on the metal substrate 50, referring to fig. 8, the method specifically includes the following steps:
in step S81, referring to fig. 9, the metal substrate 50 is provided, and the inorganic insulating layer 46 is deposited on the metal substrate 50 without patterns.
In step S82, referring to fig. 10, a patterned first photoresist layer 47 is formed on the inorganic insulating layer 46.
Specifically, the patterned second photoresist layer 91 is obtained by a mask-coating photoresist-developing process.
In step S83, referring to fig. 11, a patterned gate insulating layer 40 is formed by a curing process.
In step S84, referring to fig. 3 again, the first photoresist layer 47 is stripped to form the first preliminary structure 100.
In step S84, in this embodiment, the first photoresist layer 47 is stripped by using a photoresist removing solution that does not corrode the metal substrate 50.
Further, in step 106, that is, in the step of forming the source electrode 51, the top gate 53 and the drain electrode 55 on the metal substrate 50, referring to fig. 12, the method specifically includes the following steps:
in step S91, referring to fig. 13, a patterned second photoresist layer 91 is formed on a surface of the metal substrate 50 away from the gate insulating layer 40.
Specifically, the patterned second photoresist layer 91 is obtained by a second photo-mask-photoresist coating-developing process.
In step S92, referring to fig. 14, the metal substrate 50 is etched to obtain a source 51, a top gate 53 and a drain 55.
In step S93, the second photoresist layer 91 is stripped.
According to the TFT substrate and the manufacturing method thereof, the first graphene layer 35 and the second graphene layer 37 are arranged on the first side surface 41 of the grid electrode insulating layer 40 to form double-layer graphene to serve as an active layer, the source electrode 51 and the drain electrode 55 are connected with the double-layer graphene through the single-layer graphene, so that contact resistance between the source electrode 51 and the active layer and between the drain electrode 55 and the active layer can be reduced, and the performance of the TFT substrate 1 is improved. Furthermore, the double-layer graphene is used as an active layer, and a vertical electric field is controlled by two gates of the top gate machine 53 and the bottom gate 10, thereby performing a switching function of the TFT. Furthermore, the bottom grid 53 is obtained by ink-jet printing through carbon nanotube ink, so that the use amount of a photomask is reduced, and the cost is reduced.
In addition, in the conventional technology, for preparing graphene in a large area, a commonly used technology with good performance of the obtained graphene is mainly a Chemical Vapor Deposition (CVD) method, and the process of manufacturing the TFT device by using the method mainly includes depositing graphene on a metal substrate such as copper/nickel by the CVD method, etching away the metal substrate to obtain a graphene film, and transferring the graphene film to a substrate on which a desired film has been deposited by Roll-to-Roll (Roll) or other methods, so as to assemble the TFT device.
According to the TFT substrate and the manufacturing method thereof, the metal base 50 for depositing the graphene 30 is directly reused as a raw material for manufacturing the source electrode 11, the top gate electrode 13 and the drain electrode 15, so that the manufacturing process is simplified and the cost is reduced.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and it is therefore to be understood that the invention is not limited by the scope of the appended claims.
Claims (10)
1. A method of manufacturing a TFT substrate, comprising:
step S101, providing a metal substrate, and forming a gate insulation layer on the metal substrate to obtain a first primary structure;
step S102, depositing on the first primary structure to form graphene, wherein the graphene comprises a first graphene layer and a second graphene layer which are connected, the second graphene layer and part of the first graphene layer form double-layer graphene serving as an active layer, and the double-layer graphene is located on the gate insulating layer;
step S103, forming an organic insulating layer on the first graphene layer and the second graphene layer;
step S104, forming a bottom grid electrode on the organic insulating layer to obtain a second primary structure;
step S105, turning the second primary structure up and down to enable the bottom grid to be located at the lowermost layer and the metal substrate to be located at the uppermost layer;
step S106, etching the metal substrate to form a source electrode, a top grid electrode and a drain electrode, wherein the source electrode and the drain electrode are connected with the first graphene layer, and the top grid electrode is connected with the grid electrode insulating layer.
2. The manufacturing method according to claim 1, wherein: in the step S101, the following steps are included:
providing the metal substrate, and depositing and forming a non-pattern inorganic insulating layer on the metal substrate;
forming a patterned first photoresist layer on the inorganic insulating layer;
forming the patterned gate insulating layer through a curing process;
and stripping the first photoresist layer to form the first primary structure.
3. The manufacturing method according to claim 1, wherein: in step S106, the following steps are included:
forming a patterned second photoresist layer on one surface of the metal substrate, which is far away from the gate insulation layer;
etching the metal substrate to obtain the source electrode, the top grid electrode and the drain electrode;
and stripping the second photoresist layer.
4. The manufacturing method according to claim 1, wherein: the metal substrate is made of copper or nickel.
5. The manufacturing method according to claim 1, wherein: the gate insulating layer is made of one of silicon dioxide, yttrium oxide and hafnium oxide.
6. The manufacturing method according to claim 1, wherein: the organic insulating layer is made of polymethyl methacrylate.
7. The manufacturing method according to claim 1, wherein: in step S102, the graphene is deposited by a plasma enhanced chemical vapor deposition method.
8. The utility model provides a TFT base plate, its includes bottom gate, organic insulating layer, graphite alkene, gate insulating layer, source electrode, top grid and drain electrode, the bottom gate organic insulating layer graphite alkene reaches the gate insulating layer is range upon range of setting, its characterized in that in proper order: the graphene comprises a first graphene layer and a second graphene layer which are connected, the first graphene layer is arranged on the organic insulating layer, the first graphene layer is connected with the source electrode and the drain electrode, the second graphene layer and part of the first graphene layer form double-layer graphene serving as an active layer, the double-layer graphene is clamped between the organic insulating layer and the grid insulating layer, and the top grid is connected with the grid insulating layer.
9. The TFT substrate of claim 8, wherein: the organic insulating layer forms an accommodating groove, the gate insulating layer is accommodated in the accommodating groove, and the double-layer graphene is arranged at the bottom of the accommodating groove, which is adjacent to the organic insulating layer.
10. The TFT substrate of claim 9, wherein: the organic insulating layer comprises a first surface, a second surface, a third surface, a fourth surface and a fifth surface which are sequentially connected, the second surface, the third surface and the fourth surface enclose the accommodating groove, a first side face of the grid insulating layer is arranged close to the third surface, the first graphene layer is connected with the first surface, the second surface, the third surface, the fourth surface and the fifth surface, the second graphene layer is clamped between the third surface and the first graphene layer, the source electrode is located on the first surface, and the drain electrode is located on the fifth surface.
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