CN107993981A - TFT substrate and its manufacture method - Google Patents
TFT substrate and its manufacture method Download PDFInfo
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- CN107993981A CN107993981A CN201711178374.2A CN201711178374A CN107993981A CN 107993981 A CN107993981 A CN 107993981A CN 201711178374 A CN201711178374 A CN 201711178374A CN 107993981 A CN107993981 A CN 107993981A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
- H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Abstract
A kind of manufacture method of TFT substrate.Metallic substrates are provided first and are formed on gate insulator, obtain the first primary structure.Deposition forms graphene on the first primary structure, and graphene includes the first graphene layer and the second graphene layer that connection is set, and the second graphene layer forms bilayer graphene with the first graphene layer of part and is used as active layer, and bilayer graphene is located on gate insulator.Organic insulator is formed on graphene.Bottom-gate is formed on organic insulator, obtains the second primary structure.Second primary structure is spun upside down, bottom-gate is located at orlop, metallic substrates are located at the superiors.Etch metallic substrates and form source electrode, top-gated pole and drain electrode.Source electrode and drain electrode are connected with the first graphene layer, reduce the contact resistance between source, drain electrode and bilayer graphene.Present invention also offers a kind of TFT substrate.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of TFT substrate and its manufacture method.
Background technology
In Active Matrix LCD At technology, each pixel is by integrating thin film transistor (TFT) (Thin Film behind
Transistor, TFT) it is driven, so as to realize the Showing Effectiveness On Screen of high speed, high brightness, high contrast.It is common
TFT be usually made of three electrode of gate/source/drain electrode (Gate/Source/Drain), insulating layer and semiconductor layer.
Graphene, as nano material most thin, most hard in the world is currently known, because it has good conductive regulation and control
Property, mechanical property, thermal conduction characteristic, so that as one of current research hot spot.Graphene is high as a kind of very thin conductivity
New material, there is very big potential to be applied in electronic component/transistor.Root it is reported that graphene film have it is extremely low
Square resistance (<100 Ω/), but after overdoping, and the two-dimentional insulating materials of broadband system can be formed, thus graphite
Alkene can form the characteristic of N-shaped or p-type semiconductor, can be applied in the TFT devices of display industry after certain processing.So
And the adjustment of this method treatment process is difficult, performance is difficult to ensure that, it is more difficult to be applied to display industry TFT devices.
The content of the invention
In order to solve foregoing problems, the present invention provides a kind of TFT substrate and its manufacture method.
A kind of manufacture method of TFT substrate, comprises the following steps：
Step S101, there is provided metallic substrates, and gate insulator is formed in the metallic substrates, obtain the first primary knot
Structure；
Step S102, deposition forms graphene on first primary structure, and the graphene includes what connection was set
First graphene layer and the second graphene layer, second graphene layer form double-layer graphite with part first graphene layer
Alkene is used as active layer, and the bilayer graphene is located on the gate insulator；
Step S103, in forming organic insulator on first graphene layer and second graphene layer；
Step S104, in forming bottom-gate on the organic insulator, obtains the second primary structure；
Step S105, second primary structure is spun upside down, and the bottom-gate is located at orlop, the gold
Belong to substrate and be located at the superiors；
Step S106, etches the metallic substrates and forms source electrode, top-gated pole and drain electrode, wherein, the source electrode and the leakage
Pole is connected with first graphene layer, and the top-gated pole is connected with the gate insulator.
Further, in the step S101, comprise the following steps：
The metallic substrates are provided, and planless inorganic insulation layer is formed in deposition in the metallic substrates；
In forming patterned first photoresist layer on the inorganic insulation layer；
The patterned gate insulator is formed by curing process；
Peel off first photoresist layer and form first primary structure.
Further, in the step S107, comprise the following steps：In the metallic substrates away from the gate insulator
Patterned second photoresist layer is formed in the one side of layer；The metallic substrates are etched, obtain the source electrode, the top-gated
Pole and the drain electrode；Peel off second photoresist layer.
Further, the material of the metallic substrates is copper or nickel.
Further, the material of the gate insulator is one kind in silica, yittrium oxide, hafnium oxide.
Further, the material of the organic insulator is polymethyl methacrylate.
Further, in step s 103, the graphene is deposited by plasma reinforced chemical vapour deposition method.
A kind of TFT substrate, it includes bottom-gate, organic insulator, graphene, gate insulator, source electrode, top-gated pole and leakage
Pole, the bottom-gate, the organic insulator, the graphene and the gate insulator are in be stacked successively, the stone
Black alkene includes the first graphene layer and the second graphene layer that connection is set, and first graphene layer is arranged on the organic insulation
On layer, first graphene layer is connected with the source electrode, the drain electrode, second graphene layer and part first stone
Black alkene layer forms bilayer graphene and is used as active layer, and the bilayer graphene is located in the organic insulator and the grid is exhausted
Between edge layer, the top-gated pole is connected with the gate insulator.
Further, the organic insulator forms holding tank, and the gate insulator is contained in the holding tank, described
Bilayer graphene is arranged on the holding tank adjacent to the bottom of the organic insulator.
Further, the organic insulator include being sequentially connected the first surface of setting, second surface, the 3rd surface,
4th surface and the 5th surface, the second surface, the 3rd surface, the 4th surface surround the holding tank, the first side
Neighbouring 3rd surface is set, first graphene layer and the first surface, the second surface, the 3rd table
Face, the 4th surface and the 5th surface connection, second graphene layer are located in the 3rd surface and described the
Between one graphene layer, the source electrode is located on the first surface, and the drain electrode is on the 5th surface.
Above-mentioned TFT substrate and its manufacture method, in setting the first graphene layer and the second graphene layer shape on gate insulator
Into bilayer graphene as active layer, to control vertical electric field by two grids in top-gated pole and bottom-gate, play the switch of TFT
Effect.The source electrode and it is described drain electrode be connected by single-layer graphene with bilayer graphene, and then can reduce the source electrode and
Contact resistance between active layer and between the drain electrode and the active layer, improves the performance of the TFT substrate.Further
Ground, by making the source electrode, top-gated pole and the former material of drain electrode by being reused for the metallic substrates of deposited graphite alkene
Material, thus simplify preparation process and reduce cost.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, without creative efforts, can be with
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is the sectional view of TFT substrate provided in an embodiment of the present invention.
Fig. 2 is the manufacture method flow chart of TFT substrate provided in an embodiment of the present invention.
Fig. 3 is the sectional view of the first primary structure formed in the step S101 shown in Fig. 2.
Fig. 4 is the sectional view of the structure formed in the step S102 shown in Fig. 2.
Fig. 5 is the sectional view of the structure formed in the step S103 shown in Fig. 2.
Fig. 6 is the sectional view of the second primary structure formed in the step S104 shown in Fig. 2.
Fig. 7 is the sectional view after the second primary structure shown in Fig. 6 is spun upside down.
Fig. 8 is the flow chart of the step S101 of the manufacture method of TFT substrate.
Fig. 9 is the sectional view of the structure formed in the step S81 shown in Fig. 8.
Figure 10 is the sectional view of the structure formed in the step S82 shown in Fig. 8.
Figure 11 is the sectional view of the structure formed in the step S83 shown in Fig. 8.
Figure 12 is the flow chart of the step S106 of the manufacture method of TFT substrate.
Figure 13 is the sectional view of the structure formed in the step S91 shown in Figure 12.
Figure 14 is the sectional view of the structure formed in the step S92 shown in Figure 12.
Embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment, belongs to the scope of protection of the invention.
Referring to Fig. 1, it is a kind of TFT substrate 1 provided in an embodiment of the present invention.The TFT substrate 1 include bottom-gate 10,
Organic insulator 20, graphene 30, gate insulator 40, source electrode 51, top-gated pole 53 and drain electrode 55.
Specifically, in the present embodiment, the bottom-gate 10 is carbon nanotube layer, it will be understood that the bottom-gate 10 may be used also
Think one or more heap stack combinations in molybdenum (Mo), aluminium (Al), copper (Cu).
The organic insulator 20 is arranged in the bottom-gate 10.The thickness of the organic insulator 20 is 1 μm.It is described to have
The dielectric constant of machine insulating layer 20 need to reach 3 times of permittivity of vacuums, such as the material of the organic insulator 20 is poly- methyl
Methyl acrylate.
Further, the organic insulator 20 includes first surface 21, the second surface the 22, the 3rd for being sequentially connected setting
Surface 23, the 4th surface 24 and the 5th surface 25.The second surface 22, the 3rd surface 23, the 4th surface 24 surround holding tank
27。
The graphene 30 is arranged on the organic insulator 20 and away from the bottom-gate 10, and is partially accommodated in the appearance
Receive groove 27.The graphene 30 is bilayer graphene in the 3rd surface 23, in the first surface 21, the second surface
22nd, the 4th surface 24 and the 5th surface 25 are single-layer graphene.Specifically, the graphene 30 includes the first graphite
Alkene layer 35 and the second graphene layer 37 being connected with first graphene layer 35.First graphene layer 35 is arranged on described the
One surface 21, the second surface 22, the 3rd surface 23, the 4th surface 24 and the 5th surface 25.Described
Two graphene layers 37 are connected with first graphene layer 35.Second graphene layer 37 is located in first graphene layer
Between 35 and the 3rd surface 22.The bilayer graphene is as active layer.
The gate insulator 40 is arranged on the graphene 30 and is contained in the holding tank 27.It is described in the present embodiment
Gate insulator 40 is silicon dioxide insulating layer.The gate insulator 20 is not limited to earth silicon material, it can be by it
He substitutes inorganic insulating material, such as yittrium oxide (Y2O3), hafnium oxide (HfO2).The gate insulator 40 includes opposite set
The first side 41 and second side 43 put, the first side 41 are set adjacent to the 3rd surface 23 and the second graphene layer 37
Put.In other words, second graphene layer 37 corresponds to the first side 41 and sets.The bilayer graphene is arranged on the appearance
Groove 27 is received adjacent to the bottom of the organic insulator 20.
The source electrode 51 is arranged on first graphene layer 35 and is connected with first graphene layer 35.The source electrode 51
Above the first surface 21.The source electrode 51 is away from the organic insulator 20.
The top-gated pole 53 is arranged on the gate insulator 40 and away from the organic insulator 20.
The drain electrode 55 is connected in first graphene layer 35 and with first graphene layer 35.The drain electrode 55
In on the 5th surface 21.The drain electrode 55 is away from the organic insulator 20.
The source electrode 51 and the drain electrode 55 and are connected as between the bilayer graphene of active layer by single-layer graphene,
To reduce between the source electrode 51 and active layer, and the contact resistance between the drain electrode 55 and active layer.In the present embodiment, institute
Source electrode 51, the drain electrode 55 and the top-gated pole 53 is stated to be made for copper (Au).
Referring to Fig. 2, it is a kind of TFT substrate manufacture method provided in an embodiment of the present invention, it comprises the following steps：
Step S101, referring to Fig. 3, providing metallic substrates 50, and forms gate insulator in the metallic substrates 50
40, obtain the first primary structure 100.
Specifically, the material of the metallic substrates 50 can not only be used for base material and prepare graphene film for deposition, together
When also need possess conduction property, for being subsequently used as electrode material, such as the metal material such as copper (Cu) or nickel (Ni).This implementation
In example, copper (Cu) is selected to be used as metallic substrates, its thickness is about 1 μm (micron).
The gate insulator 40 is silicon dioxide insulating layer.The gate insulator 40 is not limited to silica material
Material, it can be substituted by other inorganic insulating materials, such as yittrium oxide (Y2O3), hafnium oxide (HfO2).The gate insulator
40 first sides 41 and second side 43 including being oppositely arranged, the first side 41 are set away from the metallic substrates 50.
First primary structure 100 includes first area 102 and the second area 103 being connected with each other, firstth area
Domain 102 is 41 region of first side, and the second area 103 is first primary structure 100 adjacent to first side
The side remainder in face 43.
Step S102, referring to Fig. 4, forming graphene 30, the graphene in deposition on first primary structure 100
30 include the first graphene layers 35 and the second graphene layer 37 that connection is set, second graphene layer 37 and part described the
One graphene layer 35 forms bilayer graphene and is located at as active layer, the bilayer graphene on the gate insulator 40.
Specifically, the graphene 30 is bilayer graphene in the first area 102, is in the second area 103
Single-layer graphene.First graphene layer 35 is formed at the first area 102 and the second area 103.Described second
Graphene layer 37 is formed at the first area 102.Second graphene layer 37, first graphene layer 35, the grid
Pole insulating layer 40 stacks gradually.In other words, bilayer graphene is formed in the first side 41 of the gate insulator 40.
Pass through plasma reinforced chemical vapour deposition method (Plasma Enhanced Chemical Vapor
Deposition, PECVD) the deposition graphene.In the present embodiment, in preparation process, by control parameter, due to urging for Cu
Change acts on, and only in the first area 101, deposition obtains bilayer graphene, and single-layer graphene is obtained in the second area 103.
Step S103, referring to Fig. 5, organic in being formed on first graphene layer 35 and second graphene layer 37
Insulating layer 20.
Second graphene layer 37 is located between first graphene layer 35 and the organic insulator 20.
The organic insulator 20 is by solution coating and is formed by curing.The thickness of the organic insulator 20 is about 1 μm.
The dielectric constant of the organic insulator 20 need to reach 3 times of permittivity of vacuums, such as the material of the organic insulator 20 is
Polymethyl methacrylate.
Further, the organic insulator 20 includes first surface 21, the second surface the 22, the 3rd for being sequentially connected setting
Surface 23, the 4th surface 24 and the 5th surface 25.The second surface 22, the 3rd surface 23, the 4th surface 24 surround holding tank
27.The graphene 30 is partially accommodated in the holding tank 27.The graphene 30 is double-layer graphite in the 3rd surface 23
Alkene, in the first surface 21, the second surface 22, the 4th surface 24 and the 5th surface 25 be mono-layer graphite
Alkene.
First graphene layer 35 is adjacent to the first surface 21, the second surface 22, the 3rd surface 23, institute
The 4th surface 24 and the 5th surface 25 is stated to set.
Second graphene layer 37 is located between first graphene layer 35 and the 3rd surface 22.
Step S104, referring to Fig. 6, in forming bottom-gate 10 on the organic insulator 20, obtains the second primary structure
200。
In the present embodiment, the bottom-gate 10 is carbon nanotube layer, passes through carbon nanotubes ink in the organic insulator 20
Water obtains patterned carbon nanotube layer using ink-jet printing process.
It is appreciated that the bottom-gate 10 can also be one or more storehouses in molybdenum (Mo), aluminium (Al), copper (Cu)
Combination.
Step S105, referring to Fig. 7, second primary structure 200 is spun upside down, makes the bottom-gate 10
In orlop, the metallic substrates 50 are located at the superiors.
Step S106, referring to Fig. 1, etching metallic substrates 50 form source electrode 51, top-gated pole 53 and drain electrode 55, obtain
TFT substrate 1, wherein, the source electrode 51 and the drain electrode 55 are connected with first graphene layer 35, and the top-gated pole 53 is arranged on
The second side 43 of the gate insulator 40.
The source electrode 51 is located on the first surface 21, and the drain electrode 55 is on the 5th surface 25.
Further, in step S101, i.e. provide metallic substrates 50, gate insulator is formed in the metallic substrates 50
In the step of layer 40, referring to Fig. 8, specifically including following steps：
Step S81, referring to Fig. 9, providing the metallic substrates 50, and forms without figure in deposition in the metallic substrates 50
The inorganic insulation layer 46 of shape.
Step S82, referring to Fig. 10, in forming patterned first photoresist layer 47 on the inorganic insulation layer 46.
Specifically, by way of one of light shield-coating optical cement-development, patterned second photoresist layer 91 is obtained.
Step S83, please refers to Fig.1 1, and patterned gate insulator 40 is formed by curing process.
Step S84, referring to Fig. 3, peels off first photoresist layer 47 and forms first primary structure 100.
In step S84, in the present embodiment, using the blocking solution stripping to the 50 corrosion-free effect of metallic substrates
From first photoresist layer 47.
Further, in step 106, i.e. source electrode 51, top-gated pole 53 and drain electrode 55 are formed in the metallic substrates 50
The step of in, please refer to Fig.1 2, specifically include following steps：
Step S91, please refers to Fig.1 3, schemes in being formed in one side of the metallic substrates 50 away from the gate insulator 40
Second photoresist layer 91 of shape.
Specifically, by way of second light shield-coating optical cement-development, patterned second photoresist layer 91 is obtained.
Step S92, please refers to Fig.1 4, and the metallic substrates 50 are etched, and obtains source electrode 51, top-gated pole 53 and drain electrode
55。
Step S93, peels off second photoresist layer 91.
The TFT substrate and its manufacture method that the application provides, in setting the first stone in the first side 41 of gate insulator 40
Black 35 and second graphene layer 37 of alkene layer forms bilayer graphene to pass through as active layer, the source electrode 51 and the drain electrode 55
Single-layer graphene is connected with bilayer graphene, can reduce between the source electrode 51 and active layer and the drain electrode 55 has with described
Contact resistance between active layer, improves the performance of the TFT substrate 1.What is more, using the bilayer graphene as active
Layer, controls vertical electric field by 10 two grids of top-gated machine 53 and bottom-gate, plays the on-off action of TFT.Further, it is described
Bottom-gate 53 is obtained by carbon nanotube ink using ink-jet printing process, therefore reduces light shield usage amount, reduces cost.
In addition, in traditional technology, graphene is prepared for large area, it is more common and obtained graphene better performances
Technology is mainly chemical vapour deposition technique (Chemical Vapor Deposition, CVD), and TFT devices are made using this method
Process be mainly first by CVD method deposited graphite alkene in metallic substrates such as copper/nickel, then to etch away metallic substrates and obtain
Graphene film, then needed for the graphene film is transferred to by volume to volume (Roll to Roll) or other modes has deposited
In the substrate of film, so as to be assembled into TFT devices, this method is grown with the cycle, complex process, and metallic substrates expend big cost
The shortcomings of high.
The application provide TFT substrate and its manufacture method, directly by for the metallic substrates 50 of deposited graphite alkene 30 again
The secondary raw material for making the source electrode 11, top-gated pole 13 and drain electrode 15 using becoming, so as to simplify manufacturing process and reduce into
This.
The above disclosure is only the preferred embodiments of the present invention, cannot limit the right model of the present invention with this certainly
Enclose, therefore equivalent variations made according to the claims of the present invention, it is still within the scope of the present invention.
Claims (10)
1. a kind of manufacture method of TFT substrate, it is characterised in that comprise the following steps：
Step S101, there is provided metallic substrates, and gate insulator is formed in the metallic substrates, obtain the first primary structure；
Step S102, deposition forms graphene on first primary structure, and the graphene includes first that connection is set
Graphene layer and the second graphene layer, second graphene layer form bilayer graphene with part first graphene layer and use
Make active layer, the bilayer graphene is located on the gate insulator；
Step S103, in forming organic insulator on first graphene layer and second graphene layer；
Step S104, in forming bottom-gate on the organic insulator, obtains the second primary structure；
Step S105, second primary structure is spun upside down, and the bottom-gate is located at orlop, the Metal Substrate
Bottom is located at the superiors；
Step S106, etches the metallic substrates and forms source electrode, top-gated pole and drain electrode, wherein, the source electrode and the drain electrode with
The first graphene layer connection, the top-gated pole is connected with the gate insulator.
2. manufacture method as claimed in claim 1, it is characterised in that：In the step S101, comprise the following steps：
The metallic substrates are provided, and planless inorganic insulation layer is formed in deposition in the metallic substrates；
In forming patterned first photoresist layer on the inorganic insulation layer；
The patterned gate insulator is formed by curing process；
Peel off first photoresist layer and form first primary structure.
3. manufacture method as claimed in claim 1, it is characterised in that：In the step S107, comprise the following steps：
In forming patterned second photoresist layer in one side of the metallic substrates away from the gate insulator；
The metallic substrates are etched, obtain the source electrode, the top-gated pole and the drain electrode；
Peel off second photoresist layer.
4. manufacture method as claimed in claim 1, it is characterised in that：The material of the metallic substrates is copper or nickel.
5. manufacture method as claimed in claim 1, it is characterised in that：The material of the gate insulator is silica, oxygen
Change one kind in yttrium, hafnium oxide.
6. manufacture method as claimed in claim 1, it is characterised in that：The material of the organic insulator is polymethylacrylic acid
Methyl esters.
7. manufacture method as claimed in claim 1, it is characterised in that：In step s 103, plasma-reinforced chemical gas is passed through
Graphene described in phase deposition method.
8. a kind of TFT substrate, it includes bottom-gate, organic insulator, graphene, gate insulator, source electrode, top-gated pole and leakage
Pole, the bottom-gate, the organic insulator, the graphene and the gate insulator are in be stacked successively, its feature
It is：The graphene includes the first graphene layer and the second graphene layer that connection is set, and first graphene layer is arranged on
On the organic insulator, first graphene layer is connected with the source electrode, the drain electrode, second graphene layer and portion
Divide first graphene layer to form bilayer graphene and be used as active layer, the bilayer graphene is located in the organic insulator
Between the gate insulator, the top-gated pole is connected with the gate insulator.
9. TFT substrate as claimed in claim 8, it is characterised in that：The organic insulator forms holding tank, and the grid is exhausted
Edge layer is contained in the holding tank, and the bilayer graphene is arranged on the holding tank adjacent to the bottom of the organic insulator.
10. TFT substrate as claimed in claim 9, it is characterised in that：The organic insulator includes being sequentially connected the of setting
One surface, second surface, the 3rd surface, the 4th surface and the 5th surface, the second surface, the 3rd surface, the 4th surface are enclosed
Into the holding tank, the first side is set adjacent to the 3rd surface, first graphene layer and the first surface,
The second surface, the 3rd surface, the 4th surface and the 5th surface connection, the second graphene layer sandwiched
Between the 3rd surface and first graphene layer, the source electrode is located on the first surface, and the drain electrode is located at
On 5th surface.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711178374.2A CN107993981B (en) | 2017-11-22 | 2017-11-22 | TFT substrate and method for manufacturing the same |
| PCT/CN2017/114252 WO2019100438A1 (en) | 2017-11-22 | 2017-12-01 | Tft substrate and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711178374.2A CN107993981B (en) | 2017-11-22 | 2017-11-22 | TFT substrate and method for manufacturing the same |
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| CN110729184A (en) * | 2019-10-24 | 2020-01-24 | 宁波石墨烯创新中心有限公司 | Thin film transistor, and manufacturing method and device thereof |
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| CN107993981B (en) | 2020-11-06 |
| WO2019100438A1 (en) | 2019-05-31 |
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