CN107993928B - Method for inhibiting copper electromigration in wafer hybrid bonding - Google Patents
Method for inhibiting copper electromigration in wafer hybrid bonding Download PDFInfo
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- CN107993928B CN107993928B CN201711154880.8A CN201711154880A CN107993928B CN 107993928 B CN107993928 B CN 107993928B CN 201711154880 A CN201711154880 A CN 201711154880A CN 107993928 B CN107993928 B CN 107993928B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
The invention discloses a method for inhibiting copper electromigration in wafer hybrid bonding, which comprises the following steps: forming a metal layer over at least two semiconductor substrates; performing chemical mechanical polishing on the semiconductor substrate to form a plurality of recesses on the metal layer; plating graphene on the metal layer having the plurality of recesses; and performing heat treatment on the at least two semiconductor substrates to enable the metal layers to be bonded through the graphene. According to the method, firstly, a recess with a specific height is controlled to be formed, then the single-layer graphene is accurately transferred into the recess to form the covering layer, then wafer bonding is carried out through a wafer hybrid bonding method, and finally heat treatment is carried out at a certain temperature, so that electromigration of copper can be inhibited.
Description
Technical Field
The invention relates to a wafer hybrid bonding method, in particular to a method for inhibiting copper electromigration in wafer hybrid bonding.
Background
New improvements for wafer bonding are increasingly important in 3D IC structures. Upon wafer bonding, two semiconductor wafers are bonded together to form a three-dimensional stack without the need for an intervening substrate or device. In applications requiring two different wafer types, the method may provide a single device with two functional devices in one package. In one particular application, a CMOS image sensor, a substrate including an image sensor array, may be bonded onto a circuit wafer to provide a 3D IC system including all of the circuitry required to implement the image sensor in the same circuit board area as the sensor array, providing a complete image sensing scheme in a single packaged integrated circuit device.
Previously known wafer bonding methods include oxide-oxide or fusion bonding, and metal-to-metal bonding using thermocompression bonding, which is performed at high pressure and using high temperature. These prior methods introduce high mechanical and thermal stresses on the device or do not provide the required metal-to-metal connections.
The prior art, such as CN104051288, uses the following method to realize bonding: forming a metal pad layer in the dielectric layer over the at least two semiconductor substrates; performing chemical mechanical polishing on the semiconductor substrates to expose surfaces of the metal pad layers and planarizing the dielectric layer to form bonding surfaces on each of the semiconductor substrates; performing an oxidation process on the at least two semiconductor substrates to oxidize the metal pad layer, thereby forming a metal oxide; performing etching to remove the metal oxide, exposing a surface of the metal pad layer from the bonding surface of the dielectric layer of each of the at least two semiconductor substrates; physically contacting the bonding surfaces of the at least two semiconductor substrates; and performing thermal annealing to form a bond between the metal pad layers of the semiconductor substrate. The use of the above method has the following disadvantages: before annealing, the metal layer has a recess generated in the chemical mechanical polishing process, and the recess cannot be completely filled after copper is heated and expanded in the bonding process, so that a plurality of holes are formed among copper layers, so that the copper cannot be effectively interconnected, and the electrical connection stability of a finished product is reduced.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a method for inhibiting copper electromigration in wafer hybrid bonding, thereby overcoming the defects of the prior art.
In order to achieve the above object, the present invention provides a method for inhibiting copper electromigration in wafer hybrid bonding, which is characterized in that: the method comprises the following steps: forming a metal layer over at least two semiconductor substrates; performing chemical mechanical polishing on the semiconductor substrate to form a plurality of recesses on the metal layer; plating graphene on the metal layer having the plurality of recesses; and performing heat treatment on the at least two semiconductor substrates to enable the metal layers to be bonded through the graphene.
Preferably, in the above technical solution, the metal layer is a copper layer.
Preferably, in the above technical solution, the process of forming the metal layer is physical vapor deposition.
Preferably, in the above technical solution, a specific method for plating graphene is: the single layer graphene is plated into the depressions of the metal layer using a graphene dispersion.
Preferably, in the above technical solution, the thickness of the graphene is about 0.34 nm.
Compared with the prior art, the invention has the following beneficial effects: the invention is further improved on the basis of the prior process, and the dispersion solution of the single-layer graphene is transferred into the recess by a plating method to form a covering layer, so that copper in two wafers is interconnected by the graphene. The work function of single-layer graphene is 4.65, the work function of Cu is 4.6, the potential barrier between the work functions is relatively small, and the resistivity of the single-layer graphene is 10-6Ω · cm, the contact resistance increases only to a small extent. The thermal expansion rate of the graphene is a negative value within the range of 0-1200K, so that the thermal expansion of Cu can be inhibited, and the recess height can be reduced. Single-layer graphene is a two-dimensional layered structure composed of carbon atoms, and has a thickness of about 0.34nm, which is the diameter of a single atom, and thus does not have a great influence on the height of a depression after plating. In summary, the formation of a recess with a specific height is controlled first, then the single-layer graphene is precisely transferred into the recess to form a capping layer, and then the wafer bonding is performed by the wafer hybrid bonding methodFinally, heat treatment is carried out at a certain temperature, so that electromigration of copper can be inhibited.
Drawings
Fig. 1a-1d are schematic diagrams illustrating the steps of wafer hybrid bonding in the prior art.
Fig. 2a-2b are schematic views of a prior art aperture.
Fig. 3a, 3b, and 3c are schematic diagrams illustrating steps of a method for suppressing electromigration of copper in wafer hybrid bonding according to an embodiment of the present invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
The following first describes a prior art wafer bonding method that provides a strong connection at the interface between two substrates. The substrate is a semiconductor substrate, and the substrate may be a semiconductor wafer. The substrate may include a donor wafer that provides metal connections and via connections, which may be bonded to another device wafer, and the substrate of the donor wafer may then be ground away using a mechanical grinding or CMP process, leaving a metal layer bonded to the device wafer. Multiple wafers may be bonded to form a 3D IC structure having multiple layers. A Chemical Mechanical Process (CMP) is used to expose the metal pads on the bonding surfaces of the two substrates and planarize the two surfaces. Then, a metal oxide layer is formed by oxidizing the exposed metal pad. During the oxidation process, the process conditions are carefully controlled. After the oxidation process, the metal oxide is removed from the metal pad using a well-controlled etching process, exposing the surface. A wet etch process is used. The control of the oxidation process and the wet etch process used provides a very matched surface profile for the metal pad. The two substrates are then aligned in a face-to-face relationship and the corresponding metal pads are brought into proximity with each other while the surrounding dielectric materials of the two substrates are in contact with each other. Fusion bonding may occur between the contacting dielectric layers. A hybrid bonding process is performed using an annealing process to create a bond between the metal pads and enhance a bond between the dielectric layers. Because the metal pads have matching surface profiles within certain parameters, the metal pads form a strong bond even at relatively low process temperatures and without the need for high mechanical pressures. The dielectric material is selected from the group consisting of oxides such as SiO2, nitrides such as SiN, oxynitrides (SiON), and high-k dielectrics used in semiconductor devices. Copper metal pads surrounded by dielectric material are formed using a damascene or dual damascene metallization scheme. After Chemical Mechanical Polishing (CMP) and planarization, the substrate undergoes an oxidation process. The copper oxide was formed using an O2 plasma. Other oxidation processes may also be used. A steam oxidation process such as In Situ Steam Generation (ISSG) may be used. Then, copper oxide removal is performed by a wet etching process. A dilute HF etch is used. The wet etch is selected from oxide etchants including DHF, HCl, HCOOH, citric acid at a concentration of 2%. The temperature of the etching process is less than 250 ℃. After the copper oxide is removed, the substrate is checked for copper pad profile matching. The pads may be slightly recessed from the surface of the dielectric material. The formation of copper oxide after a well-controlled etching process reduces or eliminates non-uniform surfaces, such as dishing, resulting from the CMP process. The control of the process allows to produce a slightly convex or concave and very uniform surface on the surface of the copper pad. By using the embodiment method, the copper pad has an almost uniform surface. The recess depth of the copper pads is well matched between the copper pads on the top substrate and the corresponding copper pads on the bottom substrate. The top and bottom substrates, selected by the well-matched copper pad profile, are brought into alignment and then into contact, the dielectric layers are brought into physical contact and the copper pads of the top and bottom substrates are slightly spaced apart. The dielectric surfaces of the substrates are in substantial contact. Fusion bonding of the dielectric layers may begin. Once the substrate is brought into physical contact, a relatively low temperature anneal is performed. During annealing, the individual copper pads form a seamless joint. The bond between the dielectric layers will continue or the bond strength will continue to increase during the anneal. A strong bond is formed when the surface profile of the copper pad is well matched and the metal pad recess depth is within a certain predetermined range. This is referred to as "seamless" bonding, where the copper material appears uniform across the bonding interface. The dielectric surfaces are also bonded in a hybrid bonding process.
Referring to fig. 1a-1d, there are schematic diagrams illustrating the steps of wafer hybrid bonding in the prior art, the main steps of wafer hybrid bonding in the prior art include: providing a wafer 101 with a trench 102 (fig. 1a), depositing a metallic copper layer 103 in the trench 102 of the wafer 101 (fig. 1 b); performing chemical mechanical polishing on the metallic copper layer 103 to create a recess 104; physically contacting the bonding surfaces of wafer 101; and performing thermal annealing to form a bond between the metallic copper layers 103 of the wafer 101. During the bonding process, since the copper layer 103 does not completely fill the recess 104 after thermal expansion, several voids 105 will appear between the copper layers 103, as shown in fig. 2a-2 b.
Fig. 3a-3c are schematic diagrams illustrating steps of a method for suppressing electromigration of copper in wafer hybrid bonding according to an embodiment of the present application, the method including the steps of: forming a metal layer 303 over at least two semiconductor substrates 301; performing chemical mechanical polishing on the semiconductor substrate 301 to form a plurality of recesses 104 on the metal layer 303; plating graphene 302 on the metal layer 303 having the plurality of recesses 104; and performing heat treatment on the at least two semiconductor substrates 301 so that the metal layers 303 are bonded through the graphene 302. In one embodiment, metal layer 303 is a copper layer. In one embodiment, the process of forming metal layer 303 is physical vapor deposition. In one embodiment, a specific method of plating the graphene 302 is: the single layer graphene is plated into the depressions of the metal layer using a graphene dispersion. In one embodiment, the graphene is about 0.34nm thick. As can be seen from fig. 3c, after the bonding of the wafer according to the present invention, the holes are completely eliminated, and the holes are filled with graphene, which is conductive, thereby preventing the occurrence of poor connection.
The invention has the advantages that: the dispersion solution of single-layer graphene is transferred into the recess by plating to form a cover coating layer, so that copper in the two wafers is interconnected by the graphene. The work function of single-layer graphene is 4.65, the work function of Cu is 4.6, the potential barrier between the work functions is relatively small, and the resistivity of the single-layer graphene is 10-6Ω · cm, the contact resistance increases only to a small extent. The thermal expansion rate of the graphene is a negative value within the range of 0-1200K, so that the thermal expansion of Cu can be inhibited, and the recess height can be reduced. Single-layer graphene is a two-dimensional layered structure composed of carbon atoms, and has a thickness of about 0.34nm, which is the diameter of a single atom, and thus does not have a great influence on the height of a depression after plating. In summary, firstly, a recess with a specific height is formed, then the single-layer graphene is accurately transferred into the recess to form a covering layer, then wafer bonding is carried out by a wafer hybrid bonding method, and finally heat treatment is carried out at a certain temperature, so that electromigration of copper can be inhibited.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (3)
1. A method for inhibiting copper electromigration in wafer hybrid bonding is characterized in that: the method comprises the following steps:
forming a metal layer over at least two semiconductor substrates; the metal layer is a copper layer;
performing chemical mechanical polishing on the semiconductor substrate to form a plurality of recesses on the metal layer;
plating graphene on the metal layer having the plurality of recesses; the specific method for plating graphene is as follows: plating single layer graphene into the depressions of the metal layer using a graphene dispersion; and
and carrying out heat treatment on the at least two semiconductor substrates so that the metal layers are bonded through the graphene.
2. The method of claim 1, wherein: the process for forming the metal layer is physical vapor deposition.
3. The method of claim 1, wherein: the thickness of the graphene is 0.34 nm.
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| CN201711154880.8A CN107993928B (en) | 2017-11-20 | 2017-11-20 | Method for inhibiting copper electromigration in wafer hybrid bonding |
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| CN201711154880.8A CN107993928B (en) | 2017-11-20 | 2017-11-20 | Method for inhibiting copper electromigration in wafer hybrid bonding |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
| US11056348B2 (en) | 2018-04-05 | 2021-07-06 | Invensas Bonding Technologies, Inc. | Bonding surfaces for microelectronics |
| US11393779B2 (en) | 2018-06-13 | 2022-07-19 | Invensas Bonding Technologies, Inc. | Large metal pads over TSV |
| US11749645B2 (en) | 2018-06-13 | 2023-09-05 | Adeia Semiconductor Bonding Technologies Inc. | TSV as pad |
| US11011494B2 (en) | 2018-08-31 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
| CN109148417A (en) * | 2018-09-03 | 2019-01-04 | 长江存储科技有限责任公司 | A kind of hybrid bonded structure and method of wafer |
| US11158573B2 (en) | 2018-10-22 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Interconnect structures |
| US11264357B1 (en) | 2020-10-20 | 2022-03-01 | Invensas Corporation | Mixed exposure for large die |
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| CN104051288A (en) * | 2013-03-15 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Methods for hybrid wafer bonding |
| CN105870089A (en) * | 2015-02-06 | 2016-08-17 | 联测总部私人有限公司 | Reliable interconnect |
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| US8647978B1 (en) * | 2012-07-18 | 2014-02-11 | International Business Machines Corporation | Use of graphene to limit copper surface oxidation, diffusion and electromigration in interconnect structures |
| EP2747132B1 (en) * | 2012-12-18 | 2018-11-21 | IMEC vzw | A method for transferring a graphene sheet to metal contact bumps of a substrate for use in semiconductor device package |
| US9437572B2 (en) * | 2013-12-18 | 2016-09-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive pad structure for hybrid bonding and methods of forming same |
| CN105355620B (en) * | 2015-12-17 | 2018-06-22 | 上海集成电路研发中心有限公司 | A kind of copper interconnection structure and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104051288A (en) * | 2013-03-15 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Methods for hybrid wafer bonding |
| CN105870089A (en) * | 2015-02-06 | 2016-08-17 | 联测总部私人有限公司 | Reliable interconnect |
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