CN107993928A - A kind of method for suppressing the hybrid bonded middle copper electromigration of wafer - Google Patents
A kind of method for suppressing the hybrid bonded middle copper electromigration of wafer Download PDFInfo
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- CN107993928A CN107993928A CN201711154880.8A CN201711154880A CN107993928A CN 107993928 A CN107993928 A CN 107993928A CN 201711154880 A CN201711154880 A CN 201711154880A CN 107993928 A CN107993928 A CN 107993928A
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- graphene
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- copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
The invention discloses a kind of method for suppressing the hybrid bonded middle copper electromigration of wafer, method comprises the following steps：Metal layer is formed at least two Semiconductor substrates；Chemically mechanical polishing is performed to Semiconductor substrate, so as to form multiple depressions on the metal layer；The plating graphene on multiple concave metal layers；And at least two Semiconductor substrates are heat-treated so that metal layer is bonded by graphene.Present invention control first forms the depression of certain height, then single-layer graphene is accurately transferred in depression and forms lid coating, then wafer bonding is carried out by the hybrid bonded method of wafer, is finally heat-treated at a certain temperature, thus can inhibit the electromigration of copper.
Description
Technical field
The present invention relates to a kind of hybrid bonded method of wafer, more particularly to a kind of hybrid bonded middle copper electricity of wafer that suppresses moves
The method of shifting.
Background technology
Become more and more important for newly improving for wafer engagement in 3D IC structures.When wafer engages, intermediary's lining is being not required
In the case of bottom or device, two semiconductor crystal wafers are joined together to form three-dimensional stacked part.Needing two kinds of not isomorphous
In the application of circle type, this method can be provided in an encapsulation individual devices with two function elements.In a spy
In fixed application, the substrate of cmos image sensor including image sensor array can be engaged on circuit wafer, to provide
It is included in the 3D IC systems that all circuits needed for imaging sensor are realized in the board area identical with sensor array,
Complete image sensing solutions are provided in the integrated circuit device of single package.
Previously known wafer joint method includes oxide-oxide or melting engagement and uses hot press
Metal to metal engage, perform the hot press under high pressure and using high temperature.These existing methods introduce on device
High mechanical stress and thermal stress, or required metal cannot be provided and connected to metal.
The prior art as CN104051288 realizes bonding with the following method：In at least two Semiconductor substrates
On dielectric layer in formed metal welding disc layer；Chemically mechanical polishing is performed to the Semiconductor substrate, with the exposure metal
The surface of pad layer, and the dielectric layer is planarized, to form composition surface in each Semiconductor substrate；To described
At least two Semiconductor substrates perform oxidation technology, to aoxidize the metal welding disc layer, so as to form metal oxide；Perform erosion
Carve, to remove the metal oxide, connect described in the dielectric layer of each from least two Semiconductor substrate
Close the surface that the metal welding disc layer is exposed in surface；By the composition surface physics of at least two Semiconductor substrate
Contact；And thermal annealing is performed, engaged with being formed between the metal welding disc layer of the Semiconductor substrate.Use above-mentioned side
There are following defect for method：Before the anneal, there are the depression produced in CMP process in metal layer, in bonding process
In since above-mentioned depression can not be filled up completely after copper expanded by heating, so will appear from several holes between layers of copper so that
Cause copper effectively to interconnect, reduce the electrical connection stability of finished product.
The information for being disclosed in the background section is merely intended to understanding of the increase to the general background of the present invention, without answering
It has been the prior art well known to persons skilled in the art when being considered as recognizing or implying the information structure in any form.
The content of the invention
It is an object of the invention to provide a kind of method for suppressing the hybrid bonded middle copper electromigration of wafer, so as to overcome existing
The shortcomings that redeeming.
To achieve the above object, the present invention provides a kind of method for suppressing the hybrid bonded middle copper electromigration of wafer, it is special
Sign is：Method comprises the following steps：Metal layer is formed at least two Semiconductor substrates；To Semiconductor substrate execution
Mechanical polishing is learned, so as to form multiple depressions on the metal layer；The plating graphene on multiple concave metal layers；And
At least two Semiconductor substrates are heat-treated so that metal layer is bonded by graphene.
Preferably, in above-mentioned technical proposal, metal layer is layers of copper.
Preferably, in above-mentioned technical proposal, the technique for forming metal layer is physical vapour deposition (PVD).
Preferably, in above-mentioned technical proposal, the specific method of plating graphene is：Using graphene dispersing solution by individual layer stone
Black alkene is plated in the depression of metal layer.
Preferably, in above-mentioned technical proposal, the thickness of graphene is about 0.34nm.
Compared with prior art, the present invention has the advantages that：The invention is carried out on existing Process ba- sis
It is further to improve, the dispersion soln of single-layer graphene is transferred in depression by the method for plating and forms one layer of lid coating,
So that the copper in two wafers is interconnected by graphene with realizing.The work function of single-layer graphene is that the work function of 4.65, Cu is
4.6, the potential barrier between them is relatively small, and in addition the resistivity of single-layer graphene is 10-6Ω cm, therefore contact resistance only can
Increase by a small margin.The coefficient of thermal expansion of graphene is negative value in the range of 0~1200K, therefore can suppress the thermal expansion of Cu, together
When can also reduce recess heights.Single-layer graphene is a kind of two-dimensional layered structure being made of carbon atom, its thickness is single
The diameter of atom, is 0.34nm or so, therefore will not have too much influence to the recess heights after plating.To sum up, control first
System forms the depression of certain height, and then single-layer graphene is accurately transferred in depression and forms lid coating, then passes through crystalline substance
The hybrid bonded method of circle carries out wafer bonding, is finally heat-treated at a certain temperature, the electricity that thus can inhibit copper moves
Move.
Brief description of the drawings
Fig. 1 a-1d are the hybrid bonded step schematic diagrames of the wafer of the prior art.
Fig. 2 a-2b are the schematic diagrames of the hole of the prior art.
Fig. 3 a, 3b, 3c are the steps of the method for the suppression hybrid bonded middle copper electromigration of wafer of one embodiment of the present of invention
Rapid schematic diagram.
Embodiment
Below in conjunction with the accompanying drawings, the embodiment of the present invention is described in detail, it is to be understood that the guarantor of the present invention
Protect scope and from the limitation of embodiment.
Explicitly indicated that unless otherwise other, otherwise in entire disclosure and claims, term " comprising " or its change
Change such as "comprising" or " including " etc. and will be understood to comprise stated element or part, and do not exclude other members
Part or other parts.
Introduce wafer bonding method of the prior art, interface of the wafer bonding method between two substrates first below
Place provides firm connection.Substrate is Semiconductor substrate, and substrate can also be semiconductor crystal wafer.Substrate can include providing metal
The donor wafer that is connected with through hole is connected, which can be engaged in another device wafers, and then can be with
The substrate of donor wafer is ground off using mechanical grinding or CMP method, leaves the metal layer being joined in device wafers.It can engage
Multiple wafers are to form with multiple layers of 3D IC structures.Use the engagement of chemical mechanical process (CMP) two substrates of exposure
Metal pad on surface, and planarize the two surfaces.Then, metal oxidation is formed by aoxidizing the metal pad of exposure
Nitride layer.In oxidation process, process conditions are carefully controlled.After oxidation technology, the etching work well controlled is used
Skill removes metal oxide from metal pad, exposes surface.Use wet etch process.Used oxidation technology and wet
The control of formula etch process provides very matched surface profile to metal pad.Then, two substrates are with face-to-face relation pair
Standard, and corresponding metal pad is close to each other, while the surrounding dielectric material of two substrates contacts with each other.Melting engagement may
Occur between the dielectric layer of contact.Make to produce between metal pad using annealing process and engage and strengthen between dielectric layer
Engagement, performs mixing joint technology.Because metal pad has the matched surface profile in special parameter, metal welding
Disk even forms firm engagement under relatively low technological temperature and in the case where high mechanical pressure is not required.Dielectric material
Material is selected from the oxide of such as SiO2, the nitride of such as SiN, nitrogen oxides (SiON) and uses in the semiconductor device
High-k dielectric.Using inlaying or dual-damascene metallization scheme, the copper metal pad by dielectric material envelops is formed.In chemistry
After mechanically polishing (CMP) and planarizing, substrate experience oxidation technology.Cupric oxide is formed using O2 plasmas.It can also make
With other oxidation technologies.It can use such as, the steam oxidation process of steam generation (ISSG) in situ.Then, lost by wet type
Carving technology performs Cu oxide and removes.Use dilution HF etchings.Wet-type etching be selected from include concentration for 2% DHF, HCl,
The oxide etching agent of HCOOH, citric acid.The temperature of etch process is less than 250 DEG C.After cupric oxide is removed, for substrate
Copper pad outline checked.Pad can be slightly concave from the surface of dielectric material.In the etching work well controlled
Cupric oxide is formed after skill and reduces or eliminates the heterogeneous surface obtained by CMP process, such as, depression.The control of technique allows
Slightly convex or recessed and highly uniform surface is produced on the surface of copper pad.By using embodiment method, brazing
Disk has almost uniform surface.Corresponding copper of the cup depth of copper pad on the copper pad and base substrate in top substrate
Meshed well between pad.The top and bottom substrate selected by the copper pad profile of matched well starts to be aligned, and
Then contact, dielectric layer is physically contacted and the copper pad of top and bottom substrate is spaced slightly apart.The dielectric table of substrate
Face comes into full contact with.The melting engagement of dielectric layer can start.Once substrate proceeds by physical contact, relatively low temperature is carried out
Annealing.During annealing, each copper pad forms seamless combination.Engagement between dielectric layer will continue, or bond strength exists
It will continue to increase during annealing.When the surface profile of copper pad is well matched with and metal pad cup depth is specific predetermined
In the range of when, form firm engagement.This is referred to as " seamless " engagement, wherein, the copper product across joint interface looks like
Uniformly.The engagement dielectric surface also in mixing joint technology (hybrid bondingprocess).
If Fig. 1 a-1d are the hybrid bonded step schematic diagrames of wafer of the prior art, the wafer of the prior art is hybrid bonded
Key step include：Wafer 101 (Fig. 1 a) with groove 102, the deposited metal copper in the groove 102 of wafer 101 are provided
103 (Fig. 1 b) of layer；Chemically mechanical polishing is performed to metal copper layer 103, to produce depression 104；By the composition surface thing of wafer 101
Reason contact；And thermal annealing is performed, so as to form engagement between the metal copper layer 103 of wafer 101.Due to copper in bonding process
Above-mentioned depression 104 can not be filled up completely after 103 expanded by heating of layer, so will appear from several holes between layers of copper 103
105, as illustrated in figures 2 a-2b.
The step of being the method for the suppression hybrid bonded middle copper electromigration of wafer of one embodiment of the application such as Fig. 3 a-3c
Schematic diagram, method comprise the following steps：Metal layer 303 is formed at least two Semiconductor substrates 301；To Semiconductor substrate
301 perform chemically mechanical polishing, so as to form multiple depressions 104 on metal layer 303；In the metal with multiple depressions 104
Plating graphene 302 on layer 303；And at least two Semiconductor substrates 301 are heat-treated so that metal layer 303 passes through
Graphene 302 is bonded.In one embodiment, metal layer 303 is layers of copper.In one embodiment, metal layer 303 is formed
Technique be physical vapour deposition (PVD).In one embodiment, the specific method of plating graphene 302 is：Use graphene dispersion
Single-layer graphene is plated in the depression of metal layer by liquid.In one embodiment, the thickness of graphene is about 0.34nm.By scheming
After 3c is as it can be seen that be bonded chip of the invention, hole all eliminates, and graphene is filled with hole, due to graphene
Conduction, institute is so as to the occurrence of preventing bad connection.
The advantage of the invention is that：The dispersion soln of single-layer graphene is transferred in depression by the method for plating and is formed
One layer of lid coating so that the copper in two wafers is interconnected by graphene with realizing.The work function of single-layer graphene is 4.65, Cu
Work function be 4.6, the potential barrier between them is relatively small, in addition the resistivity of single-layer graphene be 10-6Ω cm, therefore connect
Electric shock hinders increase that only can be by a small margin.The coefficient of thermal expansion of graphene is negative value in the range of 0~1200K, therefore can suppress Cu
Thermal expansion, while recess heights can also be reduced.Single-layer graphene is a kind of two-dimensional layered structure being made of carbon atom, its
Thickness is the diameter of single atom, is 0.34nm or so, therefore will not have too much influence to the recess heights after plating.It is comprehensive
On, control first forms the depression of certain height, and then single-layer graphene is accurately transferred in depression and forms lid coating, so
Wafer bonding is carried out by the hybrid bonded method of wafer afterwards, is finally heat-treated, thus can inhibit at a certain temperature
The electromigration of copper.
It is foregoing to the present invention specific exemplary embodiment description be in order to illustrate and illustration purpose.These descriptions
It is not wishing to limit the invention to disclosed precise forms, and it will be apparent that according to the above instruction, can be much changed
And change.The purpose of selecting and describing the exemplary embodiment is that explain that the certain principles of the present invention and its reality should
With so that those skilled in the art can realize and utilize the present invention a variety of exemplaries and
Various chooses and changes.The scope of the present invention is intended to be limited by claims and its equivalents.
Claims (5)
- A kind of 1. method for suppressing the hybrid bonded middle copper electromigration of wafer, it is characterised in that：It the described method comprises the following steps：Metal layer is formed at least two Semiconductor substrates；Chemically mechanical polishing is performed to the Semiconductor substrate, so as to form multiple depressions on the metal layer；The plating graphene on multiple concave metal layers；AndAt least two Semiconductor substrate is heat-treated so that the metal layer is bonded by the graphene.
- 2. the method as described in claim 1, it is characterised in that：The metal layer is layers of copper.
- 3. the method as described in claim 1, it is characterised in that：The technique for forming the metal layer is physical vapour deposition (PVD).
- 4. the method as described in claim 1, it is characterised in that：The specific method of plating graphene is：Use graphene dispersion Single-layer graphene is plated in the depression of the metal layer by liquid.
- 5. the method as described in claim 1, it is characterised in that：The thickness of the graphene is about 0.34nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201711154880.8A CN107993928B (en) | 2017-11-20 | 2017-11-20 | Method for inhibiting copper electromigration in wafer hybrid bonding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711154880.8A CN107993928B (en) | 2017-11-20 | 2017-11-20 | Method for inhibiting copper electromigration in wafer hybrid bonding |
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| CN107993928A true CN107993928A (en) | 2018-05-04 |
| CN107993928B CN107993928B (en) | 2020-05-12 |
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Cited By (8)
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| CN109148417A (en) * | 2018-09-03 | 2019-01-04 | 长江存储科技有限责任公司 | A kind of hybrid bonded structure and method of wafer |
| US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
| US11011494B2 (en) | 2018-08-31 | 2021-05-18 | Invensas Bonding Technologies, Inc. | Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics |
| US11158573B2 (en) | 2018-10-22 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Interconnect structures |
| US11393779B2 (en) | 2018-06-13 | 2022-07-19 | Invensas Bonding Technologies, Inc. | Large metal pads over TSV |
| US11728313B2 (en) | 2018-06-13 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Offset pads over TSV |
| US11804377B2 (en) | 2018-04-05 | 2023-10-31 | Adeia Semiconductor Bonding Technologies, Inc. | Method for preparing a surface for direct-bonding |
| US11929347B2 (en) | 2020-10-20 | 2024-03-12 | Adeia Semiconductor Technologies Llc | Mixed exposure for large die |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10840205B2 (en) | 2017-09-24 | 2020-11-17 | Invensas Bonding Technologies, Inc. | Chemical mechanical polishing for hybrid bonding |
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| US11728313B2 (en) | 2018-06-13 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Offset pads over TSV |
| US11749645B2 (en) | 2018-06-13 | 2023-09-05 | Adeia Semiconductor Bonding Technologies Inc. | TSV as pad |
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| US11929347B2 (en) | 2020-10-20 | 2024-03-12 | Adeia Semiconductor Technologies Llc | Mixed exposure for large die |
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