CN107967924B - Ternary content addressable memory using carbon nano field effect transistor - Google Patents

Ternary content addressable memory using carbon nano field effect transistor Download PDF

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CN107967924B
CN107967924B CN201711053697.9A CN201711053697A CN107967924B CN 107967924 B CN107967924 B CN 107967924B CN 201711053697 A CN201711053697 A CN 201711053697A CN 107967924 B CN107967924 B CN 107967924B
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CN107967924A (en
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汪鹏君
康耀鹏
张会红
李刚
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Ningbo University
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits

Abstract

The invention discloses a three-value content addressing memory utilizing a carbon nano field effect transistor, which comprises a first P type CNFET tube, a second P type CNFET tube, a third P type CNFET tube, a fourth P type CNFET tube, a fifth P type CNFET tube, a sixth P type CNFET tube, a seventh P type CNFET tube, an eighth P type CNFET tube, a ninth P type CNFET tube, a first N type CNFET tube, a second N type CNFET tube, a third N type CNFET tube, a fourth N type CNFET tube, a fifth N type CNFET tube, a sixth N type CNFET tube, a seventh N type CNFET tube and an eighth N type CNFET tube, a ninth N-type CNFET tube, a tenth N-type CNFET tube, an eleventh N-type CNFET tube, a twelfth N-type CNFET tube, a thirteenth N-type CNFET tube, a fourteenth N-type CNFET tube, a fifteenth N-type CNFET tube, a sixteenth N-type CNFET tube, a write word line, an inverted write word line, a write bit line, a read word line, an inverted read word line, a search line, an inverted search line and an address output line; the advantage is that the power consumption is lower, and can the complete three value data access that realizes.

Description

Ternary content addressable memory using carbon nano field effect transistor
Technical Field
The invention relates to a ternary content addressable memory, in particular to a ternary content addressable memory utilizing a carbon nano field effect transistor.
Background
A circuit diagram of a conventional ternary content addressable memory using carbon nano-fets is shown in fig. 1. In the three-value content addressable memory, a P-type CNFET P1, an N-type CNFET N1 and an N-type CNFET N2 form a first three-value inverter, a P-type CNFET P2, an N-type CNFET N4 and an N-type CNFET N5 form a second three-value inverter, the first three-value inverter, the second three-value inverter, an N-type CNFET N3 and an N-type CNFET N6 form a three-value SRAM unit for storing and reading data, and the N-type CNFET N7, an N-type CNFET N8, an N-type CNFET N9 and an N-type N10 form a search circuit for searching data in the SRAM unit and feeding back a judgment signal. When the ternary content addressing memory using the carbon nanometer field effect transistor works, one transistor in the first ternary phase inverter and the second ternary phase inverter is in a normally-on state, so that large circuit power consumption can be generated, the power consumption is high, meanwhile, the SRAM unit can finish storage and reading of a ternary signal, but the search circuit can only judge a logic value '0' and a logic value '2', and when an internal storage signal or an external search signal is a logic value '1', the search circuit is in an idle state, so that the ternary content addressing memory using the carbon nanometer field effect transistor cannot completely realize access of ternary data (0, 1 and 2).
Disclosure of Invention
The invention aims to provide a ternary content addressable memory which has low power consumption and can completely realize ternary data (0, 1 and 2) access and utilizes a carbon nanometer field effect transistor.
The technical scheme adopted by the invention for solving the technical problems is as follows: a three-value content addressing memory using carbon nano field effect transistor is characterized by comprising a first P type CNFET tube, a second P type CNFET tube, a third P type CNFET tube, a fourth P type CNFET tube, a fifth P type CNFET tube, a sixth P type CNFET tube, a seventh P type CNFET tube, an eighth P type CNFET tube, a ninth P type CNFET tube, a first N type CNFET tube, a second N type CNFET tube, a third N type CNFET tube, a fourth N type CNFET tube, a fifth N type CNFET tube, a sixth N type CNFET tube, a seventh N type CNFET tube and an eighth N type CNFET tube, a ninth N-type CNFET tube, a tenth N-type CNFET tube, an eleventh N-type CNFET tube, a twelfth N-type CNFET tube, a thirteenth N-type CNFET tube, a fourteenth N-type CNFET tube, a fifteenth N-type CNFET tube, a sixteenth N-type CNFET tube, a write word line, an inverted write word line, a write bit line, a read word line, an inverted read word line, a search line, an inverted search line and an address output line; the source electrode of the first P type CNFET tube, the source electrode of the second P type CNFET tube, the source electrode of the third P type CNFET tube, the source electrode of the fourth P type CNFET tube and the source electrode of the ninth P type CNFET tube are all connected with a power supply; a gate of the first P-type CNFET, a gate of the first N-type CNFET, a gate of the ninth N-type CNFET, a gate of the second P-type CNFET, a gate of the second N-type CNFET, a drain of the sixth P-type CNFET, a drain of the sixth N-type CNFET, a source of the eighth P-type CNFET and a source of the eighth N-type CNFET are connected, a drain of the first P-type CNFET, a drain of the first N-type CNFET, a gate of the eleventh N-type CNFET, a gate of the fourth P-type CNFET and a gate of the third N-type CNFET are connected, a source of the first N-type CNFET is grounded, a gate of the second P-type CNFET, a drain of the second N-type CNFET, a gate of the third P-type CNFET, a gate of the thirteenth N-type CNFET and a gate of the fifth N-type CNFET are connected, the source of the second N-type CNFET is grounded, the drain of the third P-type CNFET, the drain of the fifth P-type CNFET, the drain of the third N-type CNFET, the drain of the fourth N-type CNFET, the drain of the eighth P-type CNFET, the drain of the eighth N-type CNFET, the source of the seventh P-type CNFET, the gate of the fifth P-type CNFET and the gate of the fourth N-type CNFET are connected, the source of the third N-type CNFET is grounded, the drain of the fourth P-type CNFET, the source of the fifth P-type CNFET and the gate of the fourteenth N-type CNFET are connected, the source of the fourth N-type CNFET and the drain of the fifth N-type CNFET are connected, the source of the fifth N-type CNFET and the source of the sixth N-type CNFET are connected, and the source of the fifth N-type CNFET is grounded, The source of the sixth N-type CNFET is connected to the write bit line, the gate of the sixth P-type CNFET, the gate of the eighth N-type CNFET and the inverted write word line are connected to each other, the gate of the sixth N-type CNFET, the gate of the eighth P-type CNFET and the write word line are connected to each other, the drain of the seventh P-type CNFET, the drain of the seventh N-type CNFET and the read bit line are connected to each other, the gate of the seventh P-type CNFET and the inverted read word line are connected to each other, the gate of the seventh N-type CNFET and the read word line are connected to each other, the gate of the ninth P-type CNFET is a precharge signal input terminal of the three-value content addressable memory and is used for receiving a precharge signal, the drain of the ninth P-type CNFET, the drain of the ninth N-type CNFET, the drain of the eleventh N-type CNFET and the drain of the eleventh N-type CNFET are connected to each other, A drain of the thirteenth N-type CNFET is connected to the address output line, a source of the ninth N-type CNFET is connected to a drain of the tenth N-type CNFET, a source of the tenth N-type CNFET is grounded, a gate of the tenth N-type CNFET and a gate of the sixteenth N-type CNFET are connected to the reverse search line, a source of the eleventh N-type CNFET and a drain of the twelfth N-type CNFET are connected, a source of the twelfth N-type CNFET is grounded, a gate of the twelfth N-type CNFET and a gate of the fifteenth N-type CNFET are connected to the search line, a source of the thirteenth N-type CNFET and a drain of the fourteenth N-type CNFET are connected, a source of the fourteenth N-type CNFET, a drain of the fifteenth N-type CNFET and a drain of the sixteenth N-type CNFET are connected, and the source electrode of the fifteenth N-type CNFET tube and the source electrode of the sixteenth N-type CNFET tube are grounded.
Compared with the prior art, the invention has the advantages that a first character 0 arithmetic circuit is formed by the first P type CNFET tube and the first N type CNFET tube, a first character 2 non-arithmetic circuit is formed by the second P type CNFET tube and the second N type CNFET tube, a first coding circuit is formed by the first character 0 arithmetic circuit and the first character 2 non-arithmetic circuit, a first decoding circuit is formed by the third P type CNFET tube, the fourth P type CNFET tube, the fifth P type CNFET tube, the third N type CNFET tube, the fourth N type CNFET tube and the fifth N type CNFET tube, a first P type CNFET P1, a second P type CNFET tube, a third P type CNFET tube, a fourth P type CNFET tube, a fifth P type CNFET tube, a first N type CNFET tube N1, a second N type CNFET tube, a third N type CNFET tube, a fourth N type CNFET tube and a fifth N type CNFET tube form a sixth CNFET, a sixth CNFET transmission gate and a seventh transmission gate are formed by the first P CNFET tube and the seventh CNFET transmission gate, the eighth P type CNFET tube and the eighth N type CNFET tube form a first feedback control transmission gate, the ninth P type CNFET tube is used as a first pre-charging circuit, the ninth N type CNFET tube, the tenth N type CNFET tube, the eleventh N type CNFET tube, the twelfth N type CNFET tube, the thirteenth N type CNFET tube, the fourteenth N type CNFET tube, the fifteenth N type CNFET tube and the sixteenth N type CNFET tube form a first three-value data search circuit, the first coding circuit is used for converting three-value input signals of the first three-value buffer into two binary signals, the first decoding circuit is used for decoding the two binary signals converted by the first coding circuit and converting the two binary signals back into the three-value input signals, the first three-value buffer, the first writing transmission gate, the first reading transmission gate and the first feedback control transmission gate form a three-value SRAM unit to finish the storage and reading of the three-value signals (0, 1, 2), in the SRAM unit adopts the three-value buffer as a basic storage signal module of the traditional cross-coupled inverter, the circuit works only one direct current path with a logic value of 1 obtained by voltage division of a fifth P type CNFET tube and a fourth N type CNFET tube, so that the power consumption of the circuit is greatly reduced, the circuit utilizes the characteristic that when a three-value SRAM unit stores logic values of 0, 1 and 2 respectively, the logic levels of all nodes are different, and a first three-value data searching circuit is formed by the ninth N type CNFET tube, the tenth N type CNFET tube, the eleventh N type CNFET tube, the twelfth N type CNFET tube, the thirteenth N type CNFET tube, the fourteenth N type CNFET tube, the fifteenth N type CNFET tube and the sixteenth N type CNFET tube, so that the complete three-value data searching function is realized, and the power consumption is low on the basis of having the correct logic function, and the access of the three-value data (0, 1 and 2) can be completely realized.
Drawings
FIG. 1 is a circuit diagram of a conventional ternary content addressable memory using carbon nano-FETs;
FIG. 2 is a circuit diagram of a ternary content addressable memory utilizing carbon nano-FETs according to the present invention;
FIG. 3 is a waveform diagram illustrating the simulation of a ternary content addressable memory using carbon nano-FETs according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
Example (b): as shown in fig. 2: a ternary content addressable memory using carbon nano field effect transistors comprises a first P-type CNFET P1, a second P-type CNFET P2, a third P-type CNFET P3, a fourth P-type CNFET P4, a fifth P-type CNFET P5, a sixth P-type CNFET P6, a seventh P-type CNFET P7, an eighth P-type CNFET P8, a ninth P-type CNFET P9, a first N-type CNFET N1, a second N-type CNFET N2, a third N-type CNFET N3, a fourth N-type CNFET N4, a fifth N-type CNFET N5, a sixth N-type CNFET N6, a seventh N-type CNFET N7, an eighth N-type CNFET N8, a ninth N-type CNFET N2, a tenth N-type CNFET N56, a sixteenth CNFET N828653, a fifteenth N368653, a fifteenth N-type CNFET N36 12, a fifteenth N368653, a fifth N4, a fifteenth N4, a sixth N-type CNFET N4, a fifteenth N368653, a fifteenth N4, a fifth N4, a sixth N4, a fifth N-type CNFET N4, a sixth N4, a fifth N-type N4, a fifth N4, an inverted read word line RLB, a search line SL, an inverted search line SLB, and an address output line ML; the source electrode of the first P-type CNFET P1, the source electrode of the second P-type CNFET P2, the source electrode of the third P-type CNFET P3, the source electrode of the fourth P-type CNFET P4 and the source electrode of the ninth P-type CNFET P9 are all connected to a power supply VDD; the gate of first P-type CNFET P1, the gate of first N-type CNFET N1, the gate of ninth N-type CNFET N9, the gate of second P-type CNFET P2, the gate of second N-type CNFET N2, the drain of sixth P-type CNFET P6, the drain of sixth N-type CNFET N6, the source of eighth P-type CNFET P8 and the source of eighth N-type CNFET N8 are connected, the drain of first P-type CNFET P1, the drain of first N-type CNFET N1, the gate of eleventh N-type CNFET N11, the gate of fourth P-type CNFET P4 and the gate of third N-type CNFET N3 are connected, the source of first N-type CNFET N1 is grounded, the drain of second P-type CNFET P2, the drain of second N585, the gate of third N5, the drain of fifth N13, the drain of third N-type CNFET N13, the drain of CNFET N13, the fifth N13 and the drain of the fifth N13 and CNFETs are connected to the drain of the fifth N59P-type CNFET P599, The drain of third N-type CNFET N3, the drain of fourth N-type CNFET N4, the drain of eighth P-type CNFET P8, the drain of eighth N-type CNFET N8, the source of seventh N-type CNFET N7, the source of seventh P-type CNFET P7, the gate of fifth P-type CNFET P5 and the gate of fourth N-type CNFET N4 are connected, the source of third N-type CNFET N3 is grounded, the drain of fourth P-type CNFET P4, the source of fifth P-type CNFET P5 and the gate of fourteenth N-type CNFET N14 are connected, the source of fourth N-type CNFET N4 and the drain of fifth N5 are connected, the source of fifth N-type CNFET N5 is grounded, the source of sixth P-type CNFET P6, the source of sixth N68629 and the gate of fifth N5 are connected, the write-bit line of eighth N46N 4642 and the write line of the write word line are connected, the drain of the seventh P-type CNFET P7, the drain of the seventh N-type CNFET N7 and the read bit line RBL are connected, the gate of the seventh P-type CNFET P7 and the inverted read word line RLB are connected, the gate of the seventh N-type CNFET N7 and the read word line RL are connected, the gate of the ninth P-type CNFET P9 is a precharge signal input terminal of a three-value content addressable memory for accessing a precharge signal pre, the drain of the ninth P-type CNFET P9, the drain of the ninth N-type CNFET N9, the drain of the eleventh N-type CNFET N11, the drain of the thirteenth N-type CNFET N13 and the address output line ML are connected, the source of the ninth N-type CNFET N9 and the drain of the tenth N10 are connected, the source of the tenth N-type CNFET N10 is grounded, the gate of the tenth N-type CNFET N10, the sixteenth N16 and the source of the eleventh N-type CNFET N8536 are connected, the source of the twelfth N-type CNFET N12 is grounded, the gate of the twelfth N-type CNFET N12, the gate of the fifteenth N-type CNFET N15 are connected to the search line SL, the source of the thirteenth N-type CNFET N13 is connected to the drain of the fourteenth N-type CNFET N14, the source of the fourteenth N-type CNFET N14, the drain of the fifteenth N-type CNFET N15 and the drain of the sixteenth N-type CNFET N16 are connected, and the source of the fifteenth N-type CNFET N15 and the source of the sixteenth N-type CNFET N16 are grounded.
The three-value content addressable memory utilizing the carbon nano field effect transistor is simulated in HSPICE simulation software by applying a Stanford 32nm CNFET model library. Simulation waveforms of the write and seek operations of the tri-value content addressable memory using carbon nano-fets of the present invention are shown in fig. 3. As can be seen from fig. 3, when the ternary content addressable memory is the same as the external search data, the address output line ML is high; the address output line ML is low at the rest of the time, so that it can be understood that the ternary content addressable memory using the carbon nano field effect transistor of the present invention has a correct logic function.
The delay, power consumption and PDP of the present invention using the ternary content addressable memory with carbon nano field effect transistors and the existing ternary content addressable memory with carbon nano field effect transistors are compared at different temperatures and operating voltages, wherein the delay comparison data under different temperature and operating voltage conditions are shown in Table 1, the power consumption comparison data under different temperature and operating voltage conditions are shown in Table 2, and the PDP comparison data under different temperature and operating voltage conditions are shown in Table 3
TABLE 1
Figure GDA0002331169830000061
TABLE 2
Figure GDA0002331169830000062
TABLE 3
Figure GDA0002331169830000071
As can be seen from tables 1-3, under the standard conditions that the room temperature is 27 ℃ and the working voltage is 0.9v, compared with the existing ternary content addressable memory utilizing the carbon nanometer field effect transistor, the ternary content addressable memory utilizing the carbon nanometer field effect transistor has the advantages that the time delay is reduced by 21%, the power consumption is reduced by 94%, and the PDP is reduced by 95%; under other conditions, the ternary content addressable memory utilizing the carbon nano field effect transistor and the existing ternary content addressable memory utilizing the carbon nano field effect transistor have the characteristics of less time delay, low average power consumption and low PDP.

Claims (1)

1. A ternary content addressable memory using carbon nano field effect transistors is characterized by comprising a first P-type CNFET tube (P1), a second P-type CNFET tube (P2), a third P-type CNFET tube (P3), a fourth P-type CNFET tube (P4), a fifth P-type CNFET tube (P5), a sixth P-type CNFET tube (P92), a seventh P-type CNFET tube (P7), an eighth P-type CNFET tube (P8), a ninth P-type CNFET tube (P9), a first N-type CNFET tube (N1), a second N-type CNFET tube (N2), a third N-type CNFET tube (N3), a fourth N-type CNFET tube (N4), a fifth N-type CNFET tube (N5), a sixth N-type CNFET tube (N6), a seventh N-type CNFET tube (N7), an eighth N585), a ninth N-type CNFET tube (N10), a fourteenth N FET tube (N11), a fourteenth N FET tube (N11), a fourteenth N-type CNFET 14), a twelfth N-type CNFET tube (N11), a thirteenth N-type CNFET tube (N11), A fifteenth N-type CNFET transistor (N15), a sixteenth N-type CNFET transistor (N16), a write word line, an inverted write word line, a write bit line, a read word line, an inverted read word line, a search line, an inverted search line, and an address output line;
the source electrode of the first P type CNFET (P1), the source electrode of the second P type CNFET (P2), the source electrode of the third P type CNFET (P3), the source electrode of the fourth P type CNFET (P4) and the source electrode of the ninth P type CNFET (P9) are all connected with a power supply; a gate of the first P-type CNFET (P1), a gate of the first N-type CNFET (N1), a gate of the ninth N-type CNFET (N9), a gate of the second P-type CNFET (P2), a gate of the second N-type CNFET (N2), a drain of the sixth P-type CNFET (P6), a drain of the sixth N-type CNFET (N6), a source of the eighth P-type CNFET (P8) and a source of the eighth N-type CNFET (N8) are connected, a drain of the first P-type CNFET (P1), a drain of the first N-type CNFET (N1), a gate of the eleventh N-type CNFET (N11), a gate of the fourth P-type CNFET (P4) and a drain of the third N-type CNFET (N8236), a gate of the second N-type CNFET (N2) are connected to ground, a drain of the first P-type CNFET (P1), a drain of the fourth P4) and a drain of the second N-type CNFET (N8225) are connected to ground, The drain of said second N-type CNFET (N2), the gate of said third P-type CNFET (P3), the gate of said fifth N-type CNFET (N5) and the gate of said thirteenth N-type CNFET (N13) are connected, the source of said second N-type CNFET (N2) is grounded, the drain of said third P-type CNFET (P3), the drain of said fifth P-type CNFET (P5), the drain of said third N-type CNFET (N3), the drain of said fourth N-type CNFET (N4), the drain of said eighth P-type CNFET (P8), the drain of said eighth N-type CNFET (N8), the drain of said seventh N-type CNFET (N7), the source of said seventh P-type CNFET (N7), the source of said fifth P-type CNFET (P7), the source of said fifth N-type CNFET (N3) and the gate of said thirteenth N-type CNFET (N13) are grounded, the drain of the fourth P-type CNFET (P4), the source of the fifth P-type CNFET (P5) and the gate of the fourteenth N-type CNFET (N14), the source of the fourth N-type CNFET (N4) and the drain of the fifth N-type CNFET (N5), the source of the fifth N-type CNFET (N5) being grounded, the source of the sixth P-type CNFET (P6), the source of the sixth N-type CNFET (N6) and the write bit line being connected, the gate of the sixth P-type CNFET (P6), the gate of the eighth N-type CNFET (N8) and the inverted write word line being connected, the gate of the sixth N-type CNFET (N6), the drain of the eighth P-type CNFET (P8) and the drain of the seventh N7, the drain of the write bit line being connected, the gate of the seventh P-type CNFET (P7) is connected to the inverted read word line, the gate of the seventh N-type CNFET (N7) is connected to the read word line, the gate of the ninth P-type CNFET (P9) is a precharge signal input terminal of the three-value content addressable memory for receiving a precharge signal, the drain of the ninth P-type CNFET (P9), the drain of the ninth N-type CNFET (N9), the drain of the eleventh N-type CNFET (N11), the drain of the thirteenth N-type CNFET (N13) is connected to the address output line, the source of the ninth N-type CNFET (N9) is connected to the drain of the tenth N-type CNFET (N10), the source of the tenth N-type CNFET (N10) is grounded, the gate of the tenth N-type CNFET (N10), the inverted search gate of the tenth N-type CNFET (N16) is connected to the address output line, the source of the eleventh N-type CNFET (N11) and the drain of the twelfth N-type CNFET (N12) are connected, the source of the twelfth N-type CNFET (N12) is grounded, the gate of the twelfth N-type CNFET (N12), the gate of the fifteenth N-type CNFET (N15) and the search line are connected, the source of the thirteenth N-type CNFET (N13) and the drain of the fourteenth N-type CNFET (N14) are connected, the source of the fourteenth N-type CNFET (N14), the drain of the fifteenth N-type CNFET (N15) and the drain of the sixteenth N-type CNFET (N16) are connected, and the source of the fifteenth N-type CNFET (N15) and the source of the sixteenth N-type CNFET (N16) are grounded.
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