CN107946356A - A kind of transverse direction high-voltage power bipolar junction transistor and its manufacture method - Google Patents
A kind of transverse direction high-voltage power bipolar junction transistor and its manufacture method Download PDFInfo
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- CN107946356A CN107946356A CN201710118997.4A CN201710118997A CN107946356A CN 107946356 A CN107946356 A CN 107946356A CN 201710118997 A CN201710118997 A CN 201710118997A CN 107946356 A CN107946356 A CN 107946356A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 137
- 239000002184 metal Substances 0.000 claims abstract description 137
- 150000002739 metals Chemical class 0.000 claims abstract description 17
- 238000002347 injection Methods 0.000 claims abstract description 13
- 239000007924 injection Substances 0.000 claims abstract description 13
- 238000001259 photo etching Methods 0.000 claims description 45
- 238000000407 epitaxy Methods 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 23
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 21
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 21
- 239000001301 oxygen Substances 0.000 claims description 21
- 229910052760 oxygen Inorganic materials 0.000 claims description 21
- 238000002955 isolation Methods 0.000 claims description 15
- 230000000149 penetrating effect Effects 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000010276 construction Methods 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 4
- 230000001413 cellular effect Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 238000005245 sintering Methods 0.000 claims description 3
- 238000012360 testing method Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 238000004458 analytical method Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 230000005611 electricity Effects 0.000 abstract description 2
- 238000010010 raising Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 239000003292 glue Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
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- 238000004088 simulation Methods 0.000 description 1
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- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6625—Lateral transistors
Abstract
The invention discloses a kind of horizontal high-voltage power bipolar junction transistor and its manufacture method；Specifically on the basis of a kind of conventional lateral direction power dipole collective pipe, the injection of N-type ring-type is added between all collecting zones and launch site, and by optimizing the layout of all metals of first layer, make collector first layer metal all standing on collecting zone, size exceeds twice of collecting zone junction depth, and emitter metal is drawn by through hole and the second minor metal.Theory analysis is under reverse pressure-resistant working status in device, all collector junction edges are due to the covering of Metal field plate, so that the curvature effect of edge curved surface knot substantially reduces when depletion region is spread, it is pressure-resistant drastically to become larger, and the addition of N rings can greatly reduce the leakage current between device collector and emitter.Horizontal high-voltage power bipolar junction transistor of the invention is drawn in the case where remaining parameter influences less by emulation and actual flow result, BVcbo raisings more than 40%, BVceo improve more than 40%, one magnitude of capability improving of leaking electricity.
Description
Technical field
The present invention relates to technical field of semiconductors, is specifically a kind of horizontal high-voltage power bipolar junction transistor and its manufacture
Method.
Background technology
Middle 1940s, due to navigating, communicate, the electronics system such as weaponry it is increasingly complicated, lead
Send a telegraph that the integrated and micromation demand of sub-circuit is increasingly urgent, and nineteen fifty-nine U.S.'s Fairchild Semiconductor has converged predecessor finally
Technological achievement, first piece of practical silicon integrated circuit is manufactured that using planar bipolar technique integrated technology, is integrated circuit
Using and greatly develop and started the beginning, the technique of bipolar integrated circuit is invented at first in all integrated circuit technologies,
It is that application range is most commonly used, it is double although being subject to the huge challenge of CMOS technology with the continuous progress of integrated circuit technique
Polar form technique still by the advantage of its high speed, high transconductance, low noise and higher current driving ability etc., develop according to
So very fast, application field main at present is that the simulations such as high-operational amplifier, driver, interface, power management and ultrahigh speed integrate
Circuit.
Bipolar integrated circuit early stage uses buried regions technique and isolation technology mainly using standard silicon materials as substrate, after
Continue and invented that bipolar polysilicon emitter, complementary bipolar, SiGe are bipolar, SOI is complete successively on the basis of standard bipolar planar technology
Medium isolates the technique such as bipolar, and takes thin-film epitaxy, deep trench isolation, polysilicon autoregistration, multiple layer metal interconnection etc. extensively
Technology so that the bipolar device performance for the novel technique manufacture released successively is continuously improved, but bipolar process integrated technology
Also become to become increasingly complex.
Primary element includes active device and passive device in bipolar process, passive device mainly include resistance, inductance and
Capacitance, active device have diode, NPN pipes, Semi-active suspension, substrate PNP transistor, suspension PNP pipe etc..For in bipolar process
For single active component, designer wishes that the characteristic of device each side is all optimal, and bipolar junction transistor has height
The series of advantages such as gain, high current, high-frequency, but with the continuous development of bipolar process integrated technology, show
Drawback is also more and more obvious, and power tube can be understood as multiple bipolar junction transistors and be formed in parallel, the spy such as its is pressure-resistant, electric leakage
Property high pressure field limitation it is particularly evident, pressure-resistant, electric leakage with parameters such as gain, frequency, device sizes is quite to be difficult to reconcile
, thus consider each factor just become designer one it is extremely difficult the problem of.
The content of the invention
Present invention aim to address in the prior art, the pressure-resistant deficiency of horizontal high-voltage power bipolar junction transistor and leakage
The problems such as electricity is bigger than normal.
To realize that the technical solution that the object of the invention uses is a kind of such, transverse direction high-voltage power bipolar junction transistor
Pipe, it is characterised in that penetrated including P type substrate, n type buried layer, p type buried layer, N-type epitaxy layer, N-type heavy doping ring region, p-type isolation
Area, N-type reach through region, p-type collecting zone, N-type heavy doping base, p-type launch site, pre- oxygen layer, field oxygen layer, TEOS pre-metal dielectrics
Layer, collector first layer metal, emitter first layer metal, base stage first layer metal, emitter second layer metal, collector
Two layers of metal, base stage second layer metal and IMD planarized dielectrics.
The n type buried layer is located at the centre position of P type substrate upper surface.
The p type buried layer is located at the both ends of P type substrate upper surface.
The N-type epitaxy layer is located on n type buried layer, the N-type epitaxy layer and P type substrate, n type buried layer and p type buried layer
It is in contact.
The p-type isolation penetrating region is in contact with the both ends of N-type epitaxy layer, the bottom of the p-type isolation penetrating region and p-type
The top of buried regions is connected.
The N-type reach through region is located at the left end of n type buried layer, the bottom of the N-type reach through region and the top phase of n type buried layer
Even.
The p-type collecting zone is made of one or more construction unit repeated.The p-type collecting zone includes ring-type collection
Electric area and center round shape launch site.The p-type collecting zone is located at the centre position of N-type epitaxy layer.
The p-type launch site is located at the centre position of N-type epitaxy layer.The p-type launch site is between p-type collecting zone.
The N-type heavy doping ring region is between p-type collecting zone and p-type launch site.
The N-type heavy doping base structure annular in shape, one end of the N-type heavy doping base are located in N-type reach through region
Between position, the other end is located in N-type epitaxy layer.
The field oxygen layer be located at upper surface between outside, N-type reach through region and the p-type collecting zone of N-type reach through region upper surface,
Upper surface, the outside of N-type heavy doping base upper surface between p-type collecting zone and N-type heavy doping base.The N-type heavy doping
Base is one end in N-type epitaxy layer.
The pre- oxygen layer is located at the position between the field oxygen layer on N-type epitaxy layer.
The TEOS before-metal medium layers are covered in the position of the non-opening contact hole of whole device surface.The contact hole point
Not Wei Yu within p-type collecting zone, within p-type launch site and within N-type reach through region, the contact hole respectively with p-type collecting zone, P
Type launch site and N-type heavy doping base are in contact.
The emitter first layer metal is located in the contact hole of p-type launch site, the emitter first layer metal and p-type
Launch site and TEOS before-metal medium layers are in contact.The edge metal size of the emitter first layer metal is sent out no more than p-type
Penetrate area.
The collector first layer metal is located in the contact hole of p-type collecting zone, the collector first layer metal and p-type
Collecting zone and TEOS before-metal medium layers are in contact.The edge metal size of the collector first layer metal exceedes p-type current collection
The length at area both ends is 1~5 times of junction depth.
The base stage first layer metal is located in the contact hole of N-type reach through region, and the base stage first layer metal and N-type are heavily doped
Miscellaneous base and TEOS before-metal medium layers are in contact.It is heavily doped that the edge metal size of the base stage first layer metal is no more than N-type
Miscellaneous base.
The IMD planarized dielectrics are located at collector first layer metal, emitter first layer metal and base stage first layer gold
The position for not opening hole on category.The through hole is located on emitter first layer metal, the portion of collector first layer metal
On subregion and on the subregion of base stage first layer metal.
The emitter second layer metal is located on the through hole that all emitter first layer metals are opened.
The base stage second layer metal is located on the through hole that all base stage first layer metals are opened.
The collector second layer metal is located on the through hole that all collector first layer metals are opened.
A kind of manufacture method of transverse direction high-voltage power bipolar junction transistor, it is characterised in that comprise the following steps：
1) P type substrate is provided, grows oxide layer.
2) photoetching, after chemical wet etching removes photoresist, grows oxide layer, carries out n type buried layer injection.
3) secondary photoetching, after chemical wet etching removes photoresist, grows oxide layer, carries out p type buried layer injection.
4) N-type epitaxy layer, thermal growth oxide layer are grown.
5) third photo etching, N-type reach through region diffusion is carried out after photoetching at the cellular both ends of N-type epitaxy layer, grows oxide layer.
6) four mask, p-type isolation penetrating region injection, LP deposits SIN are carried out at device both ends.
7) five photoetching, after photoetching SIN, inject N-type impurity, grow oxide layer.
8) remnants SIN are peeled off, grow oxide layer.
9) six photoetching, carry out p-type collecting zone and the injection of p-type launch site after photoetching.
10) seven photoetching, carry out N-type heavy doping base and the injection of N-type heavy doping ring region after photoetching.
11) LP deposits ethyl orthosilicate (TEOS).
12) eight photoetching, etch contact hole, and the contact hole is located within p-type collecting zone, within p-type launch site and N
Among type reach through region.
13) first layer metal deposits, and nine photoetching, anti-carve aluminium.
14) alloy, planarized dielectric deposit and etching, form IMD planarized dielectrics.
15) ten photoetching, etch through hole.The through hole is located on emitter first layer metal, collector first layer
On the subregion of metal and on the subregion of base stage first layer metal.
16) second layer metal deposits, and ten photoetching, anti-carve aluminium.
17) alloy, growth of passivation layer.
18) 12 photoetching etch pressure welding point.
19) after process annealing, silicon chip preliminary survey is carried out, cuts, shelve, sintering and packaging and testing.
Further, the material of the P type substrate and N-type epitaxy layer includes body silicon, carborundum, GaAs, indium phosphide or germanium
Silicon.
Further, the transistor can be horizontal PNP, additionally it is possible to be horizontal NPN and substrate PNP device.
Further, the p-type launch site is made of one or more construction unit repeated.
The solution have the advantages that unquestionable, the present invention has the following advantages：
1) present invention proposes a kind of horizontal high-voltage power bipolar junction transistor and its manufacture method, specially a kind of normal
On the basis of the lateral direction power dipole collective pipe of rule, the injection of N-type ring-type is added between all collecting zones and launch site,
And by optimizing the layout of all metals of first layer, making collector first layer metal all standing, size surpasses on collecting zone
Go out twice of collecting zone junction depth, and emitter metal is drawn by through hole and the second minor metal.
2) theory analysis of the present invention is in the case where device is in reverse pressure-resistant working status, and all collector junction edges are due to metal field
The covering of plate so that the curvature effect of edge curved surface knot substantially reduces when depletion region is spread, pressure-resistant drastically to become larger, and N rings plus
Enter the leakage current that can greatly reduce between device collector and emitter.
3) draw the horizontal high-voltage power bipolar junction transistor of the present invention at it by emulation and actual flow result
In the case that remaining parameter influences less, BVcbo improves more than 40%, BVceo and improves more than 40%, one amount of electric leakage capability improving
Level.
Brief description of the drawings
Fig. 1 is a kind of 3-D solid structure figure of horizontal high-voltage power bipolar junction transistor of the present invention；
Fig. 2 is a kind of two-dimension plane structure figure of horizontal high-voltage power bipolar junction transistor of the present invention；
Fig. 3 is the n type buried layer domain and its device architecture of a kind of horizontal high-voltage power bipolar junction transistor of the present invention；
Fig. 4 is the p type buried layer domain and its device architecture of a kind of horizontal high-voltage power bipolar junction transistor of the present invention；
Fig. 5 is the p-type isolation reach through region domain and its device of a kind of horizontal high-voltage power bipolar junction transistor of the present invention
Part structure；
Fig. 6 is the N-type reach through region domain and its device junction of a kind of horizontal high-voltage power bipolar junction transistor of the present invention
Structure；
Fig. 7 is the active area domain and its device architecture of a kind of horizontal high-voltage power bipolar junction transistor of the present invention.
Fig. 8 is p-type launch site and the p-type collecting zone version of a kind of horizontal high-voltage power bipolar junction transistor of the present invention
Figure and its device architecture.
Fig. 9 is the N-type heavy doping source region domain and its device of a kind of horizontal high-voltage power bipolar junction transistor of the present invention
Part structure.
Figure 10 is the contact porose area domain and its device junction of a kind of horizontal high-voltage power bipolar junction transistor of the present invention
Structure.
Figure 11 is the M1 metals domain and its device architecture of a kind of horizontal high-voltage power bipolar junction transistor of the present invention.
Figure 12 is the through hole domain and its device architecture of a kind of horizontal high-voltage power bipolar junction transistor of the present invention.
Figure 13 is the M2 metals domain and its device architecture of a kind of horizontal high-voltage power bipolar junction transistor of the present invention.
In figure：P type substrate 100, n type buried layer 101, p type buried layer 102, N-type epitaxy layer 103, N-type heavy doping ring region 104, P
Type isolation penetrating region 105, N-type reach through region 106, p-type collecting zone 107, N-type heavy doping base 108, p-type launch site 109, pre- oxygen
Layer 110, field oxygen layer 111, TEOS before-metal medium layers 112, collector first layer metal 113, emitter first layer metal 114,
Base stage first layer metal 115, emitter second layer metal 116, collector second layer metal 117,118 and of base stage second layer metal
IMD planarized dielectrics 119.
Embodiment
With reference to embodiment, the invention will be further described, but should not be construed the above-mentioned subject area of the present invention only
It is limited to following embodiments.Without departing from the idea case in the present invention described above, according to ordinary skill knowledge and used
With means, various replacements and change are made, should all be included within the scope of the present invention.
Embodiment 1：
As depicted in figs. 1 and 2, a kind of horizontal high-voltage power bipolar junction transistor, it is characterised in that including P type substrate
100th, n type buried layer 101, p type buried layer 102, N-type epitaxy layer 103, N-type heavy doping ring region 104, p-type isolation penetrating region 105, N-type
Reach through region 106, p-type collecting zone 107, N-type heavy doping base 108, p-type launch site 109, pre- oxygen layer 110, field oxygen layer 111, TEOS
Before-metal medium layer 112, collector first layer metal 113, emitter first layer metal 114, base stage first layer metal 115, hair
Emitter-base bandgap grading second layer metal 116, collector second layer metal 117, base stage second layer metal 118 and IMD planarized dielectrics 119.
The n type buried layer 101 is located at the centre position of 100 upper surface of P type substrate.
The p type buried layer 102 is located at the both ends of 100 upper surface of P type substrate.
The N-type epitaxy layer 103 is located on n type buried layer 101, and the N-type epitaxy layer 103 is buried with P type substrate 100, N-type
Layer 101 and p type buried layer 102 are in contact.
The p-type isolation penetrating region 105 is in contact with the both ends of N-type epitaxy layer 103, the p-type isolation penetrating region 105
Bottom is connected with the top of p type buried layer 102.
The N-type reach through region 106 is located at the left end of n type buried layer 101, the bottom of the N-type reach through region 106 and n type buried layer
101 top is connected.
The p-type collecting zone 107 is made of one or more construction unit repeated.The p-type collecting zone 107 includes
Ring-type collecting zone and center round shape launch site.The p-type collecting zone 107 is located at the centre position of N-type epitaxy layer 103.
The p-type launch site 109 is located at the centre position of N-type epitaxy layer 103.The p-type launch site 109 is located at p-type collection
Between electric area 107.
The N-type heavy doping ring region 104 is between p-type collecting zone 107 and p-type launch site 109.
108 structure annular in shape of N-type heavy doping base, one end of the N-type heavy doping base 108 are located at N-type break-through
The centre position in area 106, the other end are located in N-type epitaxy layer 103.
The field oxygen layer 111 is located at outside, N-type reach through region 106 and the p-type collecting zone 107 of 106 upper surface of N-type reach through region
Between upper surface, the upper surface between p-type collecting zone 107 and N-type heavy doping base 108,108 upper table of N-type heavy doping base
The outside in face.The N-type heavy doping base 108 is one end in N-type epitaxy layer 103.
The pre- oxygen layer 110 is located at the position between the field oxygen layer 111 on N-type epitaxy layer 103.
The TEOS before-metal medium layers 112 are covered in the position of the non-opening contact hole of whole device surface.The contact
Respectively within p-type collecting zone 107, within p-type launch site 109 and within N-type reach through region 106, the contact hole is distinguished in hole
It is in contact with p-type collecting zone 107, p-type launch site 109 and N-type heavy doping base 108.
The emitter first layer metal 114 is located in the contact hole of p-type launch site 109, the emitter first layer gold
Belong to 114 to be in contact with p-type launch site 109 and TEOS before-metal medium layers 112.The edge of the emitter first layer metal 114
Metal dimension is no more than p-type launch site 109.
The collector first layer metal 113 is located in the contact hole of p-type collecting zone 107, the collector first layer gold
Belong to 113 to be in contact with p-type collecting zone 107 and TEOS before-metal medium layers 112.The edge of the collector first layer metal 113
The length that metal dimension exceedes 107 both ends of p-type collecting zone is 1~5 times of junction depth.
The base stage first layer metal 115 is located in the contact hole of N-type reach through region 106, the base stage first layer metal 115
It is in contact with N-type heavy doping base 108 and TEOS before-metal medium layers 112.The edge metal of the base stage first layer metal 115
Size is no more than N-type heavy doping base 108.
The IMD planarized dielectrics 119 are located at collector first layer metal 113, emitter first layer metal 114 and base stage
The position for not opening hole on first layer metal 115.The through hole is located on emitter first layer metal 114, collector
On the subregion of first layer metal 113 and on the subregion of base stage first layer metal 115.
The emitter second layer metal 116 is located on the through hole that all emitter first layer metals 114 are opened.
The base stage second layer metal 118 is located on the through hole that all base stage first layer metals 115 are opened.
The collector second layer metal 117 is located on the through hole that all collector first layer metals 113 are opened.
Embodiment 2：
As shown in Fig. 3~Figure 13, a kind of manufacture method of transverse direction high-voltage power bipolar junction transistor, it is characterised in that
Comprise the following steps：
1) the less NTD of defect is selected<111>Single-chip, about 500~700 μm of piece thickness, 5~30 Ω cm of resistivity, beat
SD washes, it is stand-by to dry；
2) a thickness oxide layer is grown1100~1150 DEG C of temperature, time 100min~120min,
Dry humidification oxidizing condition.
3) photoetching, after chemical wet etching removes photoresist, grows one layer of thin oxide layerTemperature 1000~1020
DEG C, time 30min~40min, pure dry oxidation condition.
N type buried layer 101 is carried out in wafer substrate centre position to inject, ion implanting conditions are：Dosage 1e15~5e15cm-2, 40~80KeV of energy.
Redistribution condition is：1000 DEG C of aerobic conditions, oxidated layer thickness areThe pure N of re-annealing temperature2、
1100~1150 DEG C, time 100min~120min.
4) secondary photoetching, after chemical wet etching removes photoresist, grows one layer of thin oxide layerTemperature 1000~1020
DEG C, time 30min~40min, pure dry oxidation condition.
P type buried layer 102 is carried out at wafer substrate both ends to inject, ion implanting conditions are：Dosage 4e15~8e15cm-2, energy
Measure 60~100KeV.
Redistribution condition is：Pure N2Atmosphere annealing temperature, 1100~1150 DEG C, time 100min~120min.Deoxidation
Layer.
5) silicon chip surface growth N-type epitaxy layer 103, temperature is at 1100 DEG C~1150 DEG C, and thickness is 5~30 μm, resistivity
For 4~40 Ω cm；
6) thermal growth oxide layer, thickness exist
7) third photo etching, carries out N-type reach through region 106 at the cellular both ends of N-type epitaxy layer 103 after photoetching and spreads, be specially
Spread using constant impurity surface concentration method, the oxide layer of 50~100nm thickness is grown before diffusion, constant impurity surface is dense
Degree method diffusion conditions is：PCL3 gas sources, oxygen free condition, 1100~1150 DEG C of temperature, time 100min~1500min；Go
Oxide layer；
8) one layer of thin oxide layer is grown1000~1020 DEG C of temperature, time 30min~40min, pure dry method
Oxidizing condition.
Four mask, after photoetching, p-type isolation penetrating region 105 is carried out at device both ends and is injected, ion implanting conditions are：Agent
Measure 1e15~8e15cm-2, 60~100KeV of energy.
9) LP deposits SIN, and thickness exists
10) the 5th photoetching, after chemical wet etching SIN, general note dose is 1E11-5E11, energy is 60-100KeV's
N-type impurity, then grows a thickness oxide layer 1000~1050 DEG C of temperature, time 200min~
400min, dry humidification oxidizing condition.
Annealing redistribution condition be：Pure N2Atmosphere annealing temperature, 1100~1150 DEG C, time 100min~120min.
11) remnants SIN are peeled off, and are peeled off a layer thickness and are aboutOxide layer.And grow one layer of thin oxide layer1000~1020 DEG C of temperature, time 30min~40min, pure dry oxidation condition.
12) six photoetching, carry out p-type collecting zone 107 after photoetching and p-type launch site 109 are injected, and specially use band glue
Injection, ion implanting conditions are：Dosage 1e14~5e14cm-2,60~100KeV of energy, redistribution condition are：Oxygen free condition,
1100~1150 DEG C of temperature, time 100min~200min；
13) seven photoetching, progress, N-type heavy doping base 108 and N-type heavy doping ring region 104 are injected after photoetching, specifically
To be injected using band glue, ion implanting conditions are：Dosage 1e15~5e15cm-2,40~80KeV of energy, redistribution condition are：
Oxygen free condition, 950~1000 DEG C of temperature, time 30min~60min；
14) LP deposits TEOS, and thickness exists
15) eight photoetching, etch contact hole；Contact hole site be located at p-type collecting zone 107 and p-type launch site 109 with
Among interior and N-type reach through region 106.
16) first layer metal deposits, and deposits metal AL in whole disk surfaces, nine photoetching, anti-carve aluminium；
17) alloy, 550 DEG C of furnace temperature, time 10min~30min；
18) planarized dielectric deposit and etching, form IMD planarized dielectrics 119；
19) ten photoetching, etch through hole；Through hole is located on all emitter first layer metals 114, part collector
On on first layer metal 113 and part base stage first layer metal 115.
20) second layer metal deposits, and deposits metal AL in whole disk surfaces, ten photoetching, anti-carve aluminium；
21) alloy, 550 DEG C of furnace temperature, time 10min~30min, passivation layer growth；
22) 12 photoetching etch pressure welding point；
23) process annealing, 500 DEG C~510 DEG C of temperature, constant temperature 30min；
24) silicon chip preliminary survey, cut, shelve, sintering, packaging and testing.
Claims (5)
1. a kind of transverse direction high-voltage power bipolar junction transistor, it is characterised in that including P type substrate (100), n type buried layer
(101), p type buried layer (102), N-type epitaxy layer (103), N-type heavy doping ring region (104), p-type isolation penetrating region (105), N-type are worn
Logical area (106), p-type collecting zone (107), N-type heavy doping base (108), p-type launch site (109), pre- oxygen layer (110), field oxygen layer
(111), TEOS before-metal medium layers (112), collector first layer metal (113), emitter first layer metal (114), base stage
First layer metal (115), emitter second layer metal (116), collector second layer metal (117), base stage second layer metal
(118) and IMD planarized dielectrics (119)；
The n type buried layer (101) is located at the centre position of P type substrate (100) upper surface；
The p type buried layer (102) is located at the both ends of P type substrate (100) upper surface；
The N-type epitaxy layer (103) is located on n type buried layer (101), the N-type epitaxy layer (103) and P type substrate (100), N
Type buried regions (101) and p type buried layer (102) are in contact；
P-type isolation penetrating region (105) is in contact with the both ends of N-type epitaxy layer (103), and the p-type isolates penetrating region (105)
Bottom be connected with the top of p type buried layer (102)；
The N-type reach through region (106) is located at the left end of n type buried layer (101), and the bottom of the N-type reach through region (106) is buried with N-type
The top of layer (101) is connected；
The p-type collecting zone (107) is made of one or more construction unit repeated；The p-type collecting zone (107) includes
Ring-type collecting zone and center round shape launch site；The p-type collecting zone (107) is located at the centre position of N-type epitaxy layer (103)；
The p-type launch site (109) is located at the centre position of N-type epitaxy layer (103)；The p-type launch site (109) is located at p-type
Between collecting zone (107)；
The N-type heavy doping ring region (104) is located between p-type collecting zone (107) and p-type launch site (109)；
The N-type heavy doping base (108) structure annular in shape, one end of the N-type heavy doping base (108) are located at N-type break-through
The centre position in area (106), the other end are located in N-type epitaxy layer (103)；
The field oxygen layer (111) is located at the outside of N-type reach through region (106) upper surface, N-type reach through region (106) and p-type collecting zone
(107) upper surface between upper surface, p-type collecting zone (107) and N-type heavy doping base (108) between, N-type heavy doping base
The outside of area (108) upper surface；The N-type heavy doping base (108) is one end in N-type epitaxy layer (103)；
The pre- oxygen layer (110) is located at the position between the field oxygen layer (111) on N-type epitaxy layer (103)；
The TEOS before-metal medium layers (112) are covered in the position of the non-opening contact hole of whole device surface；The contact hole
Respectively within p-type collecting zone (107), within p-type launch site (109) and within N-type reach through region (106), the contact hole
It is in contact respectively with p-type collecting zone (107), p-type launch site (109) and N-type heavy doping base (108)；
The emitter first layer metal (114) is located in the contact hole of p-type launch site (109), the emitter first layer gold
Belong to (114) to be in contact with p-type launch site (109) and TEOS before-metal medium layers (112)；The emitter first layer metal
(114) edge metal size is no more than p-type launch site (109)；
The collector first layer metal (113) is located in the contact hole of p-type collecting zone (107), the collector first layer gold
Belong to (113) to be in contact with p-type collecting zone (107) and TEOS before-metal medium layers (112)；The collector first layer metal
(113) length that edge metal size exceedes p-type collecting zone (107) both ends is 1~5 times of junction depth；
The base stage first layer metal (115) is located in the contact hole of N-type reach through region (106), the base stage first layer metal
(115) it is in contact with N-type heavy doping base (108) and TEOS before-metal medium layers (112)；The base stage first layer metal
(115) edge metal size is no more than N-type heavy doping base (108)；
The IMD planarized dielectrics (119) are located at collector first layer metal (113), emitter first layer metal (114) and base
The position for not opening hole on pole first layer metal (115)；The through hole is located on emitter first layer metal (114),
On the subregion of collector first layer metal (113) and on the subregion of base stage first layer metal (115)；
The emitter second layer metal (116) is located on the through hole that all emitter first layer metals (114) are opened；
The base stage second layer metal (118) is located on the through hole that all base stage first layer metals (115) are opened；
The collector second layer metal (117) is located on the through hole that all collector first layer metals (113) are opened.
2. a kind of manufacture method of transverse direction high-voltage power bipolar junction transistor, it is characterised in that comprise the following steps：
1) P type substrate (100) is provided, grows oxide layer；
2) photoetching, after chemical wet etching removes photoresist, grows oxide layer, carries out n type buried layer (101) injection；
3) secondary photoetching, after chemical wet etching removes photoresist, grows oxide layer, carries out p type buried layer (102) injection；
4) N-type epitaxy layer (103), thermal growth oxide layer are grown；
5) third photo etching, carries out N-type reach through region (106) diffusion, growth of oxygen at the cellular both ends of N-type epitaxy layer (103) after photoetching
Change layer；
6) four mask, p-type isolation penetrating region (105) injection, LP deposits SIN are carried out at device both ends；
7) five photoetching, after photoetching SIN, inject N-type impurity, grow oxide layer；
8) remnants SIN are peeled off, grow oxide layer；
9) six photoetching, carry out p-type collecting zone (107) and p-type launch site (109) injection after photoetching；
10) seven photoetching, carry out N-type heavy doping base (108) and N-type heavy doping ring region (104) injection after photoetching；
11) LP deposits ethyl orthosilicate (TEOS)；
12) eight photoetching, etch contact hole, and the contact hole is located within p-type collecting zone (107), p-type launch site (109)
Within and N-type reach through region (106) among；
13) first layer metal deposits, and nine photoetching, anti-carve aluminium；
14) alloy, planarized dielectric deposit and etching, form IMD planarized dielectrics (119)；
15) ten photoetching, etch through hole；The through hole is located on emitter first layer metal (114), collector first layer
On the subregion of metal (113) and on the subregion of base stage first layer metal (115)；
16) second layer metal deposits, and ten photoetching, anti-carve aluminium；
17) alloy, growth of passivation layer；
18) 12 photoetching etch pressure welding point；
19) after process annealing, silicon chip preliminary survey is carried out, cuts, shelve, sintering and packaging and testing.
3. a kind of horizontal high-voltage power bipolar junction transistor according to claim 1 or 2 and its manufacture method, its feature
It is：The material of the P type substrate (100) and N-type epitaxy layer (103) includes body silicon, carborundum, GaAs, indium phosphide or germanium
Silicon.
4. a kind of horizontal high-voltage power bipolar junction transistor according to claim 1 or 2 and its manufacture method, its feature
It is：The transistor can be horizontal PNP, additionally it is possible to be horizontal NPN and substrate PNP device.
5. a kind of horizontal high-voltage power bipolar junction transistor according to claim 1 or 2 and its manufacture method, its feature
It is：The p-type launch site (109) is made of one or more construction unit repeated.
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