CN107946356B - Lateral high-voltage power bipolar junction transistor and manufacturing method thereof - Google Patents
Lateral high-voltage power bipolar junction transistor and manufacturing method thereof Download PDFInfo
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- 239000002184 metal Substances 0.000 claims abstract description 137
- 238000002347 injection Methods 0.000 claims abstract description 12
- 239000007924 injection Substances 0.000 claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims description 45
- 239000000758 substrate Substances 0.000 claims description 24
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 22
- 238000002955 isolation Methods 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 15
- 125000000623 heterocyclic group Chemical group 0.000 claims description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
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- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6625—Lateral transistors
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Abstract
The invention discloses a lateral high-voltage power bipolar junction transistor and a manufacturing method thereof; on the basis of a conventional transverse power bipolar junction collective tube, N-type annular injection is added between all collector regions and an emitter region, and the layout of all metals of a first layer is optimized, so that the metal of the first layer of the collector is fully covered on the collector region, the size of the collector is twice the junction depth of the collector region, and the metal of the emitter is led out through a through hole and a second metal. Theoretical analysis is that under the reverse withstand voltage operating condition of the device, the curvature effect of the edge curved surface junction is greatly reduced when the depletion region is diffused due to the coverage of the metal field plate at the edges of all collector junctions, the withstand voltage is suddenly increased, and the addition of the N ring can greatly reduce the leakage current between the collector and the emitter of the device. The simulation and actual current sheet results show that under the condition that the influence of other parameters is not great, the BVCbo is improved by more than 40%, the Bvceo is improved by more than 40%, and the leakage capacity is improved by one order of magnitude.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a lateral high-voltage power bipolar junction transistor and a manufacturing method thereof.
Background
In the middle forty of the twentieth century, due to the increasing complexity of electronic device systems such as navigation, communication and weaponry, the demands for integration and miniaturization of electronic circuits are becoming urgent, and in the united states fayal semiconductor company in 1959, the former practical silicon integrated circuit is manufactured by adopting a planar bipolar process integration technology, which is the first invention in all integrated circuit processes and is the most extensive in application range, and the bipolar process is still faster by virtue of the advantages of high speed, high transconductance, low noise, higher current driving capability and the like, so that the application fields of the bipolar integrated circuit are analog and ultra-high speed integrated circuits such as high-precision operational amplifier, driver, interface and power management.
The bipolar integrated circuit is mainly prepared from standard silicon materials serving as a substrate in early stage, a buried layer process and an isolation technology are adopted, and then the processes of a polycrystalline silicon emitter bipolar, a complementary bipolar, a SiGe bipolar, an SOI full-dielectric isolation bipolar and the like are sequentially invented on the basis of a standard bipolar plane process, and technologies such as thin-layer epitaxy, deep-groove isolation, polycrystalline silicon self-alignment, multilayer metal interconnection and the like are widely adopted, so that the performance of a bipolar device manufactured by a new process technology which is sequentially pushed out is continuously improved, and the bipolar process integration technology is more and more complicated.
The basic elements in the bipolar process comprise active devices and passive devices, wherein the passive devices mainly comprise resistors, inductors and capacitors, and the active devices comprise diodes, NPN tubes, transverse PNP tubes, substrate PNP tubes, suspension PNP tubes and the like. For a single active component in a bipolar process, a designer hopes that the characteristics of the component in all aspects are optimal, a bipolar junction transistor has a series of advantages of high gain, large current, high frequency and the like, but with the continuous development of bipolar process integration technology, the defects are more and more obvious, a power tube can be understood as a plurality of bipolar junction transistors connected in parallel, the characteristics of voltage resistance, electric leakage and the like of the power tube are particularly obvious in the limitation of the high voltage field, and the parameters of voltage resistance, electric leakage, gain, frequency, component size and the like are quite difficult to reconcile, so that comprehensively considering various factors becomes a very difficult problem for the designer.
Disclosure of Invention
The invention aims to solve the problems of insufficient withstand voltage, large leakage current and the like of a transverse high-voltage power bipolar junction transistor in the prior art.
The technical scheme adopted for achieving the purpose of the invention is that the lateral high-voltage power bipolar junction transistor is characterized by comprising a P-type substrate, an N-type buried layer, a P-type buried layer, an N-type epitaxial layer, an N-type heavily doped heterocyclic region, a P-type isolation penetration region, an N-type penetration region, a P-type collector region, an N-type heavily doped base region, a P-type emission region, a pre-oxygen layer, a field oxygen layer, a TEOS (TEOS metal front dielectric layer, a collector first layer metal, an emitter first layer metal, a base first layer metal, an emitter second layer metal, a collector second layer metal, a base second layer metal and an IMD (in-plane dielectric) planarization medium.
And the N-type buried layer is positioned in the middle of the upper surface of the P-type substrate.
The P-type buried layers are positioned at two ends of the upper surface of the P-type substrate.
The N-type epitaxial layer is positioned on the N-type buried layer, and the N-type epitaxial layer is in contact with the P-type substrate, the N-type buried layer and the P-type buried layer.
The P type isolation penetrating region is contacted with two ends of the N type epitaxial layer, and the bottom of the P type isolation penetrating region is connected with the top of the P type buried layer.
The N-type through region is positioned at the left end of the N-type buried layer, and the bottom of the N-type through region is connected with the top of the N-type buried layer.
The P-type collector region is formed of one or more repeating structural units. The P-type collector region comprises an annular collector region and a central circular emitter region. And the P-type collector region is positioned in the middle of the N-type epitaxial layer.
And the P-type emission region is positioned in the middle of the N-type epitaxial layer. The P-type emission region is positioned between the P-type collector regions.
The N-type heavily doped ring region is positioned between the P-type collector region and the P-type emitter region.
The N-type heavily doped base region is of an annular structure, one end of the N-type heavily doped base region is located in the middle of the N-type through region, and the other end of the N-type heavily doped base region is located in the N-type epitaxial layer.
The field oxide layer is positioned outside the upper surface of the N-type through region, the upper surface between the N-type through region and the P-type collector region, the upper surface between the P-type collector region and the N-type heavily doped base region and outside the upper surface of the N-type heavily doped base region. The N-type heavily doped base region is positioned at one end in the N-type epitaxial layer.
The pre-oxygen layer is located at a position between the field oxygen layers above the N-type epitaxial layer.
And the TEOS metal front dielectric layer covers the whole device surface at the position where the contact hole is not opened. The contact holes are respectively positioned in the P-type collector region, the P-type emitter region and the N-type through region, and are respectively contacted with the P-type collector region, the P-type emitter region and the N-type heavily doped base region.
The first layer of metal of the emitter is positioned in the contact hole of the P-type emitter region, and the first layer of metal of the emitter is contacted with the P-type emitter region and the TEOS metal front dielectric layer. The edge metal size of the first layer metal of the emitter does not exceed the P-type emitter region.
The first layer of metal of the collector is positioned in the contact hole of the P-type collector region, and the first layer of metal of the collector is contacted with the P-type collector region and the TEOS metal front dielectric layer. The edge metal size of the first layer metal of the collector exceeds the length of the two ends of the P-type collector region by 1-5 times of the junction depth.
The first layer of base metal is positioned in the contact hole of the N-type punching region, and the first layer of base metal is contacted with the N-type heavily doped base region and the TEOS metal front dielectric layer. And the edge metal size of the base electrode first layer metal is not more than that of the N-type heavily doped base region.
The IMD planarization medium is positioned at the position of the non-opened through hole above the first layer metal of the collector, the first layer metal of the emitter and the first layer metal of the base. The via is located over the emitter first layer metal, over a partial region of the collector first layer metal, and over a partial region of the base first layer metal.
The second layer of emitter metal is located above all the through holes opened by the first layer of emitter metal.
The base second layer metal is located above all through holes opened by the base first layer metal.
The collector second layer metal is located over all the vias opened by the collector first layer metal.
A method of fabricating a lateral high voltage power bipolar junction transistor, comprising the steps of:
1) And providing a P-type substrate and growing an oxide layer.
2) And photoetching once, and after photoresist removal by photoetching, growing an oxide layer and injecting an N-type buried layer.
3) And (3) performing secondary photoetching, and growing an oxide layer and performing P-type buried layer injection after photoresist removal by photoetching.
4) And growing an N-type epitaxial layer and thermally growing an oxide layer.
5) And performing three times of photoetching, and then performing N-type through region diffusion at two ends of a cell of the N-type epitaxial layer to grow an oxide layer.
6) And performing four times of photoetching, performing P-type isolation penetrating region injection at two ends of the device, and performing LP deposition on SIN.
7) And (3) photoetching for five times, and after photoetching SIN, injecting N-type impurities to grow an oxide layer.
8) And stripping residual SIN and growing an oxide layer.
9) And (3) carrying out six times of photoetching, and carrying out injection of the P-type collector region and the P-type emitter region after photoetching.
10 Seven times of photoetching, and then the N-type heavily doped base region and the N-type heavily doped heterocyclic region are implanted.
11 LP deposition of tetraethyl orthosilicate (TEOS).
12 Eight times of photoetching, etching a contact hole, wherein the contact hole is positioned in the P-type collector region, the P-type emitter region and the middle of the N-type through region.
13 A first layer of metal is deposited, nine times of photoetching and back-etching of aluminum.
14 Alloy, planarizing dielectric deposition and etching to form an IMD planarizing dielectric.
15 Ten times of photoetching, and etching the through holes. The via is located over the emitter first layer metal, over a partial region of the collector first layer metal, and over a partial region of the base first layer metal.
16 A second metal deposition, eleven times photoetching and back etching aluminum.
17 Alloy, growing passivation layer.
18 Twelve times of photoetching to form a pressure welding spot.
19 After low-temperature annealing, performing initial testing, cutting, loading, sintering and packaging test on the silicon wafer.
Further, the materials of the P-type substrate and the N-type epitaxial layer comprise bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.
Further, the transistor can be a lateral PNP, and can also be a lateral NPN and substrate PNP device.
Further, the P-type emitter region is comprised of one or more repeating structural units.
The technical effects of the invention are undoubtedly that the invention has the following advantages:
1) The invention provides a transverse high-voltage power bipolar junction transistor and a manufacturing method thereof, in particular to an N-type annular injection is added between all collector regions and an emitter region on the basis of a conventional transverse power bipolar junction collective transistor, and the layout of all metals of a first layer is optimized to ensure that the metal of the first layer of a collector is fully covered on the collector region, the size of the metal exceeds twice the junction depth of the collector region, and the metal of an emitter is led out through a through hole and a second metal.
2) According to the invention, theoretical analysis is carried out, when the device is in a reverse pressure-resistant working state, the curvature effect of the edge curved surface junction is greatly reduced when the depletion region is diffused due to the coverage of the metal field plate, the pressure resistance is suddenly increased, and the leakage current between the collector and the emitter of the device can be greatly reduced by adding the N ring.
3) The simulation and actual current sheet results show that under the condition that the influence of other parameters is not great, the BVCbo is improved by more than 40%, the Bvceo is improved by more than 40%, and the leakage capacity is improved by one order of magnitude.
Drawings
Fig. 1 is a three-dimensional perspective view of a lateral high-voltage power bipolar junction transistor of the present invention;
fig. 2 is a two-dimensional planar block diagram of a lateral high-voltage power bipolar junction transistor of the present invention;
FIG. 3 is an N-type buried layer layout and device structure of a lateral high-voltage power bipolar junction transistor of the present invention;
FIG. 4 is a layout of a P-type buried layer of a lateral high-voltage power bipolar junction transistor and a device structure thereof;
FIG. 5 is a layout of a P-type isolation punch-through region of a lateral high voltage power bipolar junction transistor and device structure thereof according to the present invention;
FIG. 6 is an N-type punch-through region layout and device structure of a lateral high voltage power bipolar junction transistor of the present invention;
fig. 7 is an active area layout of a lateral high voltage power bipolar junction transistor and device structure thereof in accordance with the present invention.
Fig. 8 is a layout of P-type emitter and collector regions and device structure of a lateral high voltage power bipolar junction transistor of the present invention.
Fig. 9 is an N-type heavily doped source region layout and device structure of a lateral high voltage power bipolar junction transistor of the present invention.
Fig. 10 is a contact hole area layout and device structure of a lateral high voltage power bipolar junction transistor of the present invention.
Fig. 11 is an M1 metal layout and device structure of a lateral high voltage power bipolar junction transistor of the present invention.
Fig. 12 is a through hole layout and device structure of a lateral high voltage power bipolar junction transistor of the present invention.
Fig. 13 is an M2 metal layout and device structure of a lateral high voltage power bipolar junction transistor of the present invention.
In the figure: the semiconductor device comprises a P-type substrate 100, an N-type buried layer 101, a P-type buried layer 102, an N-type epitaxial layer 103, an N-type heavily doped heterocyclic region 104, a P-type isolation penetration region 105, an N-type penetration region 106, a P-type collector region 107, an N-type heavily doped base region 108, a P-type emitter region 109, a pre-oxygen layer 110, a field oxygen layer 111, a TEOS pre-metal dielectric layer 112, a collector first layer metal 113, an emitter first layer metal 114, a base first layer metal 115, an emitter second layer metal 116, a collector second layer metal 117, a base second layer metal 118 and an IMD planarization dielectric 119.
Detailed Description
The present invention is further described below with reference to examples, but it should not be construed that the scope of the above subject matter of the present invention is limited to the following examples. Various substitutions and alterations are made according to the ordinary skill and familiar means of the art without departing from the technical spirit of the invention, and all such substitutions and alterations are intended to be included in the scope of the invention.
Example 1:
as shown in fig. 1 and 2, a lateral high-voltage power bipolar junction transistor is characterized by comprising a P-type substrate 100, an N-type buried layer 101, a P-type buried layer 102, an N-type epitaxial layer 103, an N-type heavily doped heterocyclic region 104, a P-type isolation penetration region 105, an N-type penetration region 106, a P-type collector region 107, an N-type heavily doped base region 108, a P-type emitter region 109, a pre-oxygen layer 110, a field oxide layer 111, a TEOS pre-metal dielectric layer 112, a collector first metal 113, an emitter first metal 114, a base first metal 115, an emitter second metal 116, a collector second metal 117, a base second metal 118, and an IMD planarization medium 119.
The N-type buried layer 101 is located in the middle of the upper surface of the P-type substrate 100.
The P-type buried layer 102 is located at two ends of the upper surface of the P-type substrate 100.
The N-type epitaxial layer 103 is located above the N-type buried layer 101, and the N-type epitaxial layer 103 is in contact with the P-type substrate 100, the N-type buried layer 101 and the P-type buried layer 102.
The P-type isolation penetration region 105 is in contact with two ends of the N-type epitaxial layer 103, and the bottom of the P-type isolation penetration region 105 is connected with the top of the P-type buried layer 102.
The N-type through region 106 is located at the left end of the N-type buried layer 101, and the bottom of the N-type through region 106 is connected to the top of the N-type buried layer 101.
The P-type collector region 107 is made up of one or more repeating structural units. The P-type collector region 107 includes an annular collector region and a central circular emitter region. The P-type collector region 107 is located in the middle of the N-type epitaxial layer 103.
The P-type emitter 109 is located in the middle of the N-type epitaxial layer 103. The P-type emitter regions 109 are located between the P-type collector regions 107.
The N-type heavily doped heterocyclic region 104 is located between the P-type collector region 107 and the P-type emitter region 109.
The N-type heavily doped base region 108 has a ring structure, and one end of the N-type heavily doped base region 108 is located in the middle of the N-type through region 106, and the other end is located in the N-type epitaxial layer 103.
The field oxide layer 111 is located outside the upper surface of the N-type through region 106, the upper surface between the N-type through region 106 and the P-type collector region 107, the upper surface between the P-type collector region 107 and the N-type heavily doped base region 108, and the upper surface of the N-type heavily doped base region 108. The heavily doped N-type base region 108 is located at one end in the N-type epitaxial layer 103.
The pre-oxide layer 110 is located at a position between the field oxide layers 111 over the N-type epitaxial layer 103.
The TEOS pre-metal dielectric layer 112 covers the entire device surface at the locations where no contact holes are opened. The contact holes are respectively located in the P-type collector region 107, the P-type emitter region 109 and the N-type through region 106, and are respectively in contact with the P-type collector region 107, the P-type emitter region 109 and the N-type heavily doped base region 108.
The first metal layer 114 of the emitter is located in the contact hole of the P-type emitter 109, and the first metal layer 114 of the emitter is in contact with the P-type emitter 109 and the TEOS pre-metal dielectric layer 112. The edge metal dimension of the emitter first layer metal 114 does not exceed the P-type emitter region 109.
The collector first metal 113 is located in the contact hole of the P-type collector region 107, and the collector first metal 113 is in contact with the P-type collector region 107 and the TEOS pre-metal dielectric layer 112. The edge metal dimension of the collector first layer metal 113 exceeds the length of the two ends of the P-type collector region 107 by 1-5 times the junction depth.
The base first metal layer 115 is located in the contact hole of the N-type through region 106, and the base first metal layer 115 is in contact with the N-type heavily doped base region 108 and the TEOS pre-metal dielectric layer 112. The edge metal dimension of the base first layer metal 115 does not exceed the N-type heavily doped base region 108.
The IMD planarizing dielectric 119 is located at the non-via locations over the collector first layer metal 113, the emitter first layer metal 114, and the base first layer metal 115. The via is located over the emitter first layer metal 114, over a partial region of the collector first layer metal 113 and over a partial region of the base first layer metal 115.
The emitter second metal 116 is located above all of the vias opened by the emitter first metal 114.
The base second layer metal 118 is located over all of the vias opened by the base first layer metal 115.
The collector second layer metal 117 is located above all of the vias opened by the collector first layer metal 113.
Example 2:
as shown in fig. 3 to 13, a method for manufacturing a lateral high-voltage power bipolar junction transistor is characterized by comprising the steps of:
1) Selecting NTD <111> single crystal wafer with less defects, wherein the thickness of the wafer is about 500-700 mu m, the resistivity is 5-30Ω & cm, marking, cleaning and drying for standby;
2) Growing a thick oxide layerThe temperature is 1100-1150 ℃ and the time is 100-120 min, and the dry humidifying oxidation condition is adopted.
3) After photoresist is removed by one-time photoetching and photoetching, a thin oxide layer is grownThe temperature is 1000-1020 ℃, the time is 30-40 min, and the pure dry oxidation condition is adopted.
And (3) implanting an N-type buried layer 101 in the middle of the wafer substrate, wherein the ion implantation conditions are as follows: dosage of 1e 15-5 e15cm -2 Energy of 40-80 KeV.
The redistribution conditions are as follows: oxygen condition 1000 deg.C, oxide layer thickness isRe-annealing temperature pure N 2 1100-1150 ℃ and 100-120 min.
4) After photoresist is removed by secondary photoetching and photoetching, a thin oxide layer is grownThe temperature is 1000-1020 ℃, the time is 30-40 min, and the pure dry oxidation condition is adopted.
Implanting the P-type buried layer 102 at two ends of the wafer substrate, wherein the ion implantation conditions are as follows: dosage is 4e 15-8 e15cm -2 Energy of 60-100 KeV.
The redistribution conditions are as follows: pure N 2 The atmosphere annealing temperature is 1100-1150 ℃ and the time is 100-120 min. And removing the oxide layer.
5) Growing an N-type epitaxial layer 103 on the surface of the silicon wafer, wherein the temperature is 1100-1150 ℃, the thickness is 5-30 mu m, and the resistivity is 4-40 omega cm;
6) Thermally grown oxide layer of thickness of
7) And (3) carrying out three times of photoetching, and then carrying out diffusion on N-type through regions 106 at two ends of a cell of the N-type epitaxial layer 103, wherein the diffusion is concretely carried out by adopting a constant impurity surface concentration method, an oxide layer with the thickness of 50-100 nm grows before the diffusion, and the diffusion conditions of the constant impurity surface concentration method are as follows: PCL3 gas source, anaerobic condition, temperature 1100-1150 deg.C, time 100-1500 min; removing an oxidation layer;
8) Growing a thin oxide layerThe temperature is 1000-1020 ℃, the time is 30-40 min, and the pure dry oxidation condition is adopted.
And (3) performing four times of photoetching, and then implanting P-type isolation penetrating regions 105 at two ends of the device, wherein the ion implantation conditions are as follows: dosage of 1e 15-8 e15cm -2 Energy of 60-100 KeV.
9) LP depositing SIN, thickness at
10 Fifth photoetching, lightAfter etching SIN, N-type impurity with one dose of 1E11-5E11 and energy of 60-100KeV is injected, and then a thick oxide layer is grown The temperature is 1000-1050 ℃ and the time is 200-400 min, and the dry humidifying oxidation condition is adopted.
The annealing redistribution conditions are: pure N 2 The atmosphere annealing temperature is 1100-1150 ℃ and the time is 100-120 min.
11 Residual SIN peel, a layer thickness of aboutIs formed on the substrate. And growing a thin oxide layerThe temperature is 1000-1020 ℃, the time is 30-40 min, and the pure dry oxidation condition is adopted.
12 Six times of photoetching, and then carrying out injection of the P-type collector region 107 and the P-type emitter region 109, specifically adopting the injection with glue, wherein the ion injection conditions are as follows: the dose is 1e 14-5 e14cm < -2 >, the energy is 60-100KeV, and the redistribution condition is as follows: under the anaerobic condition, the temperature is 1100-1150 ℃ and the time is 100-200 min;
13 Seven times of photoetching, the N-type heavily doped base region 108 and the N-type heavily doped heterocyclic region 104 are implanted after photoetching, specifically, the photoresist implantation is adopted, and the ion implantation conditions are as follows: the dose is 1e 15-5 e15cm < -2 >, the energy is 40-80 KeV, and the redistribution condition is as follows: anaerobic condition, temperature 950-1000 deg.c, time 30-60 min;
14 LP deposition of TEOS, thickness at
15 Eight times of photoetching, and etching a contact hole; the contact hole locations are located within the P-type collector region 107 and the P-type emitter region 109, and in the middle of the N-type reach-through region 106.
16 Metal Al is deposited on the surface of the whole wafer, and aluminum is etched for nine times by photoetching;
17 Alloy, furnace temperature is 550 ℃, and the time is 10 min-30 min;
18 Planarization dielectric deposition and etching to form IMD planarization dielectric 119;
19 Ten times of photoetching, and etching a through hole; the via is located over all of the emitter first layer metal 114, over a portion of the collector first layer metal 113, and over a portion of the base first layer metal 115.
20 A second layer of metal is deposited, metal AL is deposited on the surface of the whole wafer, and aluminum is etched for eleven times;
21 Alloy, furnace temperature 550 ℃, time 10 min-30 min, passivation layer growth;
22 Twelve times of photoetching to form a pressure welding spot;
23 Low-temperature annealing at 500-510 deg.c for 30min;
24 Silicon wafer initial testing, cutting, loading, sintering and packaging.
Claims (4)
1. The lateral high-voltage power bipolar junction transistor is characterized by comprising a P-type substrate (100), an N-type buried layer (101), a P-type buried layer (102), an N-type epitaxial layer (103), an N-type heavily doped heterocyclic region (104), a P-type isolation penetration region (105), an N-type penetration region (106), a P-type collector region (107), an N-type heavily doped base region (108), a P-type emitter region (109), a pre-oxidation layer (110), a field oxide layer (111), a TEOS metal front dielectric layer (112), a collector first metal (113), an emitter first metal (114), a base first metal (115), an emitter second metal (116), a collector second metal (117), a base second metal (118) and an IMD planarization medium (119);
the N-type buried layer (101) is positioned in the middle of the upper surface of the P-type substrate (100);
the P-type buried layers (102) are positioned at two ends of the upper surface of the P-type substrate (100);
the N-type epitaxial layer (103) is positioned above the N-type buried layer (101), and the N-type epitaxial layer (103) is in contact with the P-type substrate (100), the N-type buried layer (101) and the P-type buried layer (102);
the P-type isolation penetrating region (105) is contacted with two ends of the N-type epitaxial layer (103), and the bottom of the P-type isolation penetrating region (105) is connected with the top of the P-type buried layer (102);
the N-type through region (106) is positioned at the left end of the N-type buried layer (101), and the bottom of the N-type through region (106) is connected with the top of the N-type buried layer (101);
the P-type collector region (107) is formed of one or more repeating structural units; the P-type collector region (107) comprises an annular collector region and a central circular collector region; the P-type collector region (107) is positioned in the middle of the N-type epitaxial layer (103);
the P-type emission region (109) is positioned in the middle of the N-type epitaxial layer (103); the P-type emission regions (109) are positioned between the P-type collector regions (107);
the N-type heavily doped heterocyclic region (104) is positioned between the P-type collector region (107) and the P-type emitter region (109);
two ends of the N-type heavily doped heterocyclic region (104) are contacted with the N-type epitaxial layer (103);
the N-type heavily doped heterocyclic region (104) is positioned in the N-type epitaxial layer (103), and the surface of the N-type heavily doped heterocyclic region is flush with the surface of the N-type epitaxial layer (103);
the N-type heavily doped base region (108) is in a ring-shaped structure, one end of the N-type heavily doped base region (108) is positioned in the middle of the N-type through region (106), and the other end of the N-type heavily doped base region is positioned in the N-type epitaxial layer (103);
the field oxide layer (111) is positioned outside the upper surface of the N-type through region (106), the upper surface between the N-type through region (106) and the P-type collector region (107), the upper surface between the P-type collector region (107) and the N-type heavily doped base region (108) and outside the upper surface of the N-type heavily doped base region (108); the N-type heavily doped base region (108) is positioned at one end in the N-type epitaxial layer (103);
the pre-oxygen layer (110) is positioned between the field oxygen layers (111) above the N-type epitaxial layer (103);
the TEOS metal front dielectric layer (112) covers the whole device surface at the position where the contact hole is not opened; the contact holes are respectively positioned in the P-type collector region (107), the P-type emitter region (109) and the N-type through region (106), and are respectively contacted with the P-type collector region (107), the P-type emitter region (109) and the N-type heavily doped base region (108);
the first metal layer (114) of the emitter is positioned in the contact hole of the P-type emitter region (109), and the first metal layer (114) of the emitter is contacted with the P-type emitter region (109) and the TEOS metal front dielectric layer (112); the edge metal dimension of the emitter first layer metal (114) does not exceed the P-type emitter region (109);
the first metal layer (113) of the collector is positioned in a contact hole of the P-type collector region (107), and the first metal layer (113) of the collector is contacted with the P-type collector region (107) and the TEOS metal front dielectric layer (112); the edge metal size of the collector first layer metal (113) exceeds the length of two ends of the P-type collector region (107) by 1-5 times of the junction depth;
the base electrode first layer metal (115) is positioned in a contact hole of the N-type through region (106), and the base electrode first layer metal (115) is contacted with the N-type heavily doped base region (108) and the TEOS metal front dielectric layer (112); the edge metal size of the base first layer metal (115) does not exceed the N-type heavily doped base region (108);
the IMD planarization medium (119) is positioned at the position of the non-opened through hole above the collector first layer metal (113), the emitter first layer metal (114) and the base first layer metal (115); the through holes are positioned above the first layer metal (114) of the emitter, above a partial region of the first layer metal (113) of the collector and above a partial region of the first layer metal (115) of the base;
the emitter second layer metal (116) is positioned above all through holes formed by the emitter first layer metal (114); the base second layer metal (118) is positioned above all through holes formed by the base first layer metal (115);
the second metal layer (117) of the collector is positioned above all through holes formed by the first metal layer (113) of the collector;
the P-type emitter region (109) is formed of one or more repeating structural units.
2. A lateral high voltage power bipolar junction transistor according to claim 1, wherein: the materials of the P-type substrate (100) and the N-type epitaxial layer (103) comprise bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.
3. A method of fabricating a lateral high voltage power bipolar junction transistor according to claim 1, comprising the steps of:
1) Providing a P-type substrate (100) and growing an oxide layer;
2) Performing primary photoetching, etching photoresist, growing an oxide layer, and performing injection of an N-type buried layer (101);
3) Performing secondary photoetching, growing an oxide layer after photoresist removal by photoetching, and performing P-type buried layer (102) injection;
4) Growing an N-type epitaxial layer (103), and thermally growing an oxide layer;
5) Performing three times of photoetching, and then performing N-type through region (106) diffusion at two ends of a cell of the N-type epitaxial layer (103) to grow an oxide layer;
6) Performing four times of photoetching, performing P-type isolation penetrating region (105) injection at two ends of the device, and performing LP deposition on SIN;
7) Five times of photoetching, after photoetching SIN, injecting N-type impurities, and growing an oxide layer;
8) Stripping residual SIN and growing an oxide layer;
9) Performing six times of photoetching, and performing injection of the P-type collector region (107) and the P-type emitter region (109) after photoetching;
10 Seven times of photoetching, and then injecting the N-type heavily doped base region (108) and the N-type heavily doped heterocyclic region (104);
11 LP deposition of tetraethyl orthosilicate (TEOS);
12 Eight times of photoetching, etching a contact hole, wherein the contact hole is positioned in the P-type collector region (107), the P-type emitter region (109) and the middle of the N-type through region (106);
13 A first layer of metal is deposited, and aluminum is etched for nine times by photoetching and back etching;
14 Alloy, planarizing dielectric deposition and etching to form an IMD planarizing dielectric (119);
15 Ten times of photoetching, and etching a through hole; the through holes are positioned above the first layer metal (114) of the emitter, above a partial region of the first layer metal (113) of the collector and above a partial region of the first layer metal (115) of the base;
16 A second metal deposition, eleven times photoetching and back etching aluminum;
17 Alloy, growing passivation layer;
18 Twelve times of photoetching to form a pressure welding spot;
19 After low-temperature annealing, performing initial testing, cutting, loading, sintering and packaging test on the silicon wafer;
the P-type emitter region (109) is formed of one or more repeating structural units.
4. A method of manufacturing a lateral high voltage power bipolar junction transistor according to claim 3, wherein: the materials of the P-type substrate (100) and the N-type epitaxial layer (103) comprise bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.
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