CN107911188A - Optical communication transmission network AMC based on FPGA draws fishplate bar and its implementation - Google Patents
Optical communication transmission network AMC based on FPGA draws fishplate bar and its implementation Download PDFInfo
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- CN107911188A CN107911188A CN201711330461.5A CN201711330461A CN107911188A CN 107911188 A CN107911188 A CN 107911188A CN 201711330461 A CN201711330461 A CN 201711330461A CN 107911188 A CN107911188 A CN 107911188A
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/40—Transceivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1652—Optical Transport Network [OTN]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0003—Switching fabrics, e.g. transport network, control network
- H04J2203/0005—Switching elements
- H04J2203/0007—Space switch details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0003—Switching fabrics, e.g. transport network, control network
- H04J2203/0012—Switching modules and their interconnections
- H04J2203/0016—Crossbar
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Multi Processors (AREA)
Abstract
The invention discloses a kind of optical communication transmission network AMC based on FPGA to draw fishplate bar and its implementation.Drawing fishplate bar includes power supply module, control management module, clock module and Service Processing Module, power supply module is connected with clock module, Service Processing Module, control management module respectively, clock module is connected with Service Processing Module, control management module respectively, clock module, Service Processing Module and control management module are connected with golden finger respectively, and golden finger is connected with power supply module.Being uniformly processed for a variety of access signals can be realized by drawing fishplate bar by this, including access, the FEC error correction of OTN, the demapping of SDH, the high order cross of SDH and the low order of OTN signals and SDH signals are intersected, the solution POS of SDH.The AMC plates realized using this method meet SDN thoughts, and the equipment of composition is more flexible, while use two panels FPGA finishing service processing functions, and the division of labor is clear and definite, and orderliness is clear, is conducive to the realization of function.
Description
Technical field
The present invention relates to optical communication technique, more particularly to a kind of optical communication transmission network AMC based on FPGA draw fishplate bar and its
Implementation method.
Background technology
The existing OTN signals of signal of optical communication transmission network access at present have SDH signals again, and the processing to OTN signals mainly has FEC
Error correction and signal demapping, the processing to SDH signals mainly has high order cross, low order to intersect reconciliation POS, if to meet owning
, it is necessary to which plurality of devices builds a processing platform, its cost is high, inconvenient to use for these requirements to signal processing.
The content of the invention
In view of prior art situation and defect, the present invention provides a kind of optical communication transmission network AMC based on FPGA and draws fishplate bar
And its implementation.A variety of access processing functions can be achieved in the present invention, are respectively：The access of OTN signals and connecing for SDH signals
Enter；The FEC error correction of OTN signals and SDH signal demapping functions；The high order cross and low order interleaving function of SDH signals；SDH believes
Number solution POS functions.
Present invention introduces SDN（Software defined network）Thought, has built a flexible optic communication using fpga chip and has passed
Defeated net AMC draws fishplate bar, this draws fishplate bar and meets ATCA standards, and can complete a variety of accesses by two fpga chips on AMC plates believes
Number be uniformly processed.
To achieve these goals, the present invention adopts the technical scheme that：A kind of optical communication transmission network AMC based on FPGA
Draw fishplate bar, it is characterised in that including power supply module, control management module, clock module and Service Processing Module, power supply module point
Not with clock module, Service Processing Module, control management module be connected, clock module respectively with Service Processing Module, control pipe
Module connection is managed, clock module, Service Processing Module and control management module are connected with golden finger respectively, golden finger and power supply mould
Block connects.
The power supply module includes two kinds of Linear power supply chips, including a piece of double loop power supply chip and four four-way power supplies
Chip, the model LTM4620 of double loop power supply chip, the model LTM4644 of four-way power supply chip, all Linear power supply chips
Input be 12V power supplys, the output terminal of all Linear power supply chips is connected with control management module.
The control management module includes the model of STM32 chips and FLASH, STM32 chip
Model M25P128, the STM32 chip of STM32F437NIH6, FLASH are connected by SPI mouthfuls with FLASH, for storing and reading
Send routing information, realize power-down protection, STM32 chips are connected by FE mouthfuls with golden finger, for being carried out with other boards
Information exchange, STM32 chips are connected by GPIO mouthfuls with power supply module, and for the electric sequence of Control card, STM32 chips lead to
ADC mouthfuls are crossed with power supply module to be connected, for monitoring the state of power rail, STM32 chips are connected by I2C mouthfuls with clock module,
For configuration and monitoring clock chip operation state, STM32 chips are connected by SPI mouthfuls with Service Processing Module, for configuring
Board routing iinformation and monitoring data link state.
The clock module includes two ZARLINK clock chips and 1 local crystal oscillator, ZARLINK clock chip types
Number it is ZL30165GDG2, local crystal oscillator model 530BC155M520DGR, the hpdiff0 of first ZARLINK clock chip
Pin, hpdiff2 pins, hpdiff4 pins, hpdiff6 pins are managed with the Ref0 of second ZARLINK clock chip respectively
Foot, Ref1 pins, Ref2 pins, the connection of Ref3 pins, the Ref4 pins connection of second ZARLINK clock chip are local brilliant
Shake, the Ref5 pins of second ZARLINK clock chip connect golden finger with hpout4 pins.
The Service Processing Module includes two panels fpga chip, the model XC7K410T- of FPGA1 chips
The four road SERDES closed tubes of model XC7K325T-2FFG900I, the FPGA1 chip BANK117 of 3FFG900E, FPGA2 chip
Foot is connected with the four road SERDES hair pins of FPGA2 chips BANK118 respectively, the four road SERDES hairs of FPGA1 chips BANK118
Pin is connected with the four road SERDES closed tube feet of FPGA2 chips BANK118 respectively, the four road SERDES of FPGA1 chips BANK115
Hair pin of the closed tube foot respectively with four optical modules is connected, and the four road SERDES of FPGA1 chips BANK117 hair pin is respectively with four
The closed tube foot of a optical module is connected.
A kind of optical communication transmission network AMC based on FPGA draws fishplate bar implementation method, it is characterised in that the implementation method bag
Include OTN signals access processing workflow, SDH signals low-order and high-order cross processing workflow and SDH signal solutions POS processing work
Flow, wherein the OTN signals access processing workflow has following steps：
（1）, FPGA1 chips by BANK115 access four road OTN signals, and to OTN signals carry out solution FEC correction process；
（2）, FPGA1 chips the processing of SDH signals demappings is carried out to the signal after error correction, the signal after processing is SDH signals；
（3）, FPGA1 chips pointer regulation is carried out to the SDH signals of demapping, make SDH signals synchronous, believe easy to the SDH of rear end
The processing of number time-slot cross；
（4）, FPGA1 chips SDH signals are sent to by FPGA2 chips by BANK118, FPGA2 chips carry out SDH signals high
Rank cross processing, and be sent to by BANK115-BANK117 outside AMC plates；
（5）, the exterior loading plate being equipped with or cross board coordinate that to complete SDH space crossed；
（6）, FPGA2 chips the SDH signals sent from external bearer plate or cross board are received by BANK115-BANK117,
Carry out high order cross processing.
The SDH signal low-order and high-order cross processing workflows have following steps：
（1）, FPGA1 chips by BANK115 access four road SDH signals, to SDH signals carry out pointer regulation processing, believe SDH
Number synchronization, easy to the SDH signal slot cross processings of rear end；
（2）, FPGA1 chips to after pointer regulation SDH signals carry out high order cross, restrained SDH signals, and pass through
Signal after convergence is sent to outside AMC plates by BANK115-BANK117；
（3）, the exterior loading plate being equipped with or cross board coordinate that to complete SDH space crossed；
（4）, FPGA2 chips the SDH signals sent from external bearer plate or cross board are received by BANK115-BANK117,
Carry out pointer leakage processing；
（5）, FPGA2 chips low order cross processing is carried out to the SDH signals of pointer leakage；
The SDH signal solutions POS processing workflows perform following steps：
（1）, FPGA1 chips by BANK115 access four road SDH signals, to SDH signals carry out pointer regulation processing, believe SDH
Number synchronization, easy to the SDH signal slot cross processings of rear end；
（2）, FPGA1 chips to after pointer regulation SDH signals carry out high order cross processing, will carry variety classes POS signals
SDH signals classify, and SDH signals after classification are sent to outside AMC plates by BANK115-BANK117；
（3）, the exterior loading plate being equipped with or cross board coordinate that to complete SDH space crossed；
（4）, FPGA2 chips the SDH signals sent from external bearer plate or cross board are received by BANK115-BANK117,
Carry out solution POS processing.
The beneficial effects of the invention are as follows：Being uniformly processed for a variety of access signals, including OTN letters can be realized by drawing fishplate bar by this
Number the access and access of SDH signals, the FEC error correction of the OTN signals and demapping of SDH signals, the high order cross of SDH signals and
Low order is intersected, the solution POS of SDH signals.Using this method can make each AMC plates FPGA2 chips only need to support it is a type of
POS signal processings are solved, substantially reduce the resource requirement of FPGA.The AMC plates realized using this method meet SDN thoughts, form
Equipment it is more flexible, while use two panels FPGA finishing service processing functions, the division of labor is clear and definite, and orderliness is clear, is conducive to function
Realization.
Brief description of the drawings
Fig. 1 is AMC plates overall system diagram of the present invention；
Fig. 2 is AMC plates power supply module circuit block diagram of the present invention；
Fig. 3 is AMC plates of the present invention control management modular circuit block diagram；
Fig. 4 is AMC plates clock module circuit diagram of the present invention；
Fig. 5 is AMC plates Service Processing Module circuit diagram of the present invention；
Fig. 6 is the OTN signals access processing work flow diagram of the present invention；
Fig. 7 is the SDH signal low-order and high-order cross processing work flow diagrams of the present invention；
The SDH signal solutions POS that Fig. 8 is the present invention handles work flow diagram.
Embodiment
The present invention will be further described below in conjunction with the accompanying drawings.
As shown in Figure 1, AMC, which draws fishplate bar, includes power supply module, control management module, clock module and Service Processing Module,
Power supply module respectively with clock module, Service Processing Module, control management module be connected, clock module respectively with business processing mould
Block, control management module connection, clock module, Service Processing Module and control management module are connected with golden finger respectively, golden hand
Finger is connected with power supply module.
As shown in Fig. 2, power supply module includes two kinds of Linear power supply chips, including a piece of double loop power supply chip and four four tunnels
Power supply chip, the model LTM4620 of double loop power supply chip, the model LTM4644 of four-way power supply chip, all Linear power supplys
The input of chip is 12V power supplys, and the output terminal of all Linear power supply chips is connected with control management module.
Power supply module is made of two kinds of Linear power supply chips, double loop power supply chip and four-way power supply chip, double loop power supply core
The model LTM4620 of piece, the model LTM4644 of four-way power supply chip, double loop power supply have used one, exportable two electricity
Two FPGA core power voltage supplies of rail, respectively Service Processing Module, Voltage rails 1V are pressed, four-way power supply has used four, point
It Wei not power except other Voltage rails of FPGA core voltage.The input of all Linear power supply chips is 12V, from golden finger or this plate
Power connector, except the power rail of control module, other power rail enable pins and the control module GPIO feet of power supply module
Connection, the electric sequence that board is completed by control module control, output and the control module ADC feet of all power rails of power supply module
Connection, completes the power supply status monitoring of board.
As shown in figure 3, control management module includes the model of STM32 chips and FLASH, STM32 chip
Model M25P128, the STM32 chip of STM32F437NIH6, FLASH are connected by SPI mouthfuls with FLASH, for storing and reading
Send routing information, realize power-down protection, STM32 chips are connected by FE mouthfuls with golden finger, for being carried out with other boards
Information exchange, STM32 chips are connected by GPIO mouthfuls with power supply module, and for the electric sequence of Control card, STM32 chips lead to
ADC mouthfuls are crossed with power supply module to be connected, for monitoring the state of power rail, STM32 chips are connected by I2C mouthfuls with clock module,
For configuration and monitoring clock chip operation state, STM32 chips are connected by SPI mouthfuls with Service Processing Module, for configuring
Board routing iinformation and monitoring data link state.
Control management module is connected by GPIO mouthfuls with the enable pin of each power rail of power supply module, controls power supply module
The electric sequence of each power rail, is connected by ADC mouthfuls of power rail outputs each with power supply module, monitors the defeated of each power rail
Whether normal go out voltage, be connected by I2C mouthfuls with clock module, the output of clock chip and monitoring clock in configurable clock generator module
The working status of chip, is connected by SPI mouthfuls with Service Processing Module, configures the routing iinformation and monitoring business processing mould of board
The working status of block, is connected with golden finger by FE mouthfuls, is exchanged for being controlled with outside with monitoring information.
As shown in figure 4, clock module includes two ZARLINK clock chips and 1 local crystal oscillator, ZARLINK clock cores
Piece model ZL30165GDG2, local crystal oscillator model 530BC155M520DGR, first ZARLINK clock chip
Hpdiff0 pins, hpdiff2 pins, hpdiff4 pins, hpdiff6 pins respectively with second ZARLINK clock chip
Ref0 pins, Ref1 pins, Ref2 pins, the connection of Ref3 pins, the Ref4 pins connection of second ZARLINK clock chip is originally
Ground crystal oscillator, the Ref5 pins of second ZARLINK clock chip connect golden finger with hpout4 pins.
The ZARLINK clock chips of clock module have four digital phase-locked loop DPLL0-DPLL3, have eight reference clocks defeated
Entrance ref0-ref7, there is 16 clock delivery outlets, wherein eight difference output mouth hpdiff0-hpdiff7, eight single-ended defeated
Hpout0-hpout7 is exported, all input/output ports can be used with any one DPLL interconnection.The configuration of clock module
Mode is mainly in two kinds of situation：OTN signals access configuration mode and SDH signals access configuration mode, concrete scheme such as table 1 below
Shown in table 4：
Table 1
Table 2
Table 3
Table 4
When OTN signals access, first clock chip is mainly responsible for the OTN signals recovered clock of four road 167.33M in proportion
155.52M is down to, the clock per 155.52M all the way replicates two parts, and portion is used for solving SDH signals from OTN signals to FPGA1
Map out and, portion is used for selecting system clock to second clock chip.Second clock chip local crystal oscillator passes through connection
DPLL0 provides SERDES clocks and BUFG clocks to two panels FPGA, and ref0, ref1, ref2, ref3 are selected all the way by DPLL1
It is output to that golden finger is synchronous into row clock with other boards, ref5 replicates 6 parts of clocks to FPGA1's and FPGA2 by DPLL2
SERDES, as SDH business processings.
SDH signals access when, first clock chip be mainly responsible for by the clock of four road 155.52M respectively replicate two parts, one
Part is used for handling SDH pointer regulations to FPGA1, and portion is used for selecting system clock to second clock chip.Second clock
Chip local crystal oscillator provides SERDES clocks and BUFG clocks by connecting DPLL0 to two panels FPGA, ref0, ref1, ref2,
Ref3 pins（Ref0-ref7 is the reference clock input pin of clock chip, and corresponding is the pin of chip）Pass through DPLL1
（DPLL0-DPLL3 is four digital phase-locked loops inside clock chip）Selection is output to golden finger and is carried out with other boards all the way
Clock is synchronous, and ref5 pins replicate six parts of clocks to FPGA1 chips and the SERDES of FPGA2 chips by DPLL2, as SDH
Business processing.
As shown in figure 5, Service Processing Module includes two panels fpga chip, the model XC7K410T- of FPGA1 chips
The four road SERDES closed tubes of model XC7K325T-2FFG900I, the FPGA1 chip BANK117 of 3FFG900E, FPGA2 chip
Foot is connected with the four road SERDES hair pins of FPGA2 chips BANK118 respectively, the four road SERDES hairs of FPGA1 chips BANK118
Pin is connected with the four road SERDES closed tube feet of FPGA2 chips BANK118 respectively, the four road SERDES of FPGA1 chips BANK115
Hair pin of the closed tube foot respectively with four optical modules is connected, and the four road SERDES of FPGA1 chips BANK117 hair pin is respectively with four
The closed tube foot of a optical module is connected.
BANK is the packet of FGPA high speeds SERDES, and the two FPGA high speed SERDES interfaces that the present invention selects all are 16
A, every four are one group, and totally four groups, be BANK115-BANK118 respectively.
System is divided into four function modules：Power supply module, control management module, clock module and Service Processing Module.
The input of power supply module comes from golden finger, is+12V Voltage rails, by the conversion of multiple DC/DC power modules, can manage in order to control
Manage module, clock module and Service Processing Module and each required Voltage rails are provided.Control management module Voltage rails directly by
Power supply module provides, and the Voltage rails of other modules are provided by control management module control power supply module, each to meet
The requirement of chip electric sequence.
Clock module is connected by differential lines with golden finger, clock all the way is externally sent by golden finger, and receive outside
Clock all the way, be connected by differential lines with Service Processing Module, receive the line-recovered clock that sends of Service Processing Module, warp
Unified system clock is fed back in the selection for crossing priority to Service Processing Module.
Service Processing Module is connected by differential lines with golden finger, is received by golden finger from exterior high-speed data,
And high-speed data is externally sent, while optical module of the Service Processing Module equipped with four SFP+, it can receive from fiber link
On optical signal, and processed high speed signal is returned into fiber link by optical signal.
The supply voltage that AMC draws fishplate bar is 12V, may be from the power connector of AMC edge connectors or board itself, draws and connect
Plate at most can configure four SFP+ optical modules, the high speed signal transmitted for reception optical fiber, and send processed height to optical fiber
Fast signal, interacting for high-speed data, clock and control signal can be carried out by golden finger with other boards by drawing fishplate bar, easy to multiple
Draw the collaborative work between fishplate bar.AMC, which draws fishplate bar, to arrange in pairs or groups with one piece of loading plate, form 1U equipment, also can be with multiple loading plates
Collocation, forms rack-mount unit.
System work main-process stream be：Power supply module is powered for all chips of board, and Service Processing Module, which receives, to be come
From the high-speed data of optical fiber, recover the line clock in high-speed data and be sent to clock module, clock module is by preferential
Level selection and frequency conversion, required clock, clock of the Service Processing Module according to clock module feedback are provided for Service Processing Module
High-speed data is parsed and is descrambled, and according to the control instruction that sends over of control management module, high-speed data is done into
The processing of one step.
Service Processing Module follows SDN principles, can be configured according to different access service types and process demand different
Program.The invention mainly comprises three kinds of business processing types of workflows：OTN signals access processing, SDH signals low-order and high-order are handed over
Fork processing and SDH signal solution POS processing.
As shown in fig. 6, the workflow of OTN signals access processing is broadly divided into following six step：
1）FPGA1 accesses 4 road OTN signals by BANK115, and solution FEC correction process is carried out to OTN signals；
2）FPGA1 carries out the signal after error correction the processing of SDH signals demapping, and the signal after processing is SDH signals；
3）FPGA1 carries out pointer regulation to the SDH signals of demapping, makes SDH signals synchronous, easy to the SDH signal slots of rear end
Cross processing；
4）SDH signals are sent to FPGA2 by FPGA1 by BANK118, and FPGA2 carries out SDH signals high order cross processing, and
It is sent to by BANK115-BANK117 outside AMC plates；
5）This step needs external bearer plate or cross board to coordinate completion SDH space crossed；
6）FPGA2 receives the SDH signals sent from external bearer plate or cross board by BANK115-BANK117, carries out high
Rank cross processing.
It is mainly complete to the dissection process of SDH signals, FPGA2 chips mainly to complete OTN signals for FPGA1 chips in whole process
Into the processing of two-stage SDH signals high order cross, function is well defined, clear process.
As shown in fig. 7, the workflow of SDH signal low-order and high-order cross processings is broadly divided into following five steps：
1）FPGA1 accesses 4 road SDH signals by BANK115, and pointer regulation processing is carried out to SDH signals, makes SDH signals synchronous,
Easy to the SDH signal slot cross processings of rear end；
2）FPGA1 carries out high order cross to the SDH signals after pointer regulation, is restrained SDH signals, and pass through BANK115-
Signal after convergence is sent to outside AMC plates by BANK117；
3）This step needs external bearer plate or cross board to coordinate completion SDH space crossed；
4）FPGA2 receives the SDH signals sent from external bearer plate or cross board by BANK115-BANK117, is referred to
Processing is let out under pin；
5）FPGA2 carries out low order cross processing to the SDH signals of pointer leakage.
FPGA1 chips mainly complete the high order cross processing of SDH signals in whole process, have restrained signal volume, have reduced
The pressure of back-end chip low order cross processing, FPGA2 chips are mainly completed the low order cross processing of SDH signals, are finally completed
SDH signal gathering functions.
As shown in figure 8, the workflow of SDH signal solutions POS processing is broadly divided into following four step：
1）FPGA1 accesses 4 road SDH signals by BANK115, and pointer regulation processing is carried out to SDH signals, makes SDH signals synchronous,
Easy to the SDH signal slot cross processings of rear end；
2）FPGA1 carries out high order cross processing to the SDH signals after pointer regulation, and the SDH for carrying variety classes POS signals is believed
Number classify, and SDH signals after classification are sent to outside AMC plates by BANK115-BANK117；
3）This step needs external bearer plate or cross board to coordinate completion SDH space crossed；
4）FPGA2 receives the SDH signals sent from external bearer plate or cross board by BANK115-BANK117, is solved
POS processing.
FPGA1 chips mainly complete the classification of POS signals in whole process, and FPGA2 chips mainly complete the solution of SDH signals
POS processing, can make each AMC plates FPGA2 chips only need to support a type of solution POS signal processings, greatly using this method
The big resource requirement for reducing FPGA.
Claims (2)
1. a kind of optical communication transmission network AMC based on FPGA draws fishplate bar, it is characterised in that including power supply module, control management mould
Block, clock module and Service Processing Module, power supply module connect with clock module, Service Processing Module, control management module respectively
Connect, clock module is connected with Service Processing Module, control management module respectively, clock module, Service Processing Module and control pipe
Reason module is connected with golden finger respectively, and golden finger is connected with power supply module；
The power supply module includes two kinds of Linear power supply chips, including a piece of double loop power supply chip and four four-way power supply cores
Piece, the model LTM4620 of double loop power supply chip, the model LTM4644 of four-way power supply chip, all Linear power supply chips
Input and be connected respectively with control management module for 12V power supplys, the output terminal and output terminal enable signal of all Linear power supply chips；
The control management module includes the model STM32F437NIH6 of STM32 chips and FLASH, STM32 chip,
Model M25P128, the STM32 chip of FLASH is connected by SPI mouthfuls with FLASH, real for storing and reading routing iinformation
Existing power-down protection, STM32 chips are connected by FE mouthfuls with golden finger, for carrying out information exchange, STM32 with other boards
Chip is connected by GPIO mouthfuls with power supply module, and for the electric sequence of Control card, STM32 chips pass through ADC mouthfuls and power supply
Module is connected, and for monitoring the state of power rail, STM32 chips are connected by I2C mouthfuls with clock module, for configuring and monitoring
Clock chip working status, STM32 chips are connected by SPI mouthfuls with Service Processing Module, for configuring board routing iinformation simultaneously
Monitoring data link state；
The clock module includes two ZARLINK clock chips and 1 local crystal oscillator, ZARLINK clock chip models
ZL30165GDG2, local crystal oscillator model 530BC155M520DGR, the hpdiff0 pins of first ZARLINK clock chip,
Hpdiff2 pins, hpdiff4 pins, hpdiff6 pins Ref0 pins, the Ref1 with second ZARLINK clock chip respectively
Pin, Ref2 pins, the connection of Ref3 pins, the local crystal oscillator of Ref4 pins connection of second ZARLINK clock chip, second
The Ref5 pins of ZARLINK clock chips connect golden finger with hpout4 pins；
The Service Processing Module includes two panels fpga chip, the model XC7K410T-3FFG900E of FPGA1 chips,
The four road SERDES closed tubes feet of model XC7K325T-2FFG900I, the FPGA1 chip BANK117 of FPGA2 chips respectively with
The four road SERDES hair pins of FPGA2 chips BANK118 are connected, the four road SERDES hair pin difference of FPGA1 chips BANK118
It is connected with the four road SERDES closed tube feet of FPGA2 chips BANK118, the four road SERDES closed tubes feet point of FPGA1 chips BANK115
Hair pin not with four optical modules is connected, the four road SERDES of FPGA1 chips BANK117 hair pin respectively with four optical modules
Closed tube foot be connected.
2. a kind of draw fishplate bar implementation method using the optical communication transmission network AMC based on FPGA as claimed in claim 1, its feature
Be, the implementation method include OTN signals access processing workflow, SDH signals low-order and high-order cross processing workflow and
SDH signal solutions POS handles workflow, wherein the OTN signals access processing workflow has following steps：
（1）, FPGA1 chips by BANK115 access four road OTN signals, and to OTN signals carry out solution FEC correction process；
（2）, FPGA1 chips the processing of SDH signals demappings is carried out to the signal after error correction, the signal after processing is SDH signals；
（3）, FPGA1 chips pointer regulation is carried out to the SDH signals of demapping, make SDH signals synchronous, believe easy to the SDH of rear end
The processing of number time-slot cross；
（4）, FPGA1 chips SDH signals are sent to by FPGA2 chips by BANK118, FPGA2 chips carry out SDH signals high
Rank cross processing, and be sent to by BANK115-BANK117 outside AMC plates；
（5）, the exterior loading plate being equipped with or cross board coordinate that to complete SDH space crossed；
（6）, FPGA2 chips the SDH signals sent from external bearer plate or cross board are received by BANK115-BANK117,
Carry out high order cross processing；
The SDH signal low-order and high-order cross processing workflows have following steps：
（1）, FPGA1 chips by BANK115 access four road SDH signals, to SDH signals carry out pointer regulation processing, believe SDH
Number synchronization, easy to the SDH signal slot cross processings of rear end；
（2）, FPGA1 chips to after pointer regulation SDH signals carry out high order cross, restrained SDH signals, and pass through
Signal after convergence is sent to outside AMC plates by BANK115-BANK117；
（3）, the exterior loading plate being equipped with or cross board coordinate that to complete SDH space crossed；
（4）, FPGA2 chips the SDH signals sent from external bearer plate or cross board are received by BANK115-BANK117,
Carry out pointer leakage processing；
（5）, FPGA2 chips low order cross processing is carried out to the SDH signals of pointer leakage；
The SDH signal solutions POS processing workflows perform following steps：
（1）, FPGA1 chips by BANK115 access four road SDH signals, to SDH signals carry out pointer regulation processing, believe SDH
Number synchronization, easy to the SDH signal slot cross processings of rear end；
（2）, FPGA1 chips to after pointer regulation SDH signals carry out high order cross processing, will carry variety classes POS signals
SDH signals classify, and SDH signals after classification are sent to outside AMC plates by BANK115-BANK117；
（3）, the exterior loading plate being equipped with or cross board coordinate that to complete SDH space crossed；
（4）, FPGA2 chips the SDH signals sent from external bearer plate or cross board are received by BANK115-BANK117,
Carry out solution POS processing.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711330461.5A CN107911188A (en) | 2017-12-13 | 2017-12-13 | Optical communication transmission network AMC based on FPGA draws fishplate bar and its implementation |
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| CN201711330461.5A CN107911188A (en) | 2017-12-13 | 2017-12-13 | Optical communication transmission network AMC based on FPGA draws fishplate bar and its implementation |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115017079A (en) * | 2022-05-31 | 2022-09-06 | 深圳市商汤科技有限公司 | Power-off method of management equipment, chip, PCIe card and business processing equipment |
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2017
- 2017-12-13 CN CN201711330461.5A patent/CN107911188A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115017079A (en) * | 2022-05-31 | 2022-09-06 | 深圳市商汤科技有限公司 | Power-off method of management equipment, chip, PCIe card and business processing equipment |
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