CN107910315B - Chip package - Google Patents

Chip package Download PDF

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Publication number
CN107910315B
CN107910315B CN201711105653.6A CN201711105653A CN107910315B CN 107910315 B CN107910315 B CN 107910315B CN 201711105653 A CN201711105653 A CN 201711105653A CN 107910315 B CN107910315 B CN 107910315B
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conductive
substrate
chip
chips
chip package
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CN107910315A (en
Inventor
杜光东
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Shenzhen Shenglu IoT Communication Technology Co Ltd
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Shenzhen Shenglu IoT Communication Technology Co Ltd
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Priority to CN201711105653.6A priority Critical patent/CN107910315B/en
Publication of CN107910315A publication Critical patent/CN107910315A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A chip package comprises a substrate having a first surface and a second surface opposite to each other, a plurality of chips arranged on the first surface, a substrate arranged on the second surface, a plurality of first conductive members arranged at intervals between the substrate and the substrate, a plurality of second conductive members arranged in the substrate, a plurality of third conductive members arranged between the substrate and the chips, two adjacent chips connected by a conductive connecting member contacting the first surface, a plurality of first bonding pads arranged on the substrate and the substrate contacting side, and a plurality of chips passing through the first conductive members, the second conductive component and the third conductive component are electrically conducted with the substrate, a plurality of conductive columns are arranged on one surface of the substrate, which is back to the first bonding pad, the conductive columns penetrate through the substrate to be conducted with the first bonding pad, at least one conductive column is used for grounding, and the diameter of the conductive column used for grounding is larger than that of other conductive columns. The invention can solve the problems of high cost and poor heat dissipation when the data transmission between the chips is realized in the prior art.

Description

Chip package
Technical Field
The invention relates to the technical field of chips, in particular to a chip package.
Background
With the progress of science and technology, intelligent electronic products have gradually come into the lives of people, and a chip in the intelligent electronic products is a decisive factor for determining the performance of products. After the chip is produced, the chip needs to be packaged.
At present, as electronic products are developed towards portability and miniaturization, the size of chip packages is gradually miniaturized, the packaging pitch of mounting elements is developed towards finer pitch, the chip packages usually comprise a plurality of chips, and data transmission is needed between the chips.
In the prior art, a silicon through hole technology is adopted to open a hole in an adapter plate for realizing data transmission between a chip and the chip in chip packaging, so that a through hole penetrates through the upper surface and the lower surface of the adapter plate, metal wiring is carried out in the through hole, the chip is connected with a substrate through the metal wiring in the through hole, the packaging process of the realization mode is complex, and the cost is high. In addition, as the processing data of the chip is increased, the chip package manufactured by the process also has the problem of poor heat dissipation.
Disclosure of Invention
Therefore, the invention aims to provide a chip package to solve the problems of high cost and poor heat dissipation when data transmission between chips is realized in the chip package in the prior art.
A chip package comprises a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged, a plurality of chips are arranged on the first surface, a substrate is arranged on the second surface, a plurality of first conductive components arranged at intervals are arranged between the substrate and the substrate, a plurality of second conductive components are arranged in the substrate, a plurality of third conductive components are arranged between the substrate and the chips, two adjacent chips are connected through a conductive connecting piece, the conductive connecting piece is contacted with the first surface, a plurality of first bonding pads are arranged on one surface of the substrate contacted with the substrate, the chips are electrically conducted with the substrate through the first conductive components, the second conductive components and the third conductive components, a plurality of conductive columns are arranged on one surface of the substrate opposite to the first bonding pads, the conductive columns penetrate through the substrate to be conducted with the first bonding pads, and at least one conductive column is used for grounding, and the diameter of the conductive column used for grounding is larger than that of other conductive columns. .
According to the chip package provided by the invention, two adjacent chips are connected through a conductive connecting piece, the conductive connecting piece is contacted with the first surface of the substrate, namely a plurality of conductive connecting pieces are arranged between the chips and the substrate, data transmission between the adjacent chips can be realized through the conductive connecting pieces between the chips, through-silicon-via technology opening is not needed, the realization cost is low, the packaging process is simple, in addition, as a first conductive component is arranged between the substrate and the substrate, a second conductive component is arranged in the substrate, a plurality of third conductive components are arranged between the substrate and the chips, the chips are electrically conducted with the substrate through the first conductive component, the second conductive component and the third conductive components, the data transmission between the chips and the substrate is realized, and one surface of the substrate, which is back to the first bonding pad, is provided with a conductive column, and as the number of the conductive columns is multiple, one of the conductive columns is used for grounding, therefore, the conductive column can be used as a heat radiator while being conducted, and finally the heat radiation performance of chip packaging is improved.
In addition, the chip package according to the present invention may further have the following additional features:
furthermore, one surface of each chip facing the substrate is provided with a plurality of second bonding pads, and the conductive connecting piece between two adjacent chips is respectively connected with at least one of the second bonding pads on the two adjacent chips. The conductive connecting piece can be made of metal materials or polyimide or silicon nitride containing metal conductive wires inside.
The second bonding pad is additionally arranged on each chip, so that the electric connection capacity of the chip and the conductive connecting piece can be enhanced, the electric connection capacity between adjacent chips is improved, and the condition that data transmission is unstable between the chips is avoided.
Further, a plurality of reinforcing pieces are arranged on the first surface, the reinforcing pieces are located between the adjacent chips, and the reinforcing pieces extend beyond the edge of the substrate.
The reinforcing piece is additionally arranged on the first surface of the substrate and located between the adjacent chips, and meanwhile, the reinforcing piece extends beyond the edge of the substrate, so that the substrate can be effectively prevented from warping, and the structural strength and stability of chip packaging are improved.
Furthermore, an adhesive layer is arranged between the reinforcing piece and the substrate.
Wherein, add the viscose layer between reinforcement and the basement, guarantee that product reinforcement and basement can not drop after long-term the use, further promote chip package's structural strength and stability.
Further, the reinforcing member covers all of the side of the chip facing away from the substrate.
Wherein, because the reinforcer covers all chips and faces away from the substrate, can protect the chip from damage or be contaminated.
Further, the thermal conductivity of the stiffener is higher than the thermal conductivity of the substrate. The reinforcing member can be one or a combination of aluminum, copper and gold.
Wherein, because the coefficient of heat conductivity of reinforcement is higher than the coefficient of heat conductivity of basement, the heat energy that can the active absorption chip during operation produced to further promote the radiating effect of chip package.
Further, the distance between the first bonding pad positioned at the outermost side of the substrate and the first bonding pad positioned at the second outermost side of the substrate is smaller than the distance between the other adjacent first bonding pads.
Wherein, through the above-mentioned distance between the first pad of reasonable arrangement, can guarantee to have sufficient interval between the first pad that needs the wiring to can increase the width of wiring, can reduce product cost and the processing degree of difficulty.
Further, the outer surface of the conductive column is provided with a metal coating, and the thickness of the metal coating is 20-30 microns.
Wherein, set up the metallic coating through the surface at electrically conductive post, can guarantee to electrically connect stability between electrically conductive post and the corresponding electric elements, promote the reliability of product.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic cross-sectional structure diagram of a chip package according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of the distribution of the first pads on the substrate in FIG. 1;
fig. 3 is a schematic cross-sectional structure diagram of a chip package according to a second embodiment of the invention;
fig. 4 is a schematic cross-sectional structure diagram of a chip package according to a third embodiment of the invention;
fig. 5 is a schematic cross-sectional structure diagram of a chip package according to a fourth embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. Several embodiments of the invention are presented in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. As used herein, the terms "vertical," "horizontal," "left," "right," "up," "down," and the like are for illustrative purposes only and do not indicate or imply that the referenced device or element must be in a particular orientation, constructed or operated in a particular manner, and is not to be construed as limiting the present invention.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, a chip package 100 according to a first embodiment of the invention includes a substrate 11, where the substrate 11 has a first surface 111 and a second surface 112 disposed opposite to each other. The substrate 11 may comprise a dielectric material, such as an organic materialThe material may be polypropylene (PP) with glass fiber, epoxy resin (epoxy resin), Polyimide (Polyimide), cyanate ester (cyanateester), or a combination thereof, and it is understood that the substrate 11 may also be Polyimide (PI) or silicon nitride (Si)3N4) Or a semiconductor material such as silicon.
For convenience of description, in the present embodiment, the number of chips is described by taking three as an example, specifically, the chip 12a, the chip 12b, and the chip 12c, and the structure of each chip is the same, so in the present embodiment, the structure of only one chip is described by taking as an example. Note that, in the case where two chips or three or more chips are included in the chip package, the structure and principle between adjacent two chips are the same as in the present embodiment. Therefore, the present application is not limited to the case of three chips.
The second surface 112 is provided with a substrate 13, specifically, the substrate 13 is located at the bottom of the base 11, and the substrate 13 may be a dielectric material or a circuit board. The substrate 13 is used for electrically connecting with corresponding electronic components in the end product.
A plurality of first conductive members 14 are disposed between the base 11 and the substrate 13. The first conductive member 14 may be one or more of a conductive bump, a conductive ball, a solder bump, a solder ball.
The substrate 11 has a plurality of second conductive members 15 disposed therein. The second conductive member 15 may also be one or more of a conductive bump, a conductive ball, a solder bump, and a solder ball. The number of the second conductive members 15 and the number of the first conductive members 14 may be the same, and the number of the first conductive members 14 may be more than the number of the second conductive members 15. It should be noted that the first conductive member 14 and the second conductive member 15 should be disposed correspondingly as much as possible, i.e. the first conductive member 14 and the second conductive member 15 can be contacted to achieve electrical conduction.
A plurality of third conductive members 16 are disposed between the substrate 11 and the chip (including the chip 12a, the chip 12b, and the chip 12c), and it is understood that the third conductive members 16 may also be one or more of conductive bumps, conductive balls, solder bumps, and solder balls.
Two adjacent chips are connected through a conductive connecting piece 17, specifically, the conductive connecting piece 17 is arranged between the chip 12a and the chip 12b, and the conductive connecting piece 17 is also arranged between the chip 12b and the chip 12 c. And the conductive connection 17 is in contact with the first surface 111. The conductive connecting member 17 is, for example, a strip, and the conductive connecting member 17 may be made of metal, Polyimide (PI) or silicon nitride (Si) containing a metal conductive wire therein3N4). The conductive connecting member 17 is used for conducting with an electrical element on the chip 12a, the chip 12b or the chip 12c, and since the conductive connecting member 17 is also a conductive material, the electrical conduction between the chip 12a and the chip 12b or between the chip 12b and the chip 12c can be realized, so that the data transmission between adjacent chips is realized. In addition, when the conductive connecting member 17 is made of Polyimide (PI) or silicon nitride (Si) containing a metal conductive wire therein3N4) At least two end points of the metal conductive wires are exposed from the conductive connecting member 17 for conducting with the electrical components on the adjacent chips.
The surface of the substrate 13 contacting the substrate 11 is provided with a plurality of first pads 131, the number of the first pads 131 may be the same as the number of the first conductive members 14, the first pads 131 and the first conductive members 14 are correspondingly disposed, and the first conductive members 14 at corresponding positions are in contact with the first pads 131 for conduction.
Therefore, the chips 12a, 12b, and 12c can be electrically connected to the substrate 13 through the first conductive member 14, the second conductive member 15, and the third conductive member 16.
A plurality of conductive posts 132 are disposed on a surface of the substrate 13 opposite to the first pad 131, the conductive posts 132 penetrate through the substrate 13 to be electrically connected to the first pad 131, and at least one of the conductive posts 132 is used for grounding. The number of the conductive pillars 132 may be the same as the number of the first pads 131, and the sum of the heights of the conductive pillars 132 and the first pads 131 may be equal to the height of the substrate 13, or may be higher than the height of the substrate 13, and may be specifically set according to the actual situation of the circuit board of the product. For better grounding and heat dissipation effects, for each chip, for example, for the chip 12a, the diameter of the conductive pillar 132 for grounding may be larger than the diameter of the other conductive pillars 132. The conductive posts 132 may be implemented as copper posts or aluminum posts.
In addition, in this embodiment, the distance between the first pad 131 located at the outermost side of the substrate 13 and the first pad 131 located at the second outermost side of the substrate 13 is smaller than the distance between the other adjacent first pads 131. Specifically, referring to fig. 2, in this embodiment, the distance between the first pad 131 located at the outermost side of the substrate 13 and the first pad 131 located at the second outermost side of the substrate 13 is d1, the distances between other adjacent first pads 131 are d2, and the distances between other adjacent first pads 131 may be equal. Specifically, the diameter of the first pad 131 is 0.24mm, the diameter of d1 is 0.45mm, and the diameter of d2 is 0.55mm, where d1 or d2 refers to the distance between the centers of the adjacent first pads. During packaging, for example, a ball grid array packaging mode is adopted, packaging is carried out according to the size, through the chip packaging of the design structure, subsequent PCB wiring is more convenient, enough space is guaranteed to be reserved between the first bonding pads 131 needing wiring, accordingly, the width of the wiring is increased, the product cost and the processing difficulty are reduced, the problem that the qualified rate of the PCB wiring is influenced due to the limitation of the space between the bonding pads is avoided, and the stability of the chip packaging can be improved.
In addition, in order to improve the reliability of the product, a metal plating layer 133, such as nicr, hard chrome, chemical nickel, etc., may be disposed on the outer surface of the conductive pillar 132, and by disposing the metal plating layer 133 on the outer surface of the conductive pillar 132, the stability of the electrical connection between the conductive pillar 132 and the corresponding electrical element may be ensured, and the reliability of the product may be improved. It should be noted that, in order to ensure that the entire thickness of the chip package is relatively thin, the thickness of the metal plating layer 133 is controlled to be 20 to 30 micrometers.
According to the chip package 100 of the embodiment, two adjacent chips are connected by a conductive connecting member 17, the conductive connecting member 17 is in contact with the first surface 111 of the substrate 11, that is, a plurality of conductive connecting members 17 are disposed between the chips and the substrate 11, data transmission between the adjacent chips can be realized by the conductive connecting member 17 between the chips, no through-silicon-via (tsv) technology is required for opening holes, the realization cost is low, and the packaging process is simple, in addition, because the first conductive member 14 is disposed between the substrate 11 and the substrate 13, the second conductive member 15 is disposed in the substrate 11, a plurality of third conductive members 16 are disposed between the substrate 15 and the chips, the chips are electrically conducted with the substrate 13 through the first conductive member 14, the second conductive member 15 and the third conductive member 16, the data transmission between the chips and the substrate 13 is realized, and the conductive pillar 132 is disposed on the surface of the substrate 13 facing away from the first pad 131, since the number of the conductive pillars 132 is multiple, and one of the conductive pillars 132 is used for grounding, the conductive pillar 132 can also be used as a heat sink while being conducted, so as to improve the heat dissipation performance of the chip package 100.
Referring to fig. 3, a chip package 100a according to a second embodiment of the invention includes a substrate 11, where the substrate 11 has a first surface 111 and a second surface 112 disposed opposite to each other. The substrate 11 may include a dielectric material, such as an organic material, which may be polypropylene (PP) with glass fiber, epoxy resin (epoxy resin), Polyimide (Polyimide), cyanate ester (cyanate ester), or a combination thereof, and it is understood that the substrate 11 may also adopt Polyimide (PI) or silicon nitride (Si) as well3N4) Or a semiconductor material such as silicon.
For convenience of description, in the present embodiment, the number of chips is described by taking three as an example, specifically, the chip 12a, the chip 12b, and the chip 12c, and the structure of each chip is the same, so in the present embodiment, the structure of only one chip is described by taking as an example. Note that, in the case where two chips or three or more chips are included in the chip package, the structure and principle between adjacent two chips are the same as in the present embodiment. Therefore, the present application is not limited to the case of three chips.
The second surface 112 is provided with a substrate 13, specifically, the substrate 13 is located at the bottom of the base 11, and the substrate 13 may be a dielectric material or a circuit board. The substrate 13 is used for electrically connecting with corresponding electronic components in the end product.
A plurality of first conductive members 14 are disposed between the base 11 and the substrate 13. The first conductive member 14 may be one or more of a conductive bump, a conductive ball, a solder bump, a solder ball.
The substrate 11 has a plurality of second conductive members 15 disposed therein. The second conductive member 15 may also be one or more of a conductive bump, a conductive ball, a solder bump, and a solder ball. The number of the second conductive members 15 and the number of the first conductive members 14 may be the same, and the number of the first conductive members 14 may be more than the number of the second conductive members 15. It should be noted that the first conductive member 14 and the second conductive member 15 should be disposed correspondingly as much as possible, i.e. the first conductive member 14 and the second conductive member 15 can be contacted to achieve electrical conduction.
A plurality of third conductive members 16 are disposed between the substrate 11 and the chip (including the chip 12a, the chip 12b, and the chip 12c), and it is understood that the third conductive members 16 may also be one or more of conductive bumps, conductive balls, solder bumps, and solder balls.
Two adjacent chips are connected through a conductive connecting piece 17, specifically, the conductive connecting piece 17 is arranged between the chip 12a and the chip 12b, and the conductive connecting piece 17 is also arranged between the chip 12b and the chip 12 c. And the conductive connection 17 is in contact with the first surface 111. The conductive connecting member 17 is, for example, a strip, and the conductive connecting member 17 may be made of metal, Polyimide (PI) or silicon nitride (Si) containing a metal conductive wire therein3N4). The conductive connecting member 17 is used for conducting with an electrical element on the chip 12a, the chip 12b or the chip 12c, and since the conductive connecting member 17 is also a conductive material, the electrical conduction between the chip 12a and the chip 12b or between the chip 12b and the chip 12c can be realized, so that the data transmission between adjacent chips is realized. In addition, when the conductive connecting member 17 is made of Polyimide (PI) or silicon nitride (Si) containing a metal conductive wire therein3N4) Metal conductive wireAt least two terminals are exposed from the conductive connecting member 17 for respectively conducting with the electrical components on the adjacent chips.
The surface of the substrate 13 contacting the substrate 11 is provided with a plurality of first pads 131, the number of the first pads 131 may be the same as the number of the first conductive members 14, the first pads 131 and the first conductive members 14 are correspondingly disposed, and the first conductive members 14 at corresponding positions are in contact with the first pads 131 for conduction.
In addition, in this embodiment, in order to improve the electrical conduction performance between the chips, a plurality of second pads 121 may be disposed on one surface of each chip facing the substrate 11, and the conductive connecting member 17 located between two adjacent chips is respectively connected to at least one second pad 121 on the adjacent chip. That is, the conductive connection 17 between the chip 12a and the chip 12b is connected to at least one second pad 121 on the chip 12a and at least one second pad 121 on the chip 12b, respectively, and similarly, the conductive connection 17 between the chip 12b and the chip 12c is connected to at least one second pad 121 on the chip 12b and at least one second pad 121 on the chip 12c, respectively. Through setting up second pad 121, can strengthen the electric connection ability of chip and electrically conductive connecting piece 17 to promote the electric connection ability between the adjacent chip, avoid appearing the unstable condition of data transmission between chip and the chip.
Therefore, the chips 12a and 12b can be electrically connected to the substrate 13 through the second pads 121, the first conductive members 14, the second conductive members 15, and the third conductive members 16.
A plurality of conductive posts 132 are disposed on a surface of the substrate 13 opposite to the first pad 131, the conductive posts 132 penetrate through the substrate 13 to be electrically connected to the first pad 131, and at least one of the conductive posts 132 is used for grounding. The number of the conductive pillars 132 may be the same as the number of the first pads 131, and the sum of the heights of the conductive pillars 132 and the first pads 131 may be equal to the height of the substrate 13, or may be higher than the height of the substrate 13, and may be specifically set according to the actual situation of the circuit board of the product. For better grounding and heat dissipation effects, for each chip, for example, for the chip 12a, the diameter of the conductive pillar 132 for grounding may be larger than the diameter of the other conductive pillars 132. The conductive posts 132 may be implemented as copper posts or aluminum posts.
In addition, in this embodiment, the distance between the first pad 131 located at the outermost side of the substrate 13 and the first pad 131 located at the second outermost side of the substrate 13 is smaller than the distance between the other adjacent first pads 131. Through the reasonable distance between the first pads 131, the first pads 131 needing wiring can be ensured to have enough space, so that the width of wiring can be increased, and the product cost and the processing difficulty can be reduced.
In addition, in order to improve the reliability of the product, a metal plating layer 133, such as nicr, hard chrome, chemical nickel, etc., may be disposed on the outer surface of the conductive pillar 132, and by disposing the metal plating layer 133 on the outer surface of the conductive pillar 132, the stability of the electrical connection between the conductive pillar 132 and the corresponding electrical element may be ensured, and the reliability of the product may be improved. It should be noted that, in order to ensure that the entire thickness of the chip package is relatively thin, the thickness of the metal plating layer 133 is controlled to be 20 to 30 micrometers.
According to the chip package 100a of the embodiment, two adjacent chips are connected through a conductive connecting member 17, the conductive connecting member 17 contacts with the first surface 111 of the substrate 11, that is, a plurality of conductive connecting members 17 are disposed between the chips and the substrate 11, data transmission between the adjacent chips can be realized through the conductive connecting member 17 between the chips, a through silicon via (tsv) technology opening is not needed, the implementation cost is low, the packaging process is simple, and compared with the first embodiment, in the embodiment, by arranging the second bonding pad 121, the electrical connection capability between the adjacent chips can be effectively improved, and the unstable data transmission between the chips is avoided. In addition, because the first conductive member 14 is disposed between the substrate 11 and the substrate 13, the second conductive member 15 is disposed in the substrate 11, the plurality of third conductive members 16 are disposed between the substrate 15 and the chip, and the chip is electrically connected to the substrate 13 through the first conductive member 14, the second conductive member 15 and the third conductive members 16, so as to implement data transmission between the chip and the substrate 13, and the surface of the substrate 13 facing away from the first pad 131 is disposed with the conductive posts 132, because the number of the conductive posts 132 is multiple, one of the conductive posts 132 is used for grounding, the conductive post 132 can also be used as a heat sink while implementing conduction, and finally, the heat dissipation performance of the chip package 100a is improved.
Referring to fig. 4, a chip package 100b according to a third embodiment of the invention includes a substrate 11, where the substrate 11 has a first surface 111 and a second surface 112 disposed opposite to each other. The substrate 11 may include a dielectric material, such as an organic material, which may be polypropylene (PP) with glass fiber, epoxy resin (epoxy resin), Polyimide (Polyimide), cyanate ester (cyanate ester), or a combination thereof, and it is understood that the substrate 11 may also adopt Polyimide (PI) or silicon nitride (Si) as well3N4) Or a semiconductor material such as silicon.
For convenience of description, in the present embodiment, the number of chips is described by taking three as an example, specifically, the chip 12a, the chip 12b, and the chip 12c, and the structure of each chip is the same, so in the present embodiment, the structure of only one chip is described by taking as an example. Note that, in the case where two chips or three or more chips are included in the chip package, the structure and principle between adjacent two chips are the same as in the present embodiment. Therefore, the present application is not limited to the case of three chips.
The second surface 112 is provided with a substrate 13, specifically, the substrate 13 is located at the bottom of the base 11, and the substrate 13 may be a dielectric material or a circuit board. The substrate 13 is used for electrically connecting with corresponding electronic components in the end product.
A plurality of first conductive members 14 are disposed between the base 11 and the substrate 13. The first conductive member 14 may be one or more of a conductive bump, a conductive ball, a solder bump, a solder ball.
The substrate 11 has a plurality of second conductive members 15 disposed therein. The second conductive member 15 may also be one or more of a conductive bump, a conductive ball, a solder bump, and a solder ball. The number of the second conductive members 15 and the number of the first conductive members 14 may be the same, and the number of the first conductive members 14 may be more than the number of the second conductive members 15. It should be noted that the first conductive member 14 and the second conductive member 15 should be disposed correspondingly as much as possible, i.e. the first conductive member 14 and the second conductive member 15 can be contacted to achieve electrical conduction.
A plurality of third conductive members 16 are disposed between the substrate 11 and the chip (including the chip 12a, the chip 12b, and the chip 12c), and it is understood that the third conductive members 16 may also be one or more of conductive bumps, conductive balls, solder bumps, and solder balls.
Two adjacent chips are connected through a conductive connecting piece 17, specifically, the conductive connecting piece 17 is arranged between the chip 12a and the chip 12b, and the conductive connecting piece 17 is also arranged between the chip 12b and the chip 12 c. And the conductive connection 17 is in contact with the first surface 111. The conductive connecting member 17 is, for example, a strip, and the conductive connecting member 17 may be made of metal, Polyimide (PI) or silicon nitride (Si) containing a metal conductive wire therein3N4). The conductive connecting member 17 is used for conducting with an electrical element on the chip 12a, the chip 12b or the chip 12c, and since the conductive connecting member 17 is also a conductive material, the electrical conduction between the chip 12a and the chip 12b or between the chip 12b and the chip 12c can be realized, so that the data transmission between adjacent chips is realized. In addition, when the conductive connecting member 17 is made of Polyimide (PI) or silicon nitride (Si) containing a metal conductive wire therein3N4) At least two end points of the metal conductive wires are exposed from the conductive connecting member 17 for conducting with the electrical components on the adjacent chips.
The surface of the substrate 13 contacting the substrate 11 is provided with a plurality of first pads 131, the number of the first pads 131 may be the same as the number of the first conductive members 14, the first pads 131 and the first conductive members 14 are correspondingly disposed, and the first conductive members 14 at corresponding positions are in contact with the first pads 131 for conduction.
A plurality of second bonding pads 121 are arranged on one surface of each chip facing the substrate 11, and the conductive connecting member 17 located between two adjacent chips is respectively connected with at least one second bonding pad 121 on the adjacent chip. That is, the conductive connecting member 17 between the chip 12a and the chip 12b is connected to at least one second pad 121 on the chip 12a and connected to at least one second pad 121 on the chip 12b, and similarly, the conductive connecting member 17 between the chip 12b and the chip 12c is connected to at least one second pad 121 on the chip 12b and connected to at least one second pad 121 on the chip 12c, and by providing the second pad 121, the electrical connection capability between the chip and the conductive connecting member 17 can be enhanced, thereby improving the electrical connection capability between adjacent chips, and avoiding the unstable data transmission between the chips.
Therefore, the chips 12a, 12b, and 12c can be electrically connected to the substrate 13 via the second pads 121, the first conductive members 14, the second conductive members 15, and the third conductive members 16.
In addition, in this embodiment, several reinforcing members 18 are further disposed on the first surface 111, the reinforcing members 18 are located between adjacent chips, and the reinforcing members 17 extend beyond the edge of the substrate 11. I.e. between chip 12a and chip 12b, between chip 12b and chip 12c, and the edge of substrate 11 are provided with stiffeners 18.
By adding the stiffener 18 to the first surface 111 of the substrate 11, the stiffener 18 is located between adjacent chips, and the stiffener 18 extends beyond the edge of the substrate 11, warpage of the substrate 11 can be effectively avoided, and the structural strength and stability of the chip package 100b are improved.
Further, the thermal conductivity of the reinforcing member 18 is higher than that of the substrate 11, and the reinforcing member 18 may be one or a combination of aluminum, copper and gold. Since the thermal conductivity of the stiffener 18 is higher than that of the substrate 11, the heat generated during the operation of the chip can be effectively absorbed, thereby improving the heat dissipation effect of the chip package 100 b.
A plurality of conductive posts 132 are disposed on a surface of the substrate 13 opposite to the first pad 131, the conductive posts 132 penetrate through the substrate 13 to be electrically connected to the first pad 131, and at least one of the conductive posts 132 is used for grounding. The number of the conductive pillars 132 may be the same as the number of the first pads 131, and the sum of the heights of the conductive pillars 132 and the first pads 131 may be equal to the height of the substrate 13, or may be higher than the height of the substrate 13, and may be specifically set according to the actual situation of the circuit board of the product. For better grounding and heat dissipation effects, for each chip, for example, for the chip 12a, the diameter of the conductive pillar 132 for grounding may be larger than the diameter of the other conductive pillars 132. The conductive posts 132 may be implemented as copper posts or aluminum posts.
In addition, in this embodiment, the distance between the first pad 131 located at the outermost side of the substrate 13 and the first pad 131 located at the second outermost side of the substrate 13 is smaller than the distance between the other adjacent first pads 131. Through the reasonable distance between the first pads 131, the first pads 131 needing wiring can be ensured to have enough space, so that the width of wiring can be increased, and the product cost and the processing difficulty can be reduced.
In addition, in order to improve the reliability of the product, a metal plating layer 133, such as nicr, hard chrome, chemical nickel, etc., may be disposed on the outer surface of the conductive pillar 132, and by disposing the metal plating layer 133 on the outer surface of the conductive pillar 132, the stability of the electrical connection between the conductive pillar 132 and the corresponding electrical element may be ensured, and the reliability of the product may be improved. It should be noted that, in order to ensure that the entire thickness of the chip package is relatively thin, the thickness of the metal plating layer 133 is controlled to be 20 to 30 micrometers.
According to the chip package 100b of the embodiment, two adjacent chips are connected by a conductive connecting member 17, the conductive connecting member 17 is in contact with the first surface 111 of the substrate 11, that is, a plurality of conductive connecting members 17 are disposed between the chips and the substrate 11, data transmission between the adjacent chips can be realized by the conductive connecting member 17 between the chips, no through-silicon-via (tsv) opening is needed, the realization cost is low, and the packaging process is simple, in addition, because the first conductive member 14 is disposed between the substrate 11 and the substrate 13, the second conductive member 15 is disposed in the substrate 11, a plurality of third conductive members 16 are disposed between the substrate 15 and the chips, the chips are electrically conducted with the substrate 13 through the first conductive member 14, the second conductive member 15 and the third conductive member 16, the data transmission between the chips and the substrate 13 is realized, and the conductive pillar 132 is disposed on the surface of the substrate 13 facing away from the first pad 131, since the number of the conductive pillars 132 is multiple, and one of the conductive pillars 132 is used for grounding, the conductive pillar 132 can also be used as a heat sink while being conducted, so as to improve the heat dissipation performance of the chip package 100 b. In addition, compared with the first embodiment and the second embodiment, the present embodiment can effectively avoid the warpage of the substrate 11 by providing the stiffener 18, and improve the structural strength and stability of the chip package 100 b. The thermal conductivity of the stiffener 18 is higher than that of the substrate 11, so that heat generated during the operation of the chip can be effectively absorbed, and the heat dissipation effect of the chip package 100b can be further improved.
Referring to fig. 5, a chip package 100c according to a fourth embodiment of the invention includes a substrate 11, where the substrate 11 has a first surface 111 and a second surface 112 disposed opposite to each other. The substrate 11 may include a dielectric material, such as an organic material, which may be polypropylene (PP) with glass fiber, epoxy resin (epoxy resin), Polyimide (Polyimide), cyanate ester (cyanate ester), or a combination thereof, and it is understood that the substrate 11 may also adopt Polyimide (PI) or silicon nitride (Si) as well3N4) Or a semiconductor material such as silicon.
For convenience of description, in the present embodiment, the number of chips is described by taking three as an example, specifically, the chip 12a, the chip 12b, and the chip 12c, and the structure of each chip is the same, so in the present embodiment, the structure of only one chip is described by taking as an example. Note that, in the case where two chips or three or more chips are included in the chip package, the structure and principle between adjacent two chips are the same as in the present embodiment. Therefore, the present application is not limited to the case of three chips.
The second surface 112 is provided with a substrate 13, specifically, the substrate 13 is located at the bottom of the base 11, and the substrate 13 may be a dielectric material or a circuit board. The substrate 13 is used for electrically connecting with corresponding electronic components in the end product.
A plurality of first conductive members 14 are disposed between the base 11 and the substrate 13. The first conductive member 14 may be one or more of a conductive bump, a conductive ball, a solder bump, a solder ball.
The substrate 11 has a plurality of second conductive members 15 disposed therein. The second conductive member 15 may also be one or more of a conductive bump, a conductive ball, a solder bump, and a solder ball. The number of the second conductive members 15 and the number of the first conductive members 14 may be the same, and the number of the first conductive members 14 may be more than the number of the second conductive members 15. It should be noted that the first conductive member 14 and the second conductive member 15 should be disposed correspondingly as much as possible, i.e. the first conductive member 14 and the second conductive member 15 can be contacted to achieve electrical conduction.
A plurality of third conductive members 16 are disposed between the substrate 11 and the chip (including the chip 12a, the chip 12b, and the chip 12c), and it is understood that the third conductive members 16 may also be one or more of conductive bumps, conductive balls, solder bumps, and solder balls.
Two adjacent chips are connected through a conductive connecting piece 17, specifically, the conductive connecting piece 17 is arranged between the chip 12a and the chip 12b, and the conductive connecting piece 17 is also arranged between the chip 12b and the chip 12 c. And the conductive connection 17 is in contact with the first surface 111. The conductive connecting member 17 is, for example, a strip, and the conductive connecting member 17 may be made of metal, Polyimide (PI) or silicon nitride (Si) containing a metal conductive wire therein3N4). The conductive connecting member 17 is used for conducting with an electrical element on the chip 12a, the chip 12b or the chip 12c, and since the conductive connecting member 17 is also a conductive material, the electrical conduction between the chip 12a and the chip 12b or between the chip 12b and the chip 12c can be realized, so that the data transmission between adjacent chips is realized. In addition, when the conductive connecting member 17 is made of Polyimide (PI) or silicon nitride (Si) containing a metal conductive wire therein3N4) While the metal conductor wire is in the conductive connecting piece 17At least two terminals are exposed for respectively conducting with the electrical components on the adjacent chips.
The surface of the substrate 13 contacting the substrate 11 is provided with a plurality of first pads 131, the number of the first pads 131 may be the same as the number of the first conductive members 14, the first pads 131 and the first conductive members 14 are correspondingly disposed, and the first conductive members 14 at corresponding positions are in contact with the first pads 131 for conduction.
A plurality of second bonding pads 121 are arranged on one surface of each chip facing the substrate 11, and the conductive connecting member 17 located between two adjacent chips is respectively connected with at least one second bonding pad 121 on the adjacent chip. That is, the conductive connecting member 17 between the chip 12a and the chip 12b is connected to at least one second pad 121 on the chip 12a and connected to at least one second pad 121 on the chip 12b, and similarly, the conductive connecting member 17 between the chip 12b and the chip 12c is connected to at least one second pad 121 on the chip 12b and connected to at least one second pad 121 on the chip 12c, and by providing the second pad 121, the electrical connection capability between the chip and the conductive connecting member 17 can be enhanced, thereby improving the electrical connection capability between adjacent chips, and avoiding the unstable data transmission between the chips.
Therefore, the chips 12a, 12b, and 12c can be electrically connected to the substrate 13 via the second pads 121, the first conductive members 14, the second conductive members 15, and the third conductive members 16.
In addition, in this embodiment, several reinforcing members 18 are further disposed on the first surface 111, the reinforcing members 18 are located between adjacent chips, and the reinforcing members 17 extend beyond the edge of the substrate 11. I.e. between chip 12a and chip 12b, between chip 12b and chip 12c, and the edge of substrate 11 are provided with stiffeners 18.
In this embodiment, the stiffener 18 also covers a surface of all the chips facing away from the substrate 11, that is, the stiffener 18 covers a surface of the chips 12a, 12b, and 12c facing away from the substrate 11, and since the stiffener 18 covers a surface of all the chips facing away from the substrate 11, all the chips can be protected from being damaged or contaminated.
By adding the stiffener 18 to the first surface 111 of the substrate 11, the stiffener 18 is located between adjacent chips, and the stiffener 18 extends beyond the edge of the substrate 11, warpage of the substrate 11 can be effectively avoided, and the structural strength and stability of the chip package 100c are improved.
Further, the thermal conductivity of the reinforcing member 18 is higher than that of the substrate 11, and the reinforcing member 18 may be one or a combination of aluminum, copper and gold. Since the thermal conductivity of the stiffener 18 is higher than that of the substrate 11, the heat generated during the operation of the chip can be effectively absorbed, thereby improving the heat dissipation effect of the chip package 100 c.
In addition, in the present embodiment, an adhesive layer 19 is disposed between the stiffener 18 and the substrate 11. The adhesive layer 19 is made of, for example, a polymer adhesive, and the adhesive layer 19 is additionally arranged between the stiffener 18 and the substrate 11, so that the stiffener 18 and the substrate 11 are prevented from falling off after the product is used for a long time, and the structural strength and stability of the chip package 100c are improved.
It should be noted that the adhesive layer 19 is only disposed between the stiffener 18 and the substrate 11, and the adhesive layers 19 are not disposed between the stiffener 18 and the chip 12a, between the stiffener 18 and the chip 12b, or between the stiffener 18 and the chip 12c, so as to prevent the adhesive layer 19 from affecting the working effect of the chip.
A plurality of conductive posts 132 are disposed on a surface of the substrate 13 opposite to the first pad 131, the conductive posts 132 penetrate through the substrate 13 to be electrically connected to the first pad 131, and at least one of the conductive posts 132 is used for grounding. The number of the conductive pillars 132 may be the same as the number of the first pads 131, and the sum of the heights of the conductive pillars 132 and the first pads 131 may be equal to the height of the substrate 13, or may be higher than the height of the substrate 13, and may be specifically set according to the actual situation of the circuit board of the product. For better grounding and heat dissipation effects, for each chip, for example, for the chip 12a, the diameter of the conductive pillar 132 for grounding may be larger than the diameter of the other conductive pillars 132. The conductive posts 132 may be implemented as copper posts or aluminum posts.
In addition, in this embodiment, the distance between the first pad 131 located at the outermost side of the substrate 13 and the first pad 131 located at the second outermost side of the substrate 13 is smaller than the distance between the other adjacent first pads 131. Through the reasonable distance between the first pads 131, the first pads 131 needing wiring can be ensured to have enough space, so that the width of wiring can be increased, and the product cost and the processing difficulty can be reduced.
In addition, in order to improve the reliability of the product, a metal plating layer 133, such as nicr, hard chrome, chemical nickel, etc., may be disposed on the outer surface of the conductive pillar 132, and by disposing the metal plating layer 133 on the outer surface of the conductive pillar 132, the stability of the electrical connection between the conductive pillar 132 and the corresponding electrical element may be ensured, and the reliability of the product may be improved. It should be noted that, in order to ensure that the entire thickness of the chip package is relatively thin, the thickness of the metal plating layer 133 is controlled to be 20 to 30 micrometers.
According to the chip package 100c of the embodiment, two adjacent chips are connected by a conductive connecting member 17, the conductive connecting member 17 is in contact with the first surface 111 of the substrate 11, that is, a plurality of conductive connecting members 17 are disposed between the chips and the substrate 11, data transmission between the adjacent chips can be realized by the conductive connecting member 17 between the chips, no through-silicon-via (tsv) opening is needed, the realization cost is low, and the packaging process is simple, in addition, because the first conductive member 14 is disposed between the substrate 11 and the substrate 13, the second conductive member 15 is disposed in the substrate 11, a plurality of third conductive members 16 are disposed between the substrate 15 and the chips, the chips are electrically conducted with the substrate 13 through the first conductive member 14, the second conductive member 15 and the third conductive member 16, the data transmission between the chips and the substrate 13 is realized, and the conductive pillar 132 is disposed on the surface of the substrate 13 facing away from the first pad 131, since the number of the conductive pillars 132 is multiple, and one of the conductive pillars 132 is used for grounding, the conductive pillar 132 can also be used as a heat sink while being conducted, so as to improve the heat dissipation performance of the chip package 100 c. In addition, by providing the stiffener 18, warpage of the substrate 11 can be effectively avoided, and the structural strength and stability of the chip package 100c are improved. The thermal conductivity of the stiffener 18 is higher than that of the substrate 11, so that heat generated during the operation of the chip can be effectively absorbed, and the heat dissipation effect of the chip package 100c can be further improved. In addition, compared with the third embodiment, in this embodiment, the stiffener 18 covers a surface of all the chips facing away from the substrate 11, so as to protect all the chips from being damaged or contaminated, and the adhesive layer 19 is disposed between the stiffener 18 and the substrate 11, so as to ensure that the stiffener 18 and the substrate 11 do not fall off after long-term use of the product, and improve the structural strength and stability of the chip package 100 c.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (8)

1. A chip package comprises a substrate, and is characterized in that the substrate is provided with a first surface and a second surface which are oppositely arranged, a plurality of chips are arranged on the first surface, a substrate is arranged on the second surface, a plurality of first conductive components which are arranged at intervals are arranged between the substrate and the substrate, a plurality of second conductive components are arranged in the substrate, a plurality of third conductive components are arranged between the substrate and the chips, two adjacent chips are connected through a conductive connecting piece, the conductive connecting piece is contacted with the first surface, one surface of the substrate adjacent to the substrate is provided with a plurality of first bonding pads, the chips are electrically conducted with the substrate through the first conductive components, the second conductive components and the third conductive components, one surface of the substrate opposite to the first bonding pads is provided with a plurality of conductive columns, the conductive posts penetrate through the substrate to be conducted with the first bonding pads, at least one conductive post is used for grounding, and the diameter of the conductive post used for grounding is larger than that of the other conductive posts;
each chip is towards one side of the substrate and is provided with a plurality of second bonding pads, and the conductive connecting piece between two adjacent chips is respectively connected with at least one second bonding pad on the two adjacent chips.
2. The chip package according to claim 1, wherein the conductive connecting member is made of a metal material, or the conductive connecting member is polyimide or silicon nitride containing a metal conductive wire therein.
3. The chip package according to claim 1, wherein the first surface further comprises a plurality of stiffeners, the stiffeners are located between adjacent chips, and the stiffeners extend beyond the edge of the substrate.
4. The chip package according to claim 3, wherein an adhesive layer is disposed between the stiffener and the substrate.
5. The chip package according to claim 3, wherein the stiffener covers all of the chips on a side facing away from the substrate.
6. The chip package according to any one of claims 3 to 5, wherein the thermal conductivity of the stiffener is higher than the thermal conductivity of the substrate.
7. The chip package according to claim 6, wherein the stiffener is one or a combination of aluminum, copper and gold.
8. The chip package according to claim 1, wherein the outer surface of the conductive pillar is provided with a metal plating layer, and the thickness of the metal plating layer is 20-30 μm.
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