CN107910315A - Chip package - Google Patents
Chip package Download PDFInfo
- Publication number
- CN107910315A CN107910315A CN201711105653.6A CN201711105653A CN107910315A CN 107910315 A CN107910315 A CN 107910315A CN 201711105653 A CN201711105653 A CN 201711105653A CN 107910315 A CN107910315 A CN 107910315A
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- China
- Prior art keywords
- substrate
- chip
- conductive
- pad
- chip package
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
A kind of chip package,Including substrate,Substrate has the first surface and second surface being oppositely arranged,First surface is equipped with multiple chips,Second surface is equipped with substrate,Multiple spaced first conductive members are equipped between substrate and substrate,Several second conductive members are equipped with substrate,Several the 3rd conductive members are equipped between substrate and chip,Connected between two adjacent chips by a conducting connecting part,Conducting connecting part is contacted with first surface,The one side that substrate is contacted with substrate is equipped with several first pads,Chip passes through the first conductive member,Second conductive member and the 3rd conductive member are turned on electrical property of substrate,Substrate is equipped with several conductive columns backwards to the one side of the first pad,Conductive column runs through substrate to be turned on the first pad,At least one conductive column is used to be grounded,Diameter for the conductive column of ground connection is more than the diameter of other conductive columns.Of high cost, the weak heat-dissipating when present invention can solve the problems, such as to realize data transfer between chip in the prior art.
Description
Technical field
The present invention relates to chip technology field, more particularly to a kind of chip package.
Background technology
With the development of science and technology smart electronics product has gradually come into the life of people, smart electronics product chips are
Determine the deciding factor of properties of product.Chip is after the completion of production, it is necessary to carry out chip package.
Develop now with electronic product to portable, miniaturization, chip package size also progressively minimizes, and mounts
Component encapsulation spacing develops to more thin space, generally comprises multiple chips in chip package, needs to carry out between chip and chip
Data transfer.
In the prior art, realize that the data transfer between chip package chips and chip needs to exist using silicon hole technology
Perforate in pinboard, makes through hole run through the upper and lower surface of pinboard, and carries out metal line in through-holes, and chip passes through
Metal line and substrate connection in through hole, this implementation encapsulation process is complicated, and cost is higher.In addition, at chip
Reason data continue to increase, and there is also the problem of weak heat-dissipating for the chip package that this technique is produced.
The content of the invention
For this reason, it is an object of the invention to propose a kind of chip package, solve chip package of the prior art and realizing
The problem of of high cost during data transfer between chip and chip, weak heat-dissipating.
A kind of chip package, including substrate, the substrate have the first surface and second surface that are oppositely arranged, and described the
One surface is equipped with multiple chips, and the second surface is equipped with substrate, between the substrate and the substrate be equipped with it is multiple between
Every being equipped with several second conductive members in the first conductive member of setting, the substrate, between the substrate and the chip
Equipped with several the 3rd conductive members, connected between adjacent two chips by a conducting connecting part, the conduction is even
Fitting is contacted with the first surface, and the one side that the substrate is contacted with the substrate is equipped with several first pads, the core
Piece is turned on by first conductive member, second conductive member and the 3rd conductive member with the electrical property of substrate,
The substrate is equipped with several conductive columns backwards to the one side of first pad, the conductive column through the substrate with it is described
First pad turns on, and at least one conductive column is used to be grounded, and the diameter for the conductive column of ground connection is more than other conductions
The diameter of column..
The chip package provided according to the present invention, passes through a conducting connecting part between adjacent two chips and connects, conductive
Connector is contacted with the first surface of substrate, i.e., is equipped with multiple conducting connecting parts between chip and substrate, between adjacent chip
Data transfer can be realized by conducting connecting part between chip, without using silicon hole technology perforate, cost of implementation again
Low, encapsulation process is simple, further, since setting the first conductive member between substrate and substrate, the second conductive structure is equipped with substrate
Part, is equipped with several the 3rd conductive members between substrate and chip, and chip is led by first conductive member, described second
Electric components and the 3rd conductive member are turned on electrical property of substrate, realize the data transfer of chip and substrate, and substrate is backwards to the
The one side of one pad is equipped with conductive column, and since the quantity of conductive column is multiple, one of conductive column is used to be grounded, therefore conductive
Column can also be used as radiator while conducting is realized, the final heat dissipation performance for lifting chip package.
In addition, above-mentioned chip package according to the present invention, can also have technical characteristic additional as follows：
Further, the one side of each chip towards the substrate is equipped with several the second pads, positioned at adjacent
Two chips between the conducting connecting part respectively with least one described on two adjacent chips
Two pads connect.The conducting connecting part can be metal material or the internal polyimides containing metal conductive wire or nitridation
Silicon.
Wherein, the electric connection energy of chip and conducting connecting part can be strengthened by increasing by the second pad on each chip
Power, so as to lift the electric connection ability between adjacent chip, avoids the occurrence of between chip and chip and data transfer occurs not
Stable situation.
Further, some reinforcers are additionally provided with the first surface, the reinforcer is located at the adjacent chip
Between, and the reinforcer extends beyond the edge of the substrate.
Wherein, by increasing reinforcer in the first surface of substrate, and reinforcer adds at the same time between adjacent chip
Strong part extends beyond the edge of substrate, can effectively avoid basement warping, lift the structural strength and stability of chip package.
Further, mucigel is equipped between the reinforcer and the substrate.
Wherein, mucigel is added between reinforcer and substrate, ensureing product, reinforcer will not with substrate after long-term use
Come off, further lift the structural strength and stability of chip package.
Further, the reinforcer covers one side of all chips backwards to the substrate.
Wherein, carry on the back based one side since reinforcer covers all chip, can protect chip from it is impaired or by
Pollution.
Further, the thermal conductivity factor of the reinforcer is higher than the thermal conductivity factor of the substrate.The reinforcer can be
One or several kinds of combinations in aluminium, copper, gold.
Wherein, since the thermal conductivity factor of reinforcer is higher than the thermal conductivity factor of substrate, produced when can effectively absorb chip operation
Raw thermal energy, so as to further lift the heat dissipation effect of chip package.
Further, first pad positioned at the substrate outermost and described the positioned at the substrate time exterior measuring
The distance between one pad is less than the distance between other adjacent described first pads.
Wherein, by the distance between first pad of above-mentioned rational arrangement, can ensure to need the first pad connected up
Between there is enough spacing, so as to increase the width of wiring, product cost and difficulty of processing can be reduced.
Further, the outer surface of the conductive column is equipped with the coat of metal, and the thickness of the coat of metal is micro- for 20~30
Rice.
Wherein, by setting the coat of metal in the outer surface of conductive column, conductive column and corresponding electrical equipment can be ensured
Between electric connection stability, lift the reliability of product.
The additional aspect and advantage of the present invention will be set forth in part in the description, and will partly become from the following description
Obtain substantially, or recognized by the practice of the present invention.
Brief description of the drawings
The above-mentioned and/or additional aspect and advantage of the present invention will become in the description from combination accompanying drawings below to embodiment
Substantially and it is readily appreciated that, wherein：
Fig. 1 is the cross section structure schematic diagram of chip package according to a first embodiment of the present invention；
Fig. 2 is distribution schematic diagram of first pad on substrate in Fig. 1；
Fig. 3 is the cross section structure schematic diagram of chip package according to a second embodiment of the present invention；
Fig. 4 is the cross section structure schematic diagram of chip package according to a third embodiment of the present invention；
Fig. 5 is the cross section structure schematic diagram of chip package according to a fourth embodiment of the present invention.
Embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.Some embodiments of the present invention are given in attached drawing.But the present invention can be with perhaps
More different form is realized, however it is not limited to embodiment described herein.On the contrary, the purpose for providing these embodiments is to make
To the disclosure more thorough and comprehensive.
It should be noted that when element is referred to as " being fixedly arranged on " another element, it can be directly on another element
Or there may also be element placed in the middle.When an element is considered as " connection " another element, it can be directly connected to
To another element or it may be simultaneously present centering elements.Term as used herein " vertical ", " horizontal ", " left side ",
" right side ", " on ", " under " and similar statement is for illustrative purposes only, rather than instruction or the device or member that imply meaning
Part must have specific orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
In the present invention, unless otherwise clearly defined and limited, term " installation ", " connected ", " connection ", " fixation " etc.
Term should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；It can be machine
Tool is connected or is electrically connected；It can be directly connected, can also be indirectly connected by intermediary, can be two members
Connection inside part.For the ordinary skill in the art, above-mentioned term can be understood in this hair as the case may be
Concrete meaning in bright.Term as used herein " and/or " include the arbitrary of one or more relevant Listed Items and
All combinations.
Referring to Fig. 1, the chip package 100 that first embodiment of the invention proposes, including substrate 11, the substrate 11 have
The first surface 111 and second surface 112 being oppositely arranged.Substrate 11 may include dielectric material, such as organic material, organic material
Can be the polypropylene (polypropylene, PP) with glass fibre, epoxy resin (epoxy resin), polyimides
(polyimide), cyanate (cyanateester) or foregoing combination, it is possible to understand that, substrate 11 can also use polyamides
Imines (Polyimide, PI) or silicon nitride (Si3N4) or semi-conducting material, semi-conducting material such as silicon.
The first surface 111 is equipped with multiple chips, and for convenience of description, in the present embodiment, the quantity of chip is with three
Illustrated exemplified by a, specially chip 12a, chip 12b, chip 12c, the structure all same of each chip, therefore, this implementation
In example, only illustrated by taking the structure of one of chip as an example.It is noted that include two chips for chip package
Or the situation of more than three chips, the structure and principle between two neighboring chip are identical with the present embodiment.Therefore, the application
It is not limited to the situation of three chips.
The second surface 112 is equipped with substrate 13, specifically, substrate 13 is located at the bottom of substrate 11, substrate 13 can be with
It is dielectric material or circuit board.Substrate 13 is used for realization to be electrically connected with the corresponding electronic component in end product.
Multiple spaced first conductive members 14 are equipped between the substrate 11 and the substrate 13.First conductive structure
Part 14 can be the one or more in conductive bump, conducting sphere, welding block, soldered ball.
Several second conductive members 15 are equipped with the substrate 11.Second conductive member 15 can also be conductive stud
One or more in block, conducting sphere, welding block, soldered ball.The number of second conductive member 15 and first conductive member 14
Amount can be identical, the quantity of first conductive member 14 can also unnecessary second conductive member 15 quantity.It may be noted that
It is that the first conductive member 14 and the second conductive member 15 should be correspondingly arranged as far as possible, that is, ensures the first conductive member 14 and
Two conductive members 15 can contact, and be electrically conducted with realizing.
Several the 3rd conductive structures are equipped between the substrate 11 and chip (including chip 12a, chip 12b, chip 12c)
Part 16, it is possible to understand that, the 3rd conductive member 16 can also be one kind or more in conductive bump, conducting sphere, welding block, soldered ball
Kind.
Connected between two adjacent chips by a conducting connecting part 17, specifically, between chip 12a and chip 12b
Equipped with conducting connecting part 17, conducting connecting part 17 also is provided between chip 12b and chip 12c.And the conducting connecting part 17 with
The first surface 111 contacts.Conducting connecting part 17 is, for example, strip, and conducting connecting part 17 can be that metal material or inside contain
There are the polyimides (Polyimide, PI) or silicon nitride (Si of metal conductive wire3N4).Conducting connecting part 17 is used for and chip 12a
Or the electrical components conducting on chip 12b or chip 12c, can since conducting connecting part 17 itself is also conductive material
Electrically conducting for chip 12a and chip 12b or chip 12b and chip 12c is realized, so as to fulfill the data between adjacent chip
Transmission.It should be noted that when conducting connecting part 17 using it is internal containing metal conductive wire polyimides (Polyimide,
) or silicon nitride (Si PI3N4) when, metal conductive wire at least leaks out two endpoints in conducting connecting part 17, for respectively with it is adjacent
Chip on electrical components conducting.
The one side that the substrate 13 is contacted with the substrate 11 is equipped with several first pads 131, the number of the first pad 131
Amount can be identical with the quantity of the first conductive member 14, and the first pad 131 and the 14 corresponding setting of the first conductive member, accordingly
The first conductive member 14 and the first pad 131 on position are in contact conducting.
Therefore, final chip 12a, chip 12b, chip 12c can pass through the first conductive member 14, the second conductive member 15
And the 3rd conductive member 16 electrically conducts with substrate 13.
The substrate 13 is equipped with several conductive columns 132, the conductive column 132 backwards to the one side of first pad 131
Through the substrate 13 to be turned on first pad 131, and at least one conductive column 132 is used to be grounded.Wherein, lead
The quantity of electric column 132 can be identical with the quantity of the first pad 131, and the sum of height of 132 and first pad 131 of conductive column can be with
Equal to the height of substrate 13, the height of substrate 13 can also be higher than, specifically can according to the actual conditions of the circuit board of product into
Row is set.Wherein, it is corresponding for each chip, such as chip 12a in order to preferably be grounded and heat dissipation effect
Conductive column 132 in, for ground connection conductive column 132 diameter can be more than other conductive columns 132 diameter.Conductive column 132
Copper post or aluminium column can be used to realize.
In addition, in the present embodiment, positioned at 13 outermost of substrate the first pad 131 with it is outer positioned at the substrate 13 times
The distance between first pad 131 surveyed is less than the distance between other adjacent described first pads 131.It can specifically refer to
Fig. 2, in the present embodiment, positioned at 13 outermost of substrate the first pad 131 with positioned at the first of 13 exterior measurings of substrate
The distance between pad 131 is d1, and the distance between other first adjacent pads 131 are d2, and other the first adjacent welderings
The distance between disk 131 can be equal.Specifically, a diameter of 0.24mm of the first pad 131, d1 0.45mm, d2 are
0.55mm, it should be pointed out that d1 or d2 is all referring to the distance between adjacent center of circle of the first pad here.During encapsulation,
For example with the form of BGA Package, it is packaged according to above-mentioned size, can by the chip package of the design structure
It is more convenient when connecting up follow-up pcb board, there is enough spacing between the first pad 131 for ensureing to need to connect up, so as to increase
The width of wiring, reduces product cost and difficulty of processing, will not produce due to the limitation of spacing between pad and influence pcb board cloth
The problem of qualification rate of line, therefore can also lift the stability of the chip package.
In addition, in order to lift the reliability of product, the coat of metal 133 can be equipped with the outer surface of conductive column 132, such as copper
Nickel chromium triangle, hard chrome, chemical nickel etc., by the outer surface of conductive column 132 set the coat of metal 133, can ensure conductive column 132 with
Electric connection stability between corresponding electrical equipment, lifts the reliability of product.It should be noted that in order to ensure chip
Overall thinner thickness is encapsulated, the thickness control of the coat of metal 133 is at 20~30 microns.
According to the chip package 100 of the present embodiment, connected, led by a conducting connecting part 17 between adjacent two chips
Electrical connector 17 is contacted with the first surface 111 of substrate 11, i.e., multiple conducting connecting parts 17, phase are equipped between chip and substrate 11
Data transfer between adjacent chip can be realized by the conducting connecting part 17 between chip, without using silicon hole technology again
Perforate, cost of implementation is low, and encapsulation process is simple, further, since setting the first conductive member 14, base between substrate 11 and substrate 13
The second conductive member 15 is equipped with bottom 11, several the 3rd conductive members 16 are equipped between substrate 15 and chip, and chip passes through
First conductive member 14, second conductive member 15 and the 3rd conductive member 16 electrically conduct with substrate 13, real
The data transfer of existing chip and substrate 13, and substrate 13 is equipped with conductive column 132 backwards to the one side of the first pad 131, due to conduction
To be multiple, one of conductive column 132 is used to be grounded the quantity of column 132, thus conductive column 132 realize turn on while,
Radiator can be used as, the final heat dissipation performance for lifting chip package 100.
Referring to Fig. 3, the chip package 100a that second embodiment of the invention proposes, including substrate 11, the substrate 11 have
There are the first surface 111 and second surface 112 being oppositely arranged.Substrate 11 may include dielectric material, such as organic material, You Jicai
Material can be the polypropylene (polypropylene, PP) with glass fibre, epoxy resin (epoxy resin), polyimides
(polyimide), cyanate (cyanateester) or foregoing combination, it is possible to understand that, substrate 11 can also use polyamides
Imines (Polyimide, PI) or silicon nitride (Si3N4) or semi-conducting material, semi-conducting material such as silicon.
The first surface 111 is equipped with multiple chips, and for convenience of description, in the present embodiment, the quantity of chip is with three
Illustrated exemplified by a, specially chip 12a, chip 12b, chip 12c, the structure all same of each chip, therefore, this implementation
In example, only illustrated by taking the structure of one of chip as an example.It is noted that include two chips for chip package
Or the situation of more than three chips, the structure and principle between two neighboring chip are identical with the present embodiment.Therefore, the application
It is not limited to the situation of three chips.
The second surface 112 is equipped with substrate 13, specifically, substrate 13 is located at the bottom of substrate 11, substrate 13 can be with
It is dielectric material or circuit board.Substrate 13 is used for realization to be electrically connected with the corresponding electronic component in end product.
Multiple spaced first conductive members 14 are equipped between the substrate 11 and the substrate 13.First conductive structure
Part 14 can be the one or more in conductive bump, conducting sphere, welding block, soldered ball.
Several second conductive members 15 are equipped with the substrate 11.Second conductive member 15 can also be conductive stud
One or more in block, conducting sphere, welding block, soldered ball.The number of second conductive member 15 and first conductive member 14
Amount can be identical, the quantity of first conductive member 14 can also unnecessary second conductive member 15 quantity.It may be noted that
It is that the first conductive member 14 and the second conductive member 15 should be correspondingly arranged as far as possible, that is, ensures the first conductive member 14 and
Two conductive members 15 can contact, and be electrically conducted with realizing.
Several the 3rd conductive structures are equipped between the substrate 11 and chip (including chip 12a, chip 12b, chip 12c)
Part 16, it is possible to understand that, the 3rd conductive member 16 can also be one kind or more in conductive bump, conducting sphere, welding block, soldered ball
Kind.
Connected between two adjacent chips by a conducting connecting part 17, specifically, between chip 12a and chip 12b
Equipped with conducting connecting part 17, conducting connecting part 17 also is provided between chip 12b and chip 12c.And the conducting connecting part 17 with
The first surface 111 contacts.Conducting connecting part 17 is, for example, strip, and conducting connecting part 17 can be that metal material or inside contain
There are the polyimides (Polyimide, PI) or silicon nitride (Si of metal conductive wire3N4).Conducting connecting part 17 is used for and chip 12a
Or the electrical components conducting on chip 12b or chip 12c, can since conducting connecting part 17 itself is also conductive material
Electrically conducting for chip 12a and chip 12b or chip 12b and chip 12c is realized, so as to fulfill the data between adjacent chip
Transmission.It should be noted that when conducting connecting part 17 using it is internal containing metal conductive wire polyimides (Polyimide,
) or silicon nitride (Si PI3N4) when, metal conductive wire at least leaks out two endpoints in conducting connecting part 17, for respectively with it is adjacent
Chip on electrical components conducting.
The one side that the substrate 13 is contacted with the substrate 11 is equipped with several first pads 131, the number of the first pad 131
Amount can be identical with the quantity of the first conductive member 14, and the first pad 131 and the 14 corresponding setting of the first conductive member, accordingly
The first conductive member 14 and the first pad 131 on position are in contact conducting.
, can be in each chip towards substrate in order to lift the performance that electrically conducts between chip in addition, in the present embodiment
11 one side is all provided with setting several the second pads 121, the conducting connecting part 17 between two adjacent chips respectively with
At least one second pad 121 on the adjacent chip connects.That is, the conductions of chip 12a and chip 12b between the two are even
Fitting 17 be connected respectively with least one second pad 121 on chip 12a and with least one second on chip 12b
Pad 121 connects, similarly, chip 12b and the conducting connecting parts 17 of chip 12c between the two respectively with chip 12b at least
One the second pad 121 is connected and is connected with least one second pad 121 on chip 12c.By setting the second pad
121, the electric connection ability of chip and conducting connecting part 17 can be strengthened, so as to lift the electric connection between adjacent chip
Ability, avoids the occurrence of and occurs the unstable situation of data transfer between chip and chip.
Therefore, final chip 12a, chip 12b can pass through the second pad 121, first the 14, second conductive structure of conductive member
Part 15 and the 3rd conductive member 16 electrically conduct with substrate 13.
The substrate 13 is equipped with several conductive columns 132, the conductive column 132 backwards to the one side of first pad 131
Through the substrate 13 to be turned on first pad 131, and at least one conductive column 132 is used to be grounded.Wherein, lead
The quantity of electric column 132 can be identical with the quantity of the first pad 131, and the sum of height of 132 and first pad 131 of conductive column can be with
Equal to the height of substrate 13, the height of substrate 13 can also be higher than, specifically can according to the actual conditions of the circuit board of product into
Row is set.Wherein, it is corresponding for each chip, such as chip 12a in order to preferably be grounded and heat dissipation effect
Conductive column 132 in, for ground connection conductive column 132 diameter can be more than other conductive columns 132 diameter.Conductive column 132
Copper post or aluminium column can be used to realize.
In addition, in the present embodiment, positioned at 13 outermost of substrate the first pad 131 with it is outer positioned at the substrate 13 times
The distance between first pad 131 surveyed is less than the distance between other adjacent described first pads 131.By above-mentioned reasonable
The distance between the first pad of arrangement 131, there is enough spacing between the first pad 131 that can ensure to need to connect up,
So as to increase the width of wiring, product cost and difficulty of processing can be reduced.
In addition, in order to lift the reliability of product, the coat of metal 133 can be equipped with the outer surface of conductive column 132, such as copper
Nickel chromium triangle, hard chrome, chemical nickel etc., by the outer surface of conductive column 132 set the coat of metal 133, can ensure conductive column 132 with
Electric connection stability between corresponding electrical equipment, lifts the reliability of product.It should be noted that in order to ensure chip
Overall thinner thickness is encapsulated, the thickness control of the coat of metal 133 is at 20~30 microns.
According to the chip package 100a of the present embodiment, connected between adjacent two chips by a conducting connecting part 17,
Conducting connecting part 17 is contacted with the first surface 111 of substrate 11, i.e., multiple conducting connecting parts 17 are equipped between chip and substrate 11,
Data transfer between adjacent chip can be realized by the conducting connecting part 17 between chip, without using silicon hole skill again
Art perforate, cost of implementation is low, and encapsulation process is simple, and compares first embodiment, in the present embodiment, by setting the second pad
121, the electric connection ability between adjacent chip can be effectively lifted, avoids the occurrence of between chip and chip and data biography occurs
Defeated unstable situation.Further, since setting the first conductive member 14 between substrate 11 and substrate 13, second is equipped with substrate 11
Conductive member 15, is equipped with several the 3rd conductive members 16 between substrate 15 and chip, and chip passes through the described first conductive structure
Part 14, second conductive member 15 and the 3rd conductive member 16 electrically conduct with substrate 13, realize chip and substrate 13
Data transfer, and substrate 13 is equipped with conductive column 132 backwards to the one side of the first pad 131, since the quantity of conductive column 132 is more
A, one of conductive column 132 is used to be grounded, therefore conductive column 132 can also be used as radiator while conducting is realized,
The heat dissipation performance of final lifting chip package 100a.
Referring to Fig. 4, the chip package 100b that third embodiment of the invention proposes, including substrate 11, the substrate 11 have
There are the first surface 111 and second surface 112 being oppositely arranged.Substrate 11 may include dielectric material, such as organic material, You Jicai
Material can be the polypropylene (polypropylene, PP) with glass fibre, epoxy resin (epoxy resin), polyimides
(polyimide), cyanate (cyanateester) or foregoing combination, it is possible to understand that, substrate 11 can also use polyamides
Imines (Polyimide, PI) or silicon nitride (Si3N4) or semi-conducting material, semi-conducting material such as silicon.
The first surface 111 is equipped with multiple chips, and for convenience of description, in the present embodiment, the quantity of chip is with three
Illustrated exemplified by a, specially chip 12a, chip 12b, chip 12c, the structure all same of each chip, therefore, this implementation
In example, only illustrated by taking the structure of one of chip as an example.It is noted that include two chips for chip package
Or the situation of more than three chips, the structure and principle between two neighboring chip are identical with the present embodiment.Therefore, the application
It is not limited to the situation of three chips.
The second surface 112 is equipped with substrate 13, specifically, substrate 13 is located at the bottom of substrate 11, substrate 13 can be with
It is dielectric material or circuit board.Substrate 13 is used for realization to be electrically connected with the corresponding electronic component in end product.
Multiple spaced first conductive members 14 are equipped between the substrate 11 and the substrate 13.First conductive structure
Part 14 can be the one or more in conductive bump, conducting sphere, welding block, soldered ball.
Several second conductive members 15 are equipped with the substrate 11.Second conductive member 15 can also be conductive stud
One or more in block, conducting sphere, welding block, soldered ball.The number of second conductive member 15 and first conductive member 14
Amount can be identical, the quantity of first conductive member 14 can also unnecessary second conductive member 15 quantity.It may be noted that
It is that the first conductive member 14 and the second conductive member 15 should be correspondingly arranged as far as possible, that is, ensures the first conductive member 14 and
Two conductive members 15 can contact, and be electrically conducted with realizing.
Several the 3rd conductive structures are equipped between the substrate 11 and chip (including chip 12a, chip 12b, chip 12c)
Part 16, it is possible to understand that, the 3rd conductive member 16 can also be one kind or more in conductive bump, conducting sphere, welding block, soldered ball
Kind.
Connected between two adjacent chips by a conducting connecting part 17, specifically, between chip 12a and chip 12b
Equipped with conducting connecting part 17, conducting connecting part 17 also is provided between chip 12b and chip 12c.And the conducting connecting part 17 with
The first surface 111 contacts.Conducting connecting part 17 is, for example, strip, and conducting connecting part 17 can be that metal material or inside contain
There are the polyimides (Polyimide, PI) or silicon nitride (Si of metal conductive wire3N4).Conducting connecting part 17 is used for and chip 12a
Or the electrical components conducting on chip 12b or chip 12c, can since conducting connecting part 17 itself is also conductive material
Electrically conducting for chip 12a and chip 12b or chip 12b and chip 12c is realized, so as to fulfill the data between adjacent chip
Transmission.It should be noted that when conducting connecting part 17 using it is internal containing metal conductive wire polyimides (Polyimide,
) or silicon nitride (Si PI3N4) when, metal conductive wire at least leaks out two endpoints in conducting connecting part 17, for respectively with it is adjacent
Chip on electrical components conducting.
The one side that the substrate 13 is contacted with the substrate 11 is equipped with several first pads 131, the number of the first pad 131
Amount can be identical with the quantity of the first conductive member 14, and the first pad 131 and the 14 corresponding setting of the first conductive member, accordingly
The first conductive member 14 and the first pad 131 on position are in contact conducting.
The one side of each chip towards substrate 11 is all provided with setting several the second pads 121, positioned at two adjacent chips
Between conducting connecting part 17 be connected respectively with least one second pad 121 on the adjacent chip.That is, chip 12a
Be connected respectively with least one second pad 121 on chip 12a with the conducting connecting parts 17 of chip 12b between the two and
It is connected with least one second pad 121 on chip 12b, similarly, chip 12b being conductively connected between the two with chip 12c
Part 17 is connected with least one second pad 121 on chip 12b and is welded with least one second on chip 12c respectively
Disk 121 connects, and by setting the second pad 121, can strengthen the electric connection ability of chip and conducting connecting part 17, so as to carry
The electric connection ability between adjacent chip is risen, avoids the occurrence of and occurs the unstable feelings of data transfer between chip and chip
Condition.
Therefore, final chip 12a, chip 12b, chip 12c can pass through the second pad 121, the first conductive member 14,
Two conductive members 15 and the 3rd conductive member 16 electrically conduct with substrate 13.
In addition, in the present embodiment, some reinforcers 18 are additionally provided with first surface 111, the reinforcer 18 is positioned at adjacent
The chip between, and the reinforcer 17 extends beyond the edge of the substrate 11.Between i.e. chip 12a and chip 12b,
Between the chip 12b and chip 12c and edge of substrate 11 is equipped with reinforcer 18.
Wherein, by substrate 11 first surface 111 increase reinforcer 18, and reinforcer 18 be located at adjacent chip it
Between, while reinforcer 18 extends beyond the edge of substrate 11, can effectively avoid 11 warpage of substrate, lifting chip package 100b's
Structural strength and stability.
Further, the thermal conductivity factor of the reinforcer 18 is higher than the thermal conductivity factor of the substrate 11, the reinforcer 18
Can be one or several kinds of combinations in aluminium, copper, gold.Since the thermal conductivity factor of reinforcer 18 is higher than the heat conduction system of substrate 11
Number, can effectively absorb thermal energy caused by chip operation, so as to lift the heat dissipation effect of chip package 100b.
The substrate 13 is equipped with several conductive columns 132, the conductive column 132 backwards to the one side of first pad 131
Through the substrate 13 to be turned on first pad 131, and at least one conductive column 132 is used to be grounded.Wherein, lead
The quantity of electric column 132 can be identical with the quantity of the first pad 131, and the sum of height of 132 and first pad 131 of conductive column can be with
Equal to the height of substrate 13, the height of substrate 13 can also be higher than, specifically can according to the actual conditions of the circuit board of product into
Row is set.Wherein, it is corresponding for each chip, such as chip 12a in order to preferably be grounded and heat dissipation effect
Conductive column 132 in, for ground connection conductive column 132 diameter can be more than other conductive columns 132 diameter.Conductive column 132
Copper post or aluminium column can be used to realize.
In addition, in the present embodiment, positioned at 13 outermost of substrate the first pad 131 with it is outer positioned at the substrate 13 times
The distance between first pad 131 surveyed is less than the distance between other adjacent described first pads 131.By above-mentioned reasonable
The distance between the first pad of arrangement 131, there is enough spacing between the first pad 131 that can ensure to need to connect up,
So as to increase the width of wiring, product cost and difficulty of processing can be reduced.
In addition, in order to lift the reliability of product, the coat of metal 133 can be equipped with the outer surface of conductive column 132, such as copper
Nickel chromium triangle, hard chrome, chemical nickel etc., by the outer surface of conductive column 132 set the coat of metal 133, can ensure conductive column 132 with
Electric connection stability between corresponding electrical equipment, lifts the reliability of product.It should be noted that in order to ensure chip
Overall thinner thickness is encapsulated, the thickness control of the coat of metal 133 is at 20~30 microns.
According to the chip package 100b of the present embodiment, connected between adjacent two chips by a conducting connecting part 17,
Conducting connecting part 17 is contacted with the first surface 111 of substrate 11, i.e., multiple conducting connecting parts 17 are equipped between chip and substrate 11,
Data transfer between adjacent chip can be realized by the conducting connecting part 17 between chip, without using silicon hole skill again
Art perforate, cost of implementation is low, and encapsulation process is simple, further, since the first conductive member 14 is set between substrate 11 and substrate 13,
The second conductive member 15 is equipped with substrate 11, several the 3rd conductive members 16 are equipped between substrate 15 and chip, and chip leads to
First conductive member 14, second conductive member 15 and the 3rd conductive member 16 is crossed to electrically conduct with substrate 13,
Realize the data transfer of chip and substrate 13, and substrate 13 is equipped with conductive column 132 backwards to the one side of the first pad 131, due to leading
To be multiple, one of conductive column 132 is used to be grounded the quantity of electric column 132, thus conductive column 132 realize turn on while,
Radiator can also be used as, the final heat dissipation performance for lifting chip package 100b.It is in addition, and real compared to first embodiment and second
Example is applied, the present embodiment can effectively avoid 11 warpage of substrate by setting reinforcer 18, and the structure of lifting chip package 100b is strong
Degree and stability.The thermal conductivity factor of reinforcer 18 is higher than the thermal conductivity factor of substrate 11, is produced when can effectively absorb chip operation
Thermal energy, so as to further lift the heat dissipation effect of chip package 100b.
Referring to Fig. 5, the chip package 100c that fourth embodiment of the invention proposes, including substrate 11, the substrate 11 have
There are the first surface 111 and second surface 112 being oppositely arranged.Substrate 11 may include dielectric material, such as organic material, You Jicai
Material can be the polypropylene (polypropylene, PP) with glass fibre, epoxy resin (epoxy resin), polyimides
(polyimide), cyanate (cyanateester) or foregoing combination, it is possible to understand that, substrate 11 can also use polyamides
Imines (Polyimide, PI) or silicon nitride (Si3N4) or semi-conducting material, semi-conducting material such as silicon.
The first surface 111 is equipped with multiple chips, and for convenience of description, in the present embodiment, the quantity of chip is with three
Illustrated exemplified by a, specially chip 12a, chip 12b, chip 12c, the structure all same of each chip, therefore, this implementation
In example, only illustrated by taking the structure of one of chip as an example.It is noted that include two chips for chip package
Or the situation of more than three chips, the structure and principle between two neighboring chip are identical with the present embodiment.Therefore, the application
It is not limited to the situation of three chips.
The second surface 112 is equipped with substrate 13, specifically, substrate 13 is located at the bottom of substrate 11, substrate 13 can be with
It is dielectric material or circuit board.Substrate 13 is used for realization to be electrically connected with the corresponding electronic component in end product.
Multiple spaced first conductive members 14 are equipped between the substrate 11 and the substrate 13.First conductive structure
Part 14 can be the one or more in conductive bump, conducting sphere, welding block, soldered ball.
Several second conductive members 15 are equipped with the substrate 11.Second conductive member 15 can also be conductive stud
One or more in block, conducting sphere, welding block, soldered ball.The number of second conductive member 15 and first conductive member 14
Amount can be identical, the quantity of first conductive member 14 can also unnecessary second conductive member 15 quantity.It may be noted that
It is that the first conductive member 14 and the second conductive member 15 should be correspondingly arranged as far as possible, that is, ensures the first conductive member 14 and
Two conductive members 15 can contact, and be electrically conducted with realizing.
Several the 3rd conductive structures are equipped between the substrate 11 and chip (including chip 12a, chip 12b, chip 12c)
Part 16, it is possible to understand that, the 3rd conductive member 16 can also be one kind or more in conductive bump, conducting sphere, welding block, soldered ball
Kind.
Connected between two adjacent chips by a conducting connecting part 17, specifically, between chip 12a and chip 12b
Equipped with conducting connecting part 17, conducting connecting part 17 also is provided between chip 12b and chip 12c.And the conducting connecting part 17 with
The first surface 111 contacts.Conducting connecting part 17 is, for example, strip, and conducting connecting part 17 can be that metal material or inside contain
There are the polyimides (Polyimide, PI) or silicon nitride (Si of metal conductive wire3N4).Conducting connecting part 17 is used for and chip 12a
Or the electrical components conducting on chip 12b or chip 12c, can since conducting connecting part 17 itself is also conductive material
Electrically conducting for chip 12a and chip 12b or chip 12b and chip 12c is realized, so as to fulfill the data between adjacent chip
Transmission.It should be noted that when conducting connecting part 17 using it is internal containing metal conductive wire polyimides (Polyimide,
) or silicon nitride (Si PI3N4) when, metal conductive wire at least leaks out two endpoints in conducting connecting part 17, for respectively with it is adjacent
Chip on electrical components conducting.
The one side that the substrate 13 is contacted with the substrate 11 is equipped with several first pads 131, the number of the first pad 131
Amount can be identical with the quantity of the first conductive member 14, and the first pad 131 and the 14 corresponding setting of the first conductive member, accordingly
The first conductive member 14 and the first pad 131 on position are in contact conducting.
The one side of each chip towards substrate 11 is all provided with setting several the second pads 121, positioned at two adjacent chips
Between conducting connecting part 17 be connected respectively with least one second pad 121 on the adjacent chip.That is, chip 12a
Be connected respectively with least one second pad 121 on chip 12a with the conducting connecting parts 17 of chip 12b between the two and
It is connected with least one second pad 121 on chip 12b, similarly, chip 12b being conductively connected between the two with chip 12c
Part 17 is connected with least one second pad 121 on chip 12b and is welded with least one second on chip 12c respectively
Disk 121 connects, and by setting the second pad 121, can strengthen the electric connection ability of chip and conducting connecting part 17, so as to carry
The electric connection ability between adjacent chip is risen, avoids the occurrence of and occurs the unstable feelings of data transfer between chip and chip
Condition.
Therefore, final chip 12a, chip 12b, chip 12c can pass through the second pad 121, the first conductive member 14,
Two conductive members 15 and the 3rd conductive member 16 electrically conduct with substrate 13.
In addition, in the present embodiment, some reinforcers 18 are additionally provided with first surface 111, the reinforcer 18 is positioned at adjacent
The chip between, and the reinforcer 17 extends beyond the edge of the substrate 11.Between i.e. chip 12a and chip 12b,
Between the chip 12b and chip 12c and edge of substrate 11 is equipped with reinforcer 18.
In the present embodiment, reinforcer 18 also covers one side of all chips backwards to the substrate 11, i.e. reinforcer 18 covers
Cover core piece 12a, chip 12b, chip 12c backwards to substrate 11 one side, since reinforcer 18 covers all chips backwards to substrate
11 one side, can protect all chips from impaired or contaminated.
Wherein, by substrate 11 first surface 111 increase reinforcer 18, and reinforcer 18 be located at adjacent chip it
Between, while reinforcer 18 extends beyond the edge of substrate 11, can effectively avoid 11 warpage of substrate, lifting chip package 100c's
Structural strength and stability.
Further, the thermal conductivity factor of the reinforcer 18 is higher than the thermal conductivity factor of the substrate 11, the reinforcer 18
Can be one or several kinds of combinations in aluminium, copper, gold.Since the thermal conductivity factor of reinforcer 18 is higher than the heat conduction system of substrate 11
Number, can effectively absorb thermal energy caused by chip operation, so as to lift the heat dissipation effect of chip package 100c.
In addition, in the present embodiment, mucigel 19 is equipped between reinforcer 18 and substrate 11.Mucigel 19 is for example with high score
Sub- adhesive, by adding mucigel 19 between reinforcer 18 and substrate 11, can ensure that product is strengthened after long-term use
Part 18 will not fall off with substrate 11, the structural strength and stability of lifting chip package 100c.
It is pointed out that mucigel 19 is positioned only between reinforcer 18 and substrate 11, reinforcer 18 and chip 12a it
Between, be not provided with mucigel 19 between reinforcer 18 and chip 12b and between reinforcer 18 and chip 12c, in order to avoid mucigel
19 influence the working effect of chip.
The substrate 13 is equipped with several conductive columns 132, the conductive column 132 backwards to the one side of first pad 131
Through the substrate 13 to be turned on first pad 131, and at least one conductive column 132 is used to be grounded.Wherein, lead
The quantity of electric column 132 can be identical with the quantity of the first pad 131, and the sum of height of 132 and first pad 131 of conductive column can be with
Equal to the height of substrate 13, the height of substrate 13 can also be higher than, specifically can according to the actual conditions of the circuit board of product into
Row is set.Wherein, it is corresponding for each chip, such as chip 12a in order to preferably be grounded and heat dissipation effect
Conductive column 132 in, for ground connection conductive column 132 diameter can be more than other conductive columns 132 diameter.Conductive column 132
Copper post or aluminium column can be used to realize.
In addition, in the present embodiment, positioned at 13 outermost of substrate the first pad 131 with it is outer positioned at the substrate 13 times
The distance between first pad 131 surveyed is less than the distance between other adjacent described first pads 131.By above-mentioned reasonable
The distance between the first pad of arrangement 131, there is enough spacing between the first pad 131 that can ensure to need to connect up,
So as to increase the width of wiring, product cost and difficulty of processing can be reduced.
In addition, in order to lift the reliability of product, the coat of metal 133 can be equipped with the outer surface of conductive column 132, such as copper
Nickel chromium triangle, hard chrome, chemical nickel etc., by the outer surface of conductive column 132 set the coat of metal 133, can ensure conductive column 132 with
Electric connection stability between corresponding electrical equipment, lifts the reliability of product.It should be noted that in order to ensure chip
Overall thinner thickness is encapsulated, the thickness control of the coat of metal 133 is at 20~30 microns.
According to the chip package 100c of the present embodiment, connected between adjacent two chips by a conducting connecting part 17,
Conducting connecting part 17 is contacted with the first surface 111 of substrate 11, i.e., multiple conducting connecting parts 17 are equipped between chip and substrate 11,
Data transfer between adjacent chip can be realized by the conducting connecting part 17 between chip, without using silicon hole skill again
Art perforate, cost of implementation is low, and encapsulation process is simple, further, since the first conductive member 14 is set between substrate 11 and substrate 13,
The second conductive member 15 is equipped with substrate 11, several the 3rd conductive members 16 are equipped between substrate 15 and chip, and chip leads to
First conductive member 14, second conductive member 15 and the 3rd conductive member 16 is crossed to electrically conduct with substrate 13,
Realize the data transfer of chip and substrate 13, and substrate 13 is equipped with conductive column 132 backwards to the one side of the first pad 131, due to leading
To be multiple, one of conductive column 132 is used to be grounded the quantity of electric column 132, thus conductive column 132 realize turn on while,
Radiator can also be used as, the final heat dissipation performance for lifting chip package 100c.In addition, by setting reinforcer 18, Neng Gouyou
Effect avoids 11 warpage of substrate, the structural strength and stability of lifting chip package 100c.The thermal conductivity factor of reinforcer 18 is higher than base
The thermal conductivity factor at bottom 11, can effectively absorb thermal energy caused by chip operation, so as to further lift chip package 100c's
Heat dissipation effect.In addition, and compare 3rd embodiment, reinforcer 18 covers all chips backwards to the one of substrate 11 in the present embodiment
Face, can protect all chips from impaired or contaminated, mucigel 19 is equipped between reinforcer 18 and substrate 11, enough guarantees
Reinforcer 18 will not fall off product with substrate 11 after long-term use, the structural strength and stability of lifting chip package 100c.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or the spy for combining the embodiment or example description
Point is contained at least one embodiment of the present invention or example.In the present specification, schematic expression of the above terms is not
Necessarily refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any
One or more embodiments or example in combine in an appropriate manner.
Embodiment described above only expresses the several embodiments of the present invention, its description is more specific and detailed, but simultaneously
Therefore the limitation to the scope of the claims of the present invention cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the guarantor of the present invention
Protect scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of chip package, including substrate, it is characterised in that the substrate has the first surface and the second table being oppositely arranged
Face, the first surface are equipped with multiple chips, and the second surface is equipped with substrate, is set between the substrate and the substrate
Have multiple spaced first conductive members, be equipped with several second conductive members in the substrate, the substrate with it is described
Several the 3rd conductive members are equipped between chip, are connected between adjacent two chips by a conducting connecting part, institute
State conducting connecting part to contact with the first surface, the one side that the substrate is contacted with the substrate is equipped with several the first welderings
Disk, the chip pass through first conductive member, second conductive member and the 3rd conductive member and the substrate
Electrically conduct, the substrate is equipped with several conductive columns backwards to the one side of first pad, and the conductive column runs through the base
Plate to be turned on first pad, and at least one conductive column be used for be grounded, for ground connection the conductive column it is straight
Footpath is more than the diameter of other conductive columns.
2. chip package according to claim 1, it is characterised in that each chip is equal towards the one side of the substrate
Equipped with several the second pads, the conducting connecting part between two adjacent chips respectively with adjacent two
At least one second pad connection on the chip.
3. chip package according to claim 2, it is characterised in that the conducting connecting part contains for metal material or inside
There are the polyimides or silicon nitride of metal conductive wire.
4. chip package according to claim 1, it is characterised in that some reinforcers are additionally provided with the first surface,
The reinforcer is between the adjacent chip, and the reinforcer extends beyond the edge of the substrate.
5. chip package according to claim 4, it is characterised in that viscose is equipped between the reinforcer and the substrate
Layer.
6. chip package according to claim 4, it is characterised in that the reinforcer covers all chips backwards
The one side of the substrate.
7. according to the chip package described in claim 4 to 6 any one, it is characterised in that the thermal conductivity factor of the reinforcer
Higher than the thermal conductivity factor of the substrate.
8. chip package according to claim 7, it is characterised in that the reinforcer for aluminium, copper, gold in one kind or
Several combinations.
9. chip package according to claim 1, it is characterised in that positioned at first pad of the substrate outermost
The distance between described first pad positioned at the substrate time exterior measuring is less than between other adjacent first pads
Distance.
10. chip package according to claim 1, it is characterised in that the outer surface of the conductive column is equipped with the coat of metal,
The thickness of the coat of metal is 20~30 microns.
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| CN201711105653.6A CN107910315B (en) | 2017-11-10 | 2017-11-10 | Chip package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711105653.6A CN107910315B (en) | 2017-11-10 | 2017-11-10 | Chip package |
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| CN107910315B CN107910315B (en) | 2020-09-25 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111276473A (en) * | 2018-12-04 | 2020-06-12 | Qorvo美国公司 | Monolithic microwave integrated circuit with backside interconnect for fan-out package |
| WO2021184166A1 (en) * | 2020-03-16 | 2021-09-23 | 华为技术有限公司 | Electronic apparatus, chip packaging structure, and manufacturing method for same |
| WO2021189292A1 (en) * | 2020-03-25 | 2021-09-30 | 华为技术有限公司 | Chip structure and chip preparation method |
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| CN102034718A (en) * | 2009-09-23 | 2011-04-27 | 新科金朋有限公司 | Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP |
| CN103151341A (en) * | 2013-03-13 | 2013-06-12 | 江苏物联网研究发展中心 | System-level packaging structure |
| CN104617072A (en) * | 2015-01-30 | 2015-05-13 | 华进半导体封装先导技术研发中心有限公司 | Improved three-dimensional chip integrated structure and processing technology thereof |
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| JPH09232473A (en) * | 1996-02-21 | 1997-09-05 | Toshiba Corp | Semiconductor package and its manufacture and printed board |
| CN102034718A (en) * | 2009-09-23 | 2011-04-27 | 新科金朋有限公司 | Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP |
| CN103151341A (en) * | 2013-03-13 | 2013-06-12 | 江苏物联网研究发展中心 | System-level packaging structure |
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| CN111276473A (en) * | 2018-12-04 | 2020-06-12 | Qorvo美国公司 | Monolithic microwave integrated circuit with backside interconnect for fan-out package |
| WO2021184166A1 (en) * | 2020-03-16 | 2021-09-23 | 华为技术有限公司 | Electronic apparatus, chip packaging structure, and manufacturing method for same |
| WO2021189292A1 (en) * | 2020-03-25 | 2021-09-30 | 华为技术有限公司 | Chip structure and chip preparation method |
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| CN107910315B (en) | 2020-09-25 |
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