CN107910304A - 一种1p2m cmos的封装方法 - Google Patents
一种1p2m cmos的封装方法 Download PDFInfo
- Publication number
- CN107910304A CN107910304A CN201710879035.0A CN201710879035A CN107910304A CN 107910304 A CN107910304 A CN 107910304A CN 201710879035 A CN201710879035 A CN 201710879035A CN 107910304 A CN107910304 A CN 107910304A
- Authority
- CN
- China
- Prior art keywords
- packing
- copper
- cmos
- layer
- glue
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000012856 packing Methods 0.000 title claims abstract description 13
- 229910052802 copper Inorganic materials 0.000 claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 8
- 238000001020 plasma etching Methods 0.000 claims abstract description 6
- 239000010949 copper Substances 0.000 claims description 24
- 239000003292 glue Substances 0.000 claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- 239000007788 liquid Substances 0.000 claims description 18
- 238000007747 plating Methods 0.000 claims description 13
- 239000004642 Polyimide Substances 0.000 claims description 12
- 229920001721 polyimide Polymers 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 11
- 238000004528 spin coating Methods 0.000 claims description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000009713 electroplating Methods 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 238000011161 development Methods 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 8
- 238000004026 adhesive bonding Methods 0.000 claims description 7
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- 239000002253 acid Substances 0.000 claims description 4
- 239000000654 additive Substances 0.000 claims description 4
- 230000000996 additive effect Effects 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 4
- 239000002659 electrodeposit Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 238000009966 trimming Methods 0.000 claims description 4
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 238000009499 grossing Methods 0.000 claims description 3
- 238000010992 reflux Methods 0.000 claims description 3
- 241000370738 Chlorion Species 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 claims description 2
- 150000003949 imides Chemical class 0.000 claims 1
- 238000010422 painting Methods 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 13
- 238000004544 sputter deposition Methods 0.000 abstract description 11
- 238000005530 etching Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 28
- 238000005260 corrosion Methods 0.000 description 8
- 230000007797 corrosion Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000013461 design Methods 0.000 description 3
- 239000011295 pitch Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- -1 1- methoxy-2-propanols acetic acid esters Chemical class 0.000 description 1
- ARXJGSRGQADJSQ-UHFFFAOYSA-N 1-methoxypropan-2-ol Chemical class COCC(C)O ARXJGSRGQADJSQ-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
本发明涉及一种1P2M CMOS的封装方法,包括:光刻、溅射、等离子刻蚀、电镀、去胶和回流等过程。本发明封装的1P2M相对2P2M少了第二层PI,无需刻蚀第一层Ti、Cu溅射层,无需溅射第二层Ti、Cu,在原料成本和作业时间上更节约的同时,仍能够保持其该有的性能,具有良好的应用前景。
Description
技术领域
本发明属于晶圆级芯片封装领域,特别涉及一种1P2M CMOS的封装方法。
背景技术
2P2M与1P2M是通过再布线将凸块长在芯片适当位置的一种技术,2P2M比1P2M多一层PI及多溅射了一层铜钛,材料成本较多,作业时间较长。
发明内容
本发明所要解决的技术问题是提供一种1P2M CMOS的封装方法,该方法封装的1P2M相对2P2M少了第二层PI,无需刻蚀第一层Ti、Cu溅射层,无需溅射第二层Ti、Cu,在原料成本和作业时间上更节约的同时,仍能够保持其该有的性能,具有良好的应用前景。
本发明提供了一种1P2M CMOS的封装方法,包括:
(1)在晶圆表面涂覆聚酰亚胺再钝化层;
(2)在再钝化层表面溅射Ti阻挡层和Cu种子层;
(3)使用AZ(主要成分1-甲氧基-2-丙醇乙酸酯和1-甲氧基-2-丙醇)光刻胶,经匀胶、甩胶、背洗(BSR)、甩干、甩边、烘烤、去边,得到14±3μm的AZ胶厚,再经曝光、显影,得到RDL图形;
(4)对得到RDL图形的晶圆表面进行等离子刻蚀,然后电镀8μm铜厚;其中,采用的电镀液为SC28铜电镀液;
(5)在RDL的基础上再次经涂胶、曝光、显影形成电镀图形后,电镀铜、锡形成铜锡柱;其中,采用的电镀液为SC28铜电镀液和Sn电渡液;
(6)使用KS3504去胶液,进行去胶;随后腐蚀图形外的溅射钛铜层,得到凸点;
(7)最后将电镀的锡回流成球形,即可。
所述步骤(1)中的聚酰亚胺再钝化层的厚度为5μm。
所述步骤(1)中的涂覆具体步骤包括匀胶、甩胶、背洗(BSR)、甩干和甩边。
所述步骤(4)和(5)中的SC28铜电镀液的组成为:铜25-30g/L,硫酸200-300g/L,氯离子40-50mg/L,光亮剂MD 5-6ml/L,平整剂LO 3-5ml/L。
所述步骤(5)中的Sn电渡液的组成为:Sn2+20-50g/L、甲基磺酸80-120g/L、添加剂C3-10g/L、添加剂GR 30-70g/L。
所述步骤(6)中的去胶时间为60min。
所述步骤(6)中的腐蚀采用KS6201和KS6506进行腐蚀。
有益效果
本发明封装的1P2M相对2P2M少了第二层PI,无需刻蚀第一层Ti、Cu溅射层,无需溅射第二层Ti、Cu,在原料成本和作业时间上更节约的同时,仍能够保持其该有的性能,具有良好的应用前景。
附图说明
图1为本发明的结构示意图;
图2为本发明的工艺流程图。
具体实施方式
下面结合具体实施例,进一步阐述本发明。应理解,这些实施例仅用于说明本发明而不用于限制本发明的范围。此外应理解,在阅读了本发明讲授的内容之后,本领域技术人员可以对本发明作各种改动或修改,这些等价形式同样落于本申请所附权利要求书所限定的范围。
实施例1
1)多层聚酰亚胺(PI)再钝化层涂覆工艺
聚酰亚胺(PI)光致抗蚀剂具有突出的耐热性,卓越的力学性能,绝缘性和抗蚀性。首先自动涂胶机在圆片表面定量涂布5ml的PI胶,通过旋涂、前烘、光刻、显影及固化工艺,最终在圆片表面形成一层5um的聚酰亚胺再钝化层,起到绝缘、抗蚀、缓冲应力及平坦化的作用。其中旋涂分为匀胶(200±20rpm,7±1s)、甩胶(2450±100rpm,30±3s)、BSR(1000±50rpm,15±1s)、甩干(1000±50rpm,10±1s)、甩边(3000±50rpm,1±0.1s)5个过程,涂胶完成后在曝光能量300mj、间距4um下进行stepper曝光,并在显影液KS5400(上海飞凯光电材料股份有限公司)下进行显影得到所需的图像,最后在无氧固化烘箱(氧含量控制在20ppm以下)350℃下烘烤2h进行固化。
2)多层金属溅射镀膜工艺
首先利用先进的选择性湿法刻蚀工艺对氧化层进行刻蚀而原Al垫基本无损伤,其刻蚀厚度为200±30A。然后通过多层金属溅射镀膜工艺引入厚度1000±150A的Ti阻挡层和4000±400A的Cu种子层。为满足可靠性要求,在凸点面积进一步缩小的情况下,溅射金属层高度也作了进一步优化。
3)高分辨光刻工艺
采用高分辨光刻胶通过先进的旋涂烘焙技术和高灵敏光刻显影技术,在晶圆表面形成严整清晰的图形又不会在小开口中留下残存的光刻胶,从而保证了后续凸点的高质量和有效连接。其中利用AZ胶可生成所需的RDL图形,在圆片表面定量涂布8ml的AZ胶,通过匀胶(700±30rpm,15±5s)、甩胶(1150±65rpm,15±5s)、BSR(1000±50rpm,15±5s)、甩干(1000±50rpm,10±2s)、甩边(1200±100rpm,1±0.2s)、烘烤(90℃,30min)、去边(EBR:600±100rpm,54±2s;BSR:600±100rpm,10±1s;边缘去边宽度:1.5~2.4mm)等过程得到14±3um的AZ胶厚,然后在曝光能量为1700mj,间距20um条件下进行整面曝光,最后在显影液KS5700下显影显现出所需的RDL图形。
利用JSR胶则可形成凸点的电镀图形,其过程与AZ形成RDL图形的过程类似,也是主要经过涂胶、曝光、显影等步骤。JSR的涂胶分为一次涂胶(胶量:5ml,clean:50±15rpm,2±0.2s;匀胶:1300±50rpm,16±2s)和二次涂胶(胶量:4ml;EBR:600±50rpm,19±2s;匀胶1600±60rpm,15±2s;BSR:1000±100rpm,8±2s;甩胶:1000±100rpm,5±2s;甩边;1500±100rpm,1±0.2s),两次涂胶之间需在120℃下烘烤400s,旋涂完成后在曝光能量1000mj、间距-26um下进行stepper曝光,最后在显影液KS5300下显影显现出电镀图形。
4)等离子刻蚀工艺
控制适当的频率、能量和时间等条件,对溅射层进行等离子刻蚀增加层间结合力;对光刻胶层进行等离子刻蚀增加表面亲水性防止漏镀,同时去除窗口金属表面可能带有的残胶和其他有机粘污,保证了窄节距凸点的高质量和有效连接。根据刻蚀底材的不同,刻蚀参数也有所差别,具体参数见下表。
5)电镀重新布线工艺
通过筛选高分辨率的AZ光阻材料,经曝光能量1700mj,曝光间距20um下曝光后在显影液KS5700下显影形成清晰的光刻图形;选用高润湿性Cu镀液,电镀形成清晰、一致的8um厚度的重新布线层,从而使设计更加灵活,或者在一定条件下,将传统的打线产品直接转化为WLCSP倒装产品,提升了产品适应性。
SC28铜电镀液的成分及含量如下:铜25-30g/L,硫酸200-300g/L,氯离子40-50mg/L,光亮剂MD 5-6ml/L,平整剂LO 3-5ml/L。
窄节距凸点电镀形成工艺
在前期所形成的清晰的光刻图形基础上,筛选高润湿性Cu镀液和Sn渡液,电镀形成400um窄节距的凸点,无连桥和渗镀现象发生;在对溅射金属层进行选择性刻蚀的过程中,原Al垫基本无损伤。
Sn渡液的成分及含量如下:Sn2+20-50g/L、甲基磺酸80-120g/L、添加剂C 3-10g/L、添加剂GR 30-70g/L。
6)电镀后去胶技术
电镀完成后,通过在去胶液KS3504(上海飞凯光电材料股份有限公司)中浸泡60min去除圆片表面用来限定电镀位置的80~90um厚度的AZ光刻胶。Copper Pillar采用厚胶工艺,去胶难度较大,选择合适的去胶液,采用粗槽及净槽两次去胶,可以达到完全去胶干净的要求。
7)种子层腐蚀技术
去胶后,利用腐蚀液KS6201和KS6506(上海飞凯光电材料股份有限公司)将圆片表面多余的种子层及阻挡层去除。种子层的腐蚀做到完全腐蚀干净且尽量做到较少的过腐蚀需要控制一定的腐蚀时间,经验证,铜腐蚀240s,锡腐蚀200s能达到该效果,保障产品性能。
8)回流成球技术
运用锡金属熔化成球的物理特点,旋涂上型号为NCX5003的FLux助焊剂(美丰电子科技有限公司),合理设计回流升温/降温的曲线,使锡块在略高于其熔点的温度快速熔化成球状,降温定形,最终形成设计所需高度的铜锡,具体见下表。
Claims (7)
1.一种1P2M CMOS的封装方法,包括:
(1)在晶圆表面涂覆聚酰亚胺再钝化层;
(2)在再钝化层表面溅射Ti阻挡层和Cu种子层;
(3)使用AZ光刻胶,经匀胶、甩胶、背洗、甩干、甩边、烘烤、去边,得到14±3μm的AZ胶厚,再经曝光、显影,得到RDL图形;
(4)对得到RDL图形的晶圆表面进行等离子刻蚀,然后电镀8μm铜厚;其中,采用的电镀液为SC28铜电镀液;
(5)在RDL的基础上再次经涂胶、曝光、显影形成电镀图形后,电镀铜、锡形成铜锡柱;其中,采用的电镀液为SC28铜电镀液和Sn电渡液;
(6)使用KS3504去胶液,进行去胶;随后腐蚀图形外的溅射钛铜层,得到凸点;
(7)最后将电镀的锡回流成球形,即可。
2.根据权利要求1所述的一种1P2M CMOS的封装方法,其特征在于:所述步骤(1)中的聚酰亚胺再钝化层的厚度为5μm。
3.根据权利要求1所述的一种1P2M CMOS的封装方法,其特征在于:所述步骤(1)中的涂覆具体步骤包括匀胶、甩胶、背洗、甩干和甩边。
4.根据权利要求1所述的一种1P2M CMOS的封装方法,其特征在于:所述步骤(4)和(5)中的SC28铜电镀液的组成为:铜25-30g/L,硫酸200-300g/L,氯离子40-50mg/L,光亮剂MD5-6ml/L,平整剂LO 3-5ml/L。
5.根据权利要求1所述的一种1P2M CMOS的封装方法,其特征在于:所述步骤(5)中的Sn电渡液的组成为:Sn2+20-50g/L、甲基磺酸80-120g/L、添加剂C 3-10g/L、添加剂GR 30-70g/L。
6.根据权利要求1所述的一种1P2M CMOS的封装方法,其特征在于:所述步骤(6)中的去胶时间为60min。
7.根据权利要求1所述的一种1P2M CMOS的封装方法,其特征在于:所述步骤(6)中的腐蚀采用KS6201和KS6506进行腐蚀。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710879035.0A CN107910304A (zh) | 2017-09-26 | 2017-09-26 | 一种1p2m cmos的封装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710879035.0A CN107910304A (zh) | 2017-09-26 | 2017-09-26 | 一种1p2m cmos的封装方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN107910304A true CN107910304A (zh) | 2018-04-13 |
Family
ID=61840250
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710879035.0A Pending CN107910304A (zh) | 2017-09-26 | 2017-09-26 | 一种1p2m cmos的封装方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN107910304A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112076958A (zh) * | 2020-09-18 | 2020-12-15 | 吉林华微电子股份有限公司 | 芯片涂胶方法、装置及匀胶机 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102064154A (zh) * | 2009-11-05 | 2011-05-18 | 台湾积体电路制造股份有限公司 | 集成电路结构 |
CN104253053A (zh) * | 2013-06-25 | 2014-12-31 | 台湾积体电路制造股份有限公司 | 具有与凹槽相对准的焊料区的封装件 |
US20160099221A1 (en) * | 2014-10-01 | 2016-04-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
-
2017
- 2017-09-26 CN CN201710879035.0A patent/CN107910304A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102064154A (zh) * | 2009-11-05 | 2011-05-18 | 台湾积体电路制造股份有限公司 | 集成电路结构 |
CN104253053A (zh) * | 2013-06-25 | 2014-12-31 | 台湾积体电路制造股份有限公司 | 具有与凹槽相对准的焊料区的封装件 |
US20160099221A1 (en) * | 2014-10-01 | 2016-04-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method thereof |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112076958A (zh) * | 2020-09-18 | 2020-12-15 | 吉林华微电子股份有限公司 | 芯片涂胶方法、装置及匀胶机 |
CN112076958B (zh) * | 2020-09-18 | 2021-11-19 | 吉林华微电子股份有限公司 | 芯片涂胶方法、装置及匀胶机 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102881607B (zh) | 一种新型焦平面阵列电互连工艺 | |
TWI331494B (en) | Circuit board structure | |
CN1431681A (zh) | 利用弹性体电镀掩模做为芯片级封装的方法 | |
CN101330010A (zh) | 一种制作t型hbt发射极/hemt栅的方法 | |
CN101847592A (zh) | 一种基于电镀工艺制备铟焊球阵列方法 | |
CN107910304A (zh) | 一种1p2m cmos的封装方法 | |
CN109254423A (zh) | 一种铌酸锂电光器件厚膜导线电极的制作方法 | |
CN106504998A (zh) | 用于高密度微波电路组装的金属阻焊膜的制作方法及产物 | |
CN101561629A (zh) | 一种用倒梯形剖面的光刻胶制作介质边缘缓坡的方法 | |
TWI264253B (en) | Method for fabricating conductive connection structure of circuit board | |
CN114496809A (zh) | Htcc基板薄膜多层布线的制作方法 | |
CN102222630A (zh) | 一种制备Sn-Ag-In三元无铅倒装凸点的方法 | |
TWI419284B (zh) | 晶片之凸塊結構及凸塊結構之製造方法 | |
CN100576579C (zh) | 一种制备铟柱的方法 | |
CN105006437A (zh) | 一种高密度凸块结构的制造方法 | |
JP2010003793A (ja) | 配線基板、ポスト電極の転写用基板及び電子機器 | |
CN101908516B (zh) | 倒装芯片锡银凸块结构及其制造方法 | |
JP2007258714A (ja) | 高温工程に適した絶縁構造体及びその製造方法 | |
CN106024379B (zh) | 一种梁式引线电容的加工方法 | |
CN110581120A (zh) | 板级扇出封装基板的细线路结构及其制备方法 | |
CN110993556A (zh) | 一种电镀镍层作为掩模层的陶瓷薄膜电路制备方法 | |
CN110739237A (zh) | 一种新型电镀法制作大锡球方法 | |
WO2016107336A1 (zh) | 晶圆级封装的制造方法 | |
CN107895698A (zh) | 一种15μm铜厚的封装方法 | |
US10483232B2 (en) | Method for fabricating bump structures on chips with panel type process |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180413 |