CN107910280B - Method for establishing global regulation model for optimizing rapid thermal annealing - Google Patents
Method for establishing global regulation model for optimizing rapid thermal annealing Download PDFInfo
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- CN107910280B CN107910280B CN201711160733.1A CN201711160733A CN107910280B CN 107910280 B CN107910280 B CN 107910280B CN 201711160733 A CN201711160733 A CN 201711160733A CN 107910280 B CN107910280 B CN 107910280B
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Abstract
The invention provides a method for establishing a global regulation model to optimize rapid thermal annealing, which is applied to thermal compensation of a wafer during annealing, and comprises the following steps: carrying out a test, collecting and processing wafer test data, and establishing a global regulation model; calculating the required temperature compensation amount according to the global regulation model, and controlling the annealing temperature of the machine; has the advantages that: by collecting the parameter data of the resistance value, the film thickness and the like of the wafer and carrying out heat compensation on the wafer according to the parameter change of the wafer through the self-built global regulation model, the condition that different areas of the wafer are heated consistently and the electrical parameters of the semiconductor device are stable is ensured.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing, in particular to a method for establishing a global regulation model to optimize rapid thermal annealing.
Background
With the development of the semiconductor industry, integrated circuits are developed in the direction of small size, high speed, and low power consumption. The characteristic dimension of the semiconductor device is continuously reduced in proportion, the transverse and longitudinal diffusion degrees of the doped elements after annealing are correspondingly reduced, and the junction depth is shallow. In order to control the diffusion of the doping element, a rapid thermal annealing process (RTP) is commonly used. For the temperature adjustment of the wafer in the rapid thermal annealing process chamber, the current adjustment estimation model only affects the nearby area, and in reality, the temperature adjustment of each thermometer affects the whole wafer.
In the integrated circuit manufacturing process, it often occurs that: due to uneven heating of the wafer in the process chamber of the rapid thermal annealing machine, the resistance uniformity of the subsequent wafer manufacturing process fluctuates. For example: in the annealing process, the actual heat absorption of each region of the wafer is different, so that the uniformity of the related parameters (resistance, film thickness and the like) of the wafer temperature is poor, the related parameter change of a semiconductor device is caused, the difference between the adjustment estimation model of the nearby region and the actual is only influenced, and the expected purpose cannot be achieved by using the near region estimation model to perform machine temperature compensation.
Disclosure of Invention
Aiming at the problems, the invention provides a method for establishing a global regulation model to carry out optimized rapid thermal annealing, which is applied to thermal compensation of a wafer during annealing, and comprises the following steps:
step S1, performing a test, collecting and processing wafer test data, and establishing a global regulation model;
and step S2, calculating the required temperature compensation amount according to the global regulation model, and controlling the annealing temperature of the machine.
Wherein the step S1 includes the steps of:
step S11, measuring the temperature sensitive coefficient of the wafer resistance;
step S12, providing n test wafers, and respectively placing n-1 corresponding thermometers in different areas of the working chamber, wherein n is at least 4;
s13, setting a temperature compensation value, using 1 test wafer each time, and performing n-1 temperature compensation tests;
step S14, setting the temperature compensation value to be 0, and testing the rest test wafers to be used as baseline resistance data;
step S15, collecting resistance value data of the wafer;
step S16, subtracting the baseline resistance data from the resistance data to obtain the variation value of the resistance of each area of the wafer after the temperature compensation setting of each thermometer;
step S17, multiplying the change value of the resistance value of each area of the wafer after the temperature compensation setting of each thermometer by the temperature sensitivity coefficient to obtain the change value of the temperature data;
step S18, standardizing the change value of the temperature data to obtain the global temperature change value of the wafer when the temperature compensation of the test wafer changes by 1 ℃;
and step S19, calculating a relation coefficient A between the temperature compensation and the global temperature change value of the wafer when the temperature compensation value is 1.
Wherein the temperature compensation value ranges from 3 ℃ to 10 ℃.
Wherein the step of collecting wafer test data is as follows:
s151, collecting transverse data by taking m data points in the transverse direction of the test wafer, wherein m is at least 13;
s152, collecting longitudinal data by taking m data points in the longitudinal direction of the test wafer;
step S153, adding each longitudinal data and the corresponding transverse data, and averaging to obtain resistance data of m test wafers, wherein m is at least 13.
Wherein the temperature compensation test only changes the temperature compensation amount of one thermometer at a time, the temperature compensation of the remaining n-2 thermometers is 0, and n is at least 4.
Wherein the measuring method of step S11 is: adjusting the operation temperature of the operation cavity to three temperatures, respectively carrying out wafer tests at the three temperatures, obtaining and recording the average resistance of the wafer at the three temperatures, and calculating the temperature sensitivity coefficient according to the following formula:
in the formula, sensitivity is a temperature sensitive coefficient, R1 is an average resistance of the wafers tested in the first temperature test, R2 is an average resistance of the wafers tested in the second temperature test, and R3 is an average resistance of the wafers tested in the third temperature test.
The calculation method of the relation coefficient A comprises the following steps:
Offset(n-1)x1＝A(n-1)x m*Deltamx1，
in the formula, Offset(n-1)x1Temperature value to be compensated for the standardized rear thermometer, A(n-1)x mA relation coefficient, Delta, of the temperature compensation and the global temperature variation value of the wafer when the temperature compensation value is 1mx1The temperature at m points on the wafer changes when the compensation value is set for the thermometer.
Wherein the temperature compensation amount satisfies the formula:
in the formula, Offset(n-1)x1Temperature value to be compensated for the standardized rear thermometer, A(n-1)x mIs the temperatureA coefficient of relationship between the temperature compensation and the global temperature variation value of the wafer when the compensation value is 1, RSm×1The resistance data of the test wafer, target is the target resistance and sensitivity is the temperature sensitivity coefficient.
Has the advantages that: by collecting the parameter data of the resistance value, the film thickness and the like of the wafer and carrying out heat compensation on the wafer according to the parameter change of the wafer through the self-built global regulation model, the condition that different areas of the wafer are heated consistently and the electrical parameters of the semiconductor device are stable is ensured.
Drawings
FIG. 1 illustrates a global temperature variation process gain curve for a rapid thermal anneal wafer in a prior art process;
FIG. 2 is a flow chart of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
In a preferred embodiment, a method for establishing a global tuning model for optimizing rapid thermal annealing is provided, which is applied to thermal compensation of a wafer during annealing, and comprises the following steps:
step S1, performing a test, collecting and processing wafer test data, and establishing a global regulation model;
and step S2, calculating the required temperature compensation amount according to the global regulation model, and controlling the annealing temperature of the machine.
According to the technical scheme, the wafer is subjected to heat compensation according to the parameter change of the wafer through the self-established global regulation model by collecting the parameter data of the resistance value, the film thickness and the like of the wafer, so that the different areas of the wafer are heated consistently, and the electrical parameters of the semiconductor device are stable.
In a preferred embodiment, the wafer resistance temperature sensitivity is first measured; setting the operating temperature of the operating cavity to be 600 ℃, then carrying out three wafer tests at 590 ℃, 600 ℃ and 610 ℃ respectively, and measuring the average values of the resistance values of three wafers to be 158 omega, 127 omega and 98 omega respectively; the temperature sensitivity coefficient (sensitivity) of the wafer resistance value satisfies the formula:
in the formula, sensitivity is a temperature sensitive coefficient, R1 is an average resistance of the wafers tested in the first temperature test, R2 is an average resistance of the wafers tested in the second temperature test, and R3 is an average resistance of the wafers tested in the third temperature test.
In the technical scheme, the calculation result of the temperature sensitive coefficient is-3 omega/DEG C.
In a preferred embodiment, 4 wafers are used, 3 corresponding thermometers T1-T3 are placed at different positions of the process chamber, the compensation temperature of the thermometers is set to 3 ℃, 3 temperature compensation change tests are performed, the temperature of only one thermometer is changed at a time, and the temperature compensation of the other two thermometers is 0. The remaining 1 wafer was tested with temperature compensation of 0, and the resulting test data was used as baseline resistance data, with specific temperature settings as shown in table 1.
TABLE 1
In the technical scheme, the number of the wafers is not less than 4, noise interference can be eliminated by temperature compensation, and the value range can be 3-10 ℃.
In a preferred embodiment, the wafer surface is scanned transversely and longitudinally respectively, 13 data points are taken in each direction, and the data of the first transverse data point and the data of the first longitudinal data point are added and divided by 2 to obtain the resistance value data of the first point; and analogizing in sequence to obtain three groups of resistance data:
Rs1＝[130.7 127.6 126.1 137.9 124.5 112.9 139.4 112.9 124.5 137.9126.1 127.6 130.7]T
Rs2＝[129.9 132.4 128.3 124.7 133.5 130.7 128.8 130.7 133.5 124.7128.3 132.4 129.9]T
Rs3＝[130.3 129.2 128.9 133.1 128.5 124.9 133.4 124.9 128.5 133.1128.9 129.2 130.3]T
baseline resistance data for a compensated temperature of 0 are:
Rs0＝[130.1 130.0 130.3 130.7 130.5 130.9 130.4 130.9 130.5 130.7130.3 130.0 130.1]T
in the technical scheme, a plurality of data points are measured respectively in the transverse direction and the longitudinal direction, the number of the data points cannot be less than 13, and therefore bad points caused by measurement or problems of the wafer can be eliminated.
In a preferred embodiment, the baseline resistance data is subtracted from the three sets of resistance data, multiplied by a temperature sensitive coefficient, and then Offsetn-1＝[0 0 0 ···1]TFor the standard, the data obtained are normalized by Deltan-1＝[Delta1Delta2······Deltam]TThe test data are collated in a form to obtain the global temperature change values of the wafer when three groups of temperature compensation change are 1 ℃:
Delta1＝[-0.1 0.4 0.7 -1.2 1 3 -1.5 3 1 -1.2 0.7 0.4 -0.1]
Delta2＝[0.1 -1.2 1 3 -1.5 0.1 0.8 0.1 -1.5 3 1 -1.2 0.1]
Delta3＝[0.4 3 -1.5 -0.1 1 -0.1 0.6 -0.1 1 -0.1 -1.5 3 0.4]
in the technical scheme, the purpose of carrying out standardized processing on the data is to conveniently carry out global temperature adjustment on the wafer.
In a preferred embodiment, the temperature variation of 13 points on the wafer in 3 trials is plotted on the same coordinate system, resulting in a process gain curve (process gain curves) as shown in fig. 1.
In a preferred embodiment, the influence of the temperature change Delta at 13 points on the wafer on the thermometer offset is used as a linear relation to establish the equation:
Offset3x1＝A3x13*Delta13x1
in the formula, Offset3x1Temperature value to be compensated for thermometer, A3x 13A coefficient of relationship, Delta, between the temperature compensation and the global temperature variation value of the wafer when the temperature compensation value is 113x1When the compensation value is set for the thermometer, the temperature of 13 points on the wafer changes.
By substituting three sets of data, A can be calculated3x13。
In a preferred embodiment, a target resistance value is set for a wafer product, and the average value data of the resistance values of 13 data points in the transverse direction and the longitudinal direction is measured to obtain the temperature value to be compensated for by each thermometer. The temperature value required to be compensated by each thermometer meets the following conditions:
wherein, Offset3x1Temperature value to be compensated for thermometer, A3x 13A relation coefficient between the temperature compensation and the global temperature variation value of the wafer when the temperature compensation value is 1, RS13×1The average resistance value of 13 points in the longitudinal direction and the transverse direction of the test wafer is shown, target is a target resistance value, and sensitivity is a temperature sensitive coefficient.
In the above technical solution, by calculation, the following are obtained:
Offset3x1＝[0.8 0.4 -0.2]
then, the annealing temperature of the machine can be compensated according to the calculated temperature compensation amount.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (7)
1. A method for establishing a global regulation model to optimize rapid thermal annealing is applied to thermal compensation of a wafer during annealing, and is characterized by comprising the following steps:
step S1, performing a test, collecting and processing wafer test data, and establishing a global regulation model;
step S2, calculating the required temperature compensation amount according to the global regulation model, and controlling the annealing temperature of the machine;
the step S1 includes the steps of:
step S11, measuring the temperature sensitive coefficient of the wafer resistance;
step S12, providing n test wafers, and respectively placing n-1 corresponding thermometers in different areas of the working chamber, wherein n is at least 4;
s13, setting a temperature compensation value, using 1 test wafer each time, and performing n-1 temperature compensation tests;
step S14, setting the temperature compensation value to be 0, and testing the rest test wafers to be used as baseline resistance data;
step S15, collecting resistance value data of the wafer;
step S16, subtracting the baseline resistance data from the resistance data to obtain the variation value of the resistance of each area of the wafer after the temperature compensation setting of each thermometer;
step S17, dividing the variation value of the resistance value of each area of the wafer after the temperature compensation setting of each thermometer by the temperature sensitive coefficient to obtain the variation value of the temperature data
Step S18, standardizing the change value of the temperature data to obtain the global temperature change value of the wafer when the temperature compensation of the test wafer changes by 1 ℃;
and step S19, calculating a relation coefficient A between the temperature compensation and the global temperature change value of the wafer when the temperature compensation value is 1.
2. The method according to claim 1, wherein the temperature compensation value is in a range of 3-10 ℃.
3. The method of claim 1, wherein the step of collecting wafer test data is as follows:
s151, collecting transverse data by taking m data points in the transverse direction of the test wafer, wherein m is at least 13;
s152, collecting longitudinal data by taking m data points in the longitudinal direction of the test wafer;
step S153, adding each longitudinal data and the corresponding transverse data, and averaging to obtain resistance data of m test wafers, wherein m is at least 13.
4. The method of claim 1, wherein the temperature compensation test changes the amount of temperature compensation for only one thermometer at a time, the temperature compensation for the remaining n-2 thermometers being 0, and n being at least 4.
5. The method according to claim 1, wherein the determination method of step S11 is: adjusting the operation temperature of the operation cavity to three temperatures, respectively carrying out wafer tests at the three temperatures, obtaining and recording the average resistance of the wafer at the three temperatures, and calculating the temperature sensitivity coefficient according to the following formula:
in the formula, sensitivity is a temperature sensitive coefficient, R1 is an average resistance of the wafers tested in the first temperature test, R2 is an average resistance of the wafers tested in the second temperature test, and R3 is an average resistance of the wafers tested in the third temperature test.
6. The method according to claim 1, wherein the relation coefficient a is calculated by:
Offset(n-1)x1＝A(n-1)xm*Deltamx1，
in the formula, Offset(n-1)x1Temperature value to be compensated for the standardized rear thermometer, A(n-1)xmA relation coefficient, Delta, of the temperature compensation and the global temperature variation value of the wafer when the temperature compensation value is 1mx1The temperature at m points on the wafer changes when the compensation value is set for the thermometer.
7. The method of claim 1, wherein the temperature compensation amount satisfies the formula:
in the formula, Offset(n-1)x1Temperature value to be compensated for the standardized rear thermometer, A(n-1)xmA relation coefficient, RS, between the temperature compensation value and the global temperature variation value of the wafer when the temperature compensation value is 1m×1The resistance data of the test wafer, target is the target resistance and sensitivity is the temperature sensitivity coefficient.
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| TW421832B (en) * | 1999-09-23 | 2001-02-11 | Applied Materials Inc | Method for adjusting the temperature distribution on the wafer surface in a thermal treatment |
| JP2014150160A (en) * | 2013-02-01 | 2014-08-21 | Hitachi High-Technologies Corp | Plasma processing apparatus and sample table |
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| TW421832B (en) * | 1999-09-23 | 2001-02-11 | Applied Materials Inc | Method for adjusting the temperature distribution on the wafer surface in a thermal treatment |
| JP2014150160A (en) * | 2013-02-01 | 2014-08-21 | Hitachi High-Technologies Corp | Plasma processing apparatus and sample table |
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