CN107887397A - 用于薄膜晶体管的阵列基板及其显示装置 - Google Patents
用于薄膜晶体管的阵列基板及其显示装置 Download PDFInfo
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- CN107887397A CN107887397A CN201710889328.7A CN201710889328A CN107887397A CN 107887397 A CN107887397 A CN 107887397A CN 201710889328 A CN201710889328 A CN 201710889328A CN 107887397 A CN107887397 A CN 107887397A
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- NYBWUHOMYZZKOR-UHFFFAOYSA-N tes-adt Chemical compound C1=C2C(C#C[Si](CC)(CC)CC)=C(C=C3C(SC=C3)=C3)C3=C(C#C[Si](CC)(CC)CC)C2=CC2=C1SC=C2 NYBWUHOMYZZKOR-UHFFFAOYSA-N 0.000 description 1
- PFZLGKHSYILJTH-UHFFFAOYSA-N thieno[2,3-c]thiophene Chemical compound S1C=C2SC=CC2=C1 PFZLGKHSYILJTH-UHFFFAOYSA-N 0.000 description 1
- YODZTKMDCQEPHD-UHFFFAOYSA-N thiodiglycol Chemical compound OCCSCCO YODZTKMDCQEPHD-UHFFFAOYSA-N 0.000 description 1
- 229950006389 thiodiglycol Drugs 0.000 description 1
- 150000003577 thiophenes Chemical class 0.000 description 1
- RBNWAMSGVWEHFP-UHFFFAOYSA-N trans-p-Menthane-1,8-diol Chemical compound CC(C)(O)C1CCC(C)(O)CC1 RBNWAMSGVWEHFP-UHFFFAOYSA-N 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- ZIBGPFATKBEMQZ-UHFFFAOYSA-N triethylene glycol Chemical compound OCCOCCOCCO ZIBGPFATKBEMQZ-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/22—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
- H01L29/227—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds further characterised by the doping material
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
- H10K10/486—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising two or more active layers, e.g. forming pn heterojunctions
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- Thin Film Transistor (AREA)
Abstract
公开了用于薄膜晶体管的阵列基板及其显示装置。薄膜晶体管阵列基板包括:基板;位于所述基板上的栅极;包括第一有源层和第二有源层的有源层,所述第一有源层与所述栅极相对并且与所述栅极相邻并包括半导体材料和多个碳的同素异形体,所述第二有源层与所述第一有源层接触并包括半导体材料;位于所述栅极和所述有源层之间的栅极绝缘膜;以及分别与所述有源层接触的源极和漏极。
Description
技术领域
本发明涉及一种薄膜晶体管阵列基板及包括薄膜晶体管阵列基板的显示装置。
背景技术
近来,随着多媒体的发展,平板显示(FPD)装置的重要性日益增大。因此,诸如液晶显示(LCD)装置、等离子体显示面板(PDP)、场发射显示(FED)装置、有机发光显示(OLED)装置之类的各种显示器投入实际使用。
用于驱动显示装置的方法包括无源矩阵法和使用薄膜晶体管的有源矩阵法。在无源矩阵法中,阳极和阴极被形成为彼此正交,并且选择一行进行驱动;而在有源矩阵法中,将薄膜晶体管连接至每个像素电极以根据开/关切换来执行驱动。
由于薄膜晶体管的诸如电子迁移率和漏电流之类的基本特性、以及能够保持长寿命的耐久性和电可靠性,薄膜晶体管非常重要。特别是,薄膜晶体管的有源层可主要由非晶硅、多晶硅或氧化物半导体形成。尽管非晶硅在膜形成工艺简单以及生产成本低的方面有利,但是在电子迁移率低到0.5cm2/Vs的方面不利。氧化物半导体具有大约108的开/关比以及低漏电流,但是在具有比多晶硅低的10cm2/Vs的电子迁移率的方面不利。多晶硅具有大约100cm2/Vs的高电子迁移率,但是在与氧化物半导体相比具有低的开/关比并且将其应用于大面积将很昂贵的方面不利。因此,正在持续进行研究以改善薄膜晶体管的诸如电子迁移率、漏电流、开/关比等之类的特性。
发明内容
本发明提供一种薄膜晶体管阵列基板及包括薄膜晶体管阵列基板的显示装置,其能够通过形成包括碳的同素异形体(carbon allotrope)的有源层来改善元件特性。
在一个方面,提供了一种薄膜晶体管阵列基板,包括:基板;位于所述基板上的栅极;包括第一有源层和第二有源层的有源层,所述第一有源层与所述栅极相对并且与所述栅极相邻并包括半导体材料和多个碳的同素异形体,所述第二有源层与所述第一有源层接触并包括半导体材料;位于所述栅极和所述有源层之间的栅极绝缘膜;以及分别与所述有源层接触的源极和漏极。
在一个或多个实施方式中,所述第二有源层还包括多个碳的同素异形体,其中在所述第一有源层中的碳的同素异形体所占的含量比高于在所述第二有源层中的碳的同素异形体所占的含量比。
在一个或多个实施方式中,所述碳的同素异形体分散在所述半导体材料的内部。
在一个或多个实施方式中,在所述第一有源层中的碳的同素异形体的含量比随着远离所述栅极而降低。
在一个或多个实施方式中,所述第二有源层中的碳的同素异形体的含量比随着远离所述栅极而降低。
在一个或多个实施方式中,所述碳的同素异形体具有一维结构或二维结构。
在一个或多个实施方式中,所述碳的同素异形体是选自由还原的氧化石墨烯(rGO)、非氧化石墨烯、石墨烯纳米带、以及碳纳米管(CNT)组成的集合中的一种,或其混合物。
在一个或多个实施方式中,所述半导体材料是选自由陶瓷半导体、有机半导体、过渡金属硫族化合物和氧化半导体组成的集合中的一种,或其混合物。
在一个或多个实施方式中,基于100重量百分比的所述半导体材料的含量,所述第一有源层中的碳的同素异形体的含量是0.05重量百分比至1重量百分比。
在一个或多个实施方式中,基于100重量百分比的所述半导体材料的含量,所述第二有源层中的碳的同素异形体的含量是0.001重量百分比至0.01重量百分比。
在一个或多个实施方式中,所述第一有源层和所述第二有源层的厚度分别在1nm至10nm的范围内。
在另一个方面,提供一种显示装置,包括:基板;位于所述基板上的栅极;包括第一有源层和第二有源层的有源层,所述第一有源层与所述栅极相对并且与所述栅极相邻并包括半导体材料和多个碳的同素异形体,所述第二有源层与所述第一有源层接触并包括半导体材料;位于所述栅极和所述有源层之间的栅极绝缘膜;分别与所述有源层接触的源极和漏极;位于所述源极和所述漏极上的有机绝缘膜;以及位于所述有机绝缘膜上的像素电极。
在一个或多个实施方式中,所述第二有源层还包括多个碳的同素异形体,其中在所述第一有源层中的碳的同素异形体所占的含量比高于在所述第二有源层中的碳的同素异形体所占的含量比。
在一个或多个实施方式中,所述碳的同素异形体分散在所述半导体材料的内部。
在一个或多个实施方式中,在所述第一有源层中的碳的同素异形体的含量比随着远离所述栅极而降低。
在一个或多个实施方式中,所述第二有源层中的碳的同素异形体的含量比随着远离所述栅极而降低。
在一个或多个实施方式中,所述碳的同素异形体具有一维结构或二维结构。
在一个或多个实施方式中,所述碳的同素异形体是选自由还原的氧化石墨烯(rGO)、非氧化石墨烯、石墨烯纳米带、以及碳纳米管(CNT)组成的集合中的一种,或其混合物。
在一个或多个实施方式中,所述半导体材料是选自由陶瓷半导体、有机半导体、过渡金属硫族化合物和氧化半导体组成的集合中的一种,或其混合物。
在一个或多个实施方式中,基于100重量百分比的所述半导体材料的含量,所述第一有源层中的碳的同素异形体的含量是0.05重量百分比至1重量百分比。
在一个或多个实施方式中,基于100重量百分比的所述半导体材料的含量,所述第二有源层中的碳的同素异形体的含量是0.001重量百分比至0.01重量百分比。
在一个或多个实施方式中,所述第一有源层和所述第二有源层的厚度分别在1nm至10nm的范围内。
在一个或多个实施方式中,所述显示装置还包括:电连接至所述像素电极的有机发光二极管;位于所述有机发光二极管上的封装层;以及位于所述封装层上的盖窗。
在一个或多个实施方式中,所述显示装置还包括:公共电极,所述公共电极被设置为与位于相同平面上的像素电极间隔开或者位于所述像素电极的下部;以及设置在所述公共电极上的液晶层。
附图说明
给本发明提供进一步理解并且并入本申请构成本申请一部分的附图图解了本发明的实施方式,并与说明书一起用于解释本发明的原理。在附图中:
图1和2示出用于例示本发明的碳的同素异形体-半导体组合物(composition)的制备工艺的示意图。
图3示出根据本发明示例性实施方式的薄膜晶体管阵列基板的剖视图。
图4和5示出用于例示根据本发明示例性实施方式的有源层的剖视图。
图6至8示出用于例示根据本发明示例性实施方式的薄膜晶体管阵列基板的各种结构的剖视图。
图9和10示出用于例示根据本发明示例性实施方式的显示装置的剖视图。
图11示出用于例示仅由半导体材料形成的有源层的拉曼光谱分析结果的曲线图。
图12示出用于例示混合有半导体材料和碳的同素异形体的有源层的拉曼光谱分析结果的曲线图。
图13示出用于例示根据比较例1、2与实施方式制造的薄膜晶体管的电流-电压曲线的曲线图。
图14示出用于例示SQRT-电压(其表示图13的漏极电流的平方根值)的曲线图。
具体实施方式
下文中,将参照例示附图详细描述本发明的示例性实施方式。在向附图的组成元件添加参考标记时,应当注意,在通篇说明书中,相同的组成元件即使被显示在不同的图中也尽可能地由相同的参考符号表示,相似的参考标记基本表示相似的组件。此外,在解释本发明的示例性实施方式时,如果确定对本发明相关的已知功能或构造的详细描述可能使本发明的主旨模糊不清,将省略其详细描述。
在解释本发明的组成要素时,可使用诸如第一、第二、A、B、(a)、(b)之类的术语。这些术语旨在将组成要素彼此区分开,组成要素的性质、等级、次序等不受这些术语的限制。当一个组成要素被描述为与另一个组成要素“链接”、“耦接”或“连接时”,可以理解为,这个组成要素与不同的组成要素直接链接、耦接或链接;但是也可以理解为,在这个组成要素和另一组成要素之间链接、耦接或连接有不同的组成要素。在相同的语境下,当一组成元件被描述为位于不同组成元件“上”或“下”时,可以理解为包括这个组成元件直接形成在不同组成元件上的情形、以及通过将另一不同组成元件插入到这个不同组成元件而间接形成在这个不同组成元件上的情形。
根据如下描述的本发明的显示装置可以是有机发光显示装置、液晶显示装置、电泳显示装置等。在本发明中,描述液晶显示装置作为示例性实施方式。液晶显示装置由薄膜晶体管阵列基板(其中像素电极和公共电极形成在薄膜晶体管上)、滤色器基板以及插置在两个基板之间的液晶层组成。在这种液晶显示装置中,通过垂直地或水平地施加至公共电极和像素电极的电场来驱动液晶。根据本发明的显示装置也可用在有机发光显示装置中。例如,有机发光显示装置包括第一电极、连接至薄膜晶体管的第二电极、以及插入在第一电极和第二电极之间的由有机材料形成的发光层。因此,从第一电极提供的空穴和从第二电极提供的电子在发光层中组合以形成激子(即,电子空穴对),激子通过在返回到基态时产生的能量而发光。包含如下描述的本发明的碳的同素异形体的有源层可用在上述显示装置的薄膜晶体管中。
下文中,将参照附图描述本发明的示例性实施方式。
本发明公开了一种包含碳的同素异形体以及半导体材料的薄膜晶体管,特别地,公开了一种薄膜晶体管,其中形成有包含碳的同素异形体以及半导体材料的有源层。薄膜晶体管用作显示装置的开关元件或驱动元件。
<碳的同素异形体>
本发明公开的碳的同素异形体表示碳原子共价地彼此键合的多环芳烃分子。共价地键合的碳原子可形成6元环作为重复单元;附加地,共价地键合的碳原子还可包括从5元环和7元环选出的至少之一。碳的同素异形体可以是单层,或者可包括叠置在碳的同素异形体的不同层上的多个碳的同素异形体层。碳的同素异形体可具有一维或二维结构。碳的同素异形体具有大约100nm,特别地从大约10nm至大约90nm,更特别地从大约20nm至大约80nm的最大厚度。
碳的同素异形体主要可通过四种不同方法,比如物理剥落(exfoliation)、化学气相沉积、化学剥落和外延生长来制造。物理剥落是将透明胶带(scotch tape)贴附到石墨样品然后去除透明胶带从而在透明胶带的表面上获得从石墨脱离的碳的同素异形体片的方法。化学气相沉积是通过在基板表面上,以高动能吸收/分解气体或水汽形式的碳前体来生长碳的结晶同素异形体(其中碳的结晶同素异形体旨在被生长为分离碳原子并且建立相应碳原子之间的原子键的形成)的方法。化学剥落利用石墨的氧化还原特性,将石墨添加到硫酸和硝酸的混合物中,将羧基化合物贴附到碳的同素异形体板的边缘。通过氯化亚砜将生成物转换成氯化酰基,然后再使用十八胺形成为碳的同素异形体酰胺。当采用诸如四氢呋喃之类的溶液来恢复碳的同素异形体酰胺时,出现了粉化并获得单独的碳的同素异形体片。外延生长是通过在1500℃的高温加热金刚砂(SiC)来获得碳的同素异形体的方法,由此去除硅(Si)并通过剩余的碳来获得碳的同素异形体。
在本发明中使用的碳的同素异形体可包含还原的氧化石墨烯(rGO)、非氧化石墨烯、石墨烯纳米带、碳纳米管(CNT)等。还原的氧化石墨烯(GO)是氧化石墨烯的还原形式,可通过还原氧化石墨烯来制备还原的氧化石墨烯,氧化石墨烯是通过将强酸添加到石墨中以使其氧化并且化学形成为小颗粒来制备的。非氧化石墨烯是指通过上述制备碳的同素异形体的方法之中的一种方法,而不是氧化还原工艺,来制备的碳的同素异形体。石墨烯纳米带是通过切割具有纳米宽度的带形式的石墨烯来制备的,并且根据其宽度具有恒定的能带隙。石墨烯纳米带可从包含碳的同素异形体的单体合成,或者通过切割碳纳米管并将其扩展到平面中来合成。除了上述类型的碳的同素异形体之外,诸如石墨烯纳米网(graphenenanomesh)等之类的已知碳的同素异形体结构也可用于本发明的碳的同素异形体。
本发明的碳的同素异形体以薄片(flake)的形式使用。可通过在基板上涂覆分散物(其中碳的同素异形体分散在溶剂中)、干燥溶剂并且对其施加物理力来制备碳的同素异形体薄片。作为施加物理力的方法,可通过诸如球磨机、砂磨机、超声波均质机和搅拌(stirring)之类的方法来获得碳的同素异形体薄片。
<半导体材料>
本发明的半导体材料可以是可被溶液涂覆的陶瓷半导体、有机半导体、过渡金属硫族化合物或氧化半导体。
陶瓷半导体利用陶瓷的电特性。由于陶瓷是束缚到某些离子或原子,因此它们不能自由移动,因而很难被电气化。但是,当从外部施加电场时,电子能够响应于状态变化,由于束缚电子的重新排列而移动。陶瓷半导体由通过在诸如硅(Si)、锗(Ge)、硒(Se)、铝(Al)、钛(Ti)、锆(Zr)等之类的金属元素与氧(O)、碳(C)、氮(N)等之间的束缚(binding)而制备的氧化物、碳化物和氮化物组成。典型的陶瓷半导体可包括钛酸钡(BaTiO3)。
氧化物半导体是具有半导体特性的有机化合物,并且可包括聚合有机半导体或低分子有机半导体。聚合有机半导体的例子可包括聚[(9,9-二辛基芴-2,7-二基)-共-并噻吩](F8T2)、聚[(5,6-二氢-5-辛基-4,6-二氧-4H-噻吩并[3,4-C]吡咯-1,3-二基){4,8-双[(2-丁辛基)氧]苯并[1,2-b:4,5-b′]二噻吩-2,6-二基}](PBDTBOTPDO)、聚[[5-(2-乙基己基)-5,6-二氢-4,6-二氧-4H-噻吩并[3,4-c]吡咯-1,3-二基][4,8-双[(2-乙基己基)氧]苯并[1,2-b:4,5-b′]二噻吩-2,6-二基]](PBDT-TPD)、聚[1-(6-{4,8-双[(2-乙基己基)氧]-6-甲基苯并[1,2-b:4,5-b′]二噻吩-2-基}-3-氟代-4-甲基噻吩并[3,4-b]噻吩-2-基)-1-辛酮](PBDTTT-CF)、聚[N-9′-正辛基-2,7-咔唑-alt-5,5-(4′,7′-二-2-噻吩基-2′,1′,3′-苯并噻二唑)](PCDTBT)、聚[[9-(1-辛基壬基)-9H-咔唑-2,7-二基]-2,5-噻吩二基-2,1,3-苯并噻二唑-4,7-二基-2,5-噻吩二基]、聚[2,6-(4,4-双-(2-乙基己基)-4H-环戊二烯[2,1-b;3,4-b′]二噻吩)-alt-4,7(2,1,3-苯并噻二唑)](PCPDTBT)、聚[2,7-(9,9-二辛基芴)-alt-4,7-双(噻吩-2-基)苯并-2,1,3-噻重氮](PFO-DBT)、聚[双(4-苯基)(2,4,6-苯基三甲基)胺](PTAA)、聚[(5,6-二氢-5-辛基-4,6-二氧-4H-噻吩并[3,4-c]吡咯-1,3-二基)[4,8-双[(2-乙基己基)氧]苯并[1,2-b:4,5-b′]二噻吩-2,6-二基]]、聚[(9,9-二-正辛基芴-2,7-二基)-alt-(苯并[2,1,3]噻二唑-4,8-二基)](F8BT)、聚(3-十二烷基噻吩-2,5-二基)(P3DDT)、聚(3-己基噻吩-2,5-二基)(P3HT)、聚[2-甲氧基-5-(3′,7′-二甲基辛氧基)-1,4-对苯乙炔](MDMOPPV)、聚[2-甲氧基-5-(2-乙基己基氧)-1,4-对苯乙炔](MEH-PPV)、聚(3-辛基噻吩-2,5-二基)(P3OT)、以及聚({4,8-双[(2-乙基己基)氧]苯并[1,2-b:4,5-b′]二噻吩-2,6-二基}{3-氟代-2-[(2-乙基己基)碳酰基]噻吩并[3,4-b]噻吩二基})(PTB7)等。
低分子有机半导体例如可包括6,13-双(三异丙基甲硅烷基乙炔基)并五苯(TIPS-并五苯)、6,13-双((三乙基硅基)乙炔基)并五苯(TES并五苯)、5,5′-双(7-己基-9H-芴-2-基)-2,2′-二噻吩(DH-FTTF)、2,8-二氟-5,11-双(三乙基硅基乙炔基)噻吩蒽(二F-TES-ADT)、5,5′-十二烷-2,2′-二噻吩(DH2T),3,3″′-十二烷-2,2′:5′,2″:5″,2″′-四噻吩(DH4T)、5,5″″′-十二烷-2,2′:5′,2″:5″,2″′:5″′,2″″:5″″,2″″′-六噻吩(DH6T)、2(4,4′-[4,4-双(2-乙基己基)-4H-硅杂环戊二烯并[3,2-b:4,5-b′]二噻吩-2,6-二基]双[7-(5′-己基-[2,2′-二噻吩]-5-基)-[1,2,5]噻二唑并[3,4-c]吡啶](DTS(PTTh2)))、5,5′-双{[4-(7-己基噻吩-2-基)噻吩-2-基]-[1,2,5]噻二唑并[3,4-c]吡啶}-3,3′-二-2-(乙基己基亚甲硅基-2,2′-二噻吩)、2,5-二-(2-乙基己基)-3,6-双-(5″-正己基-[2,2′,5′,2″]三联噻吩-5-基)-吡咯并[3,4-c]吡咯-1,4-二酮(SMDPPEH)、5,11-双(三乙基硅基乙炔基)噻吩蒽(TES-ADT)等。
作为上述有机半导体,可采用选自聚合有机半导体和低分子有机半导体的至少两种,或者可采用相互不同的聚合有机半导体,或者可采用相互不同的低分子有机半导体。
过渡金属硫族化合物是具有半导体特性的材料,并且可包括过渡金属硫化物、过渡金属硒化物、过渡金属碲化物等。作为过渡金属硫族化合物,例如可采用SnSe2,CdSe,ZnSe,ZnTe,MoS2,MoSe2,MoTe2,WS2,WSe2,WTe2等。
氧化半导体是具有半导体特性的材料,并且可以是包含诸如镓(Ga)、铟(In)、锌(Zn)、锡(Sn)、硅(Si)、锆(Zr)等之类的金属的氧化物。要采用的氧化半导体的例子可包括IGZO,In2O3,ZnO,IZO,IGO等,但不限于此,可采用已知材料。
碳的同素异形体-半导体组合物
图1和2示出用于例示本发明的碳的同素异形体-半导体组合物的制备工艺的示意图。
本发明可通过混合碳的同素异形体和半导体材料来制备碳的同素异形体-半导体组合物。更具体地,参照图1,制备碳的同素异形体薄片和半导体材料。可以以粉末的形式制备碳的同素异形体薄片和半导体材料。碳的同素异形体薄片和半导体材料在添加到溶剂之后混合,以生成碳的同素异形体-半导体组合物。与前述不同,参照图2,本发明的碳的同素异形体-半导体组合物可通过混合碳的同素异形体分散物来制备,在分散物中,碳的同素异形体分散在包含半导体材料的半导体溶液中。
尤其是,要采用的溶剂可以选自由水;选自乙醇,甲醇,异丙醇,丁醇,2-乙基己基醇,甲氧戊醇,丁氧基乙醇,乙氧基乙氧基乙醇,丁氧基乙氧基乙醇,甲氧丙氧基丙醇,酯醇,松油醇,及其组合物的醇;四氢呋喃(THF);甘油,乙二醇,三甘醇,聚乙二醇,丙二醇,二丙二醇,二己二醇,或其烷基醚;丙三醇,N-甲基-2-吡咯酮(NMP),2-吡咯烷酮,乙酰丙酮,1,3-二甲基咪唑啉酮,硫二甘醇,二甲亚砜(DMSO),N,N-二甲替乙酰胺(DMAc),二甲基甲酰胺(DMF),环丁砜,二乙醇氨,三乙醇胺及其组合物组成的集合的至少之一。
为了碳的同素异形体的良好分散,可添加其它添加剂或者可对其辐射超声波。当用超声波来辐照碳的同素异形体-半导体组合物时,优选以某一间隔几次辐射超声波。例如,碳的同素异形体和半导体材料混合,并且利用超声波粉碎机用强超声波(大约250W)辐照大约30分钟。通过重复这种处理,能够制备碳的同素异形体得到良好分散的碳的同素异形体-半导体组合物。
在本发明的碳的同素异形体-半导体组合物中要使用的碳的同素异形体可基于100重量百分比的半导体材料固体而具有介于0.001重量百分比和1重量百分比之间的含量。尤其是,当碳的同素异形体的含量基于100重量百分比的半导体材料固体等于或大于0.001重量百分比时,能够改善电荷迁移率;而当碳的同素异形体的含量基于100重量百分比的半导体材料固体等于或小于1重量百分比时,能够呈现防止开关比下降的效果。
下文中,将描述包括采用上述碳的同素异形体-半导体组合物的有源层的薄膜晶体管及其显示装置。
图3示出根据本发明示例性实施方式的薄膜晶体管阵列基板的剖视图;图4和5示出用于例示根据本发明示例性实施方式的有源层的剖视图;图6至8示出用于例示根据本发明示例性实施方式的薄膜晶体管阵列基板的各种结构的剖视图。
<薄膜晶体管阵列基板>
采用底栅型薄膜晶体管(其中栅极设置在有源层下方)作为示例性实施方式来解释本发明公开的薄膜晶体管阵列基板。
参照图3,在基板110上设置栅极120。基板110由透明或不透明玻璃、塑料或金属形成。栅极120可由从由铜(Cu)、钼(Mo)、铝(Al)、铬(Cr)、金(Au)、钛(Ti)、镍(Ni)、钕(Nd)、钽(Ta)和钨(W)组成的集合选出的任一种或其合金的单层或多层形成。栅极绝缘膜130设置在栅极120上以将栅极120绝缘。栅极绝缘膜130由硅氧化物膜(SiOx)、硅氮化物膜(SiNx)或其多层形成。
有源层140设置在栅极绝缘膜130上。有源层140由本发明的碳的同素异形体-半导体组合物形成。本发明的有源层140包括第一有源层142和第二有源层146。第一有源层142与栅极120相邻设置,第二有源层146设置为远离栅极120,且在第二有源层146和栅极120之间具有第一有源层142。第一有源层142形成有源层140的下部,第二有源层146形成在第一有源层142的顶部上并且形成有源层140的上部。
第一有源层142是形成了有源层沟道的层,并且包括半导体材料和多个碳的同素异形体。在第一有源层142中,半导体材料通过允许第一有源层142用作半导体来控制阈值电压。在第一有源层142中,多个碳的同素异形体通过允许载流子经过碳的同素异形体快速移动来加速电子迁移率。第一有源层142的大部分由半导体材料形成,碳的同素异形体分散在半导体材料中。特别是,由于碳的同素异形体分散在第一有源层142中,电子和空穴初始根据半导体材料中的半导体材料的电荷迁移率而移动,然后在与导体邻近设置的碳的同素异形体中非常快速地移动。电子和空穴能够与半导体和碳的同素异形体一起移动,由此显著提高电荷迁移率。
第二有源层146是具有向第一有源层142的沟道提供载流子的作用的层,并且可仅由半导体材料形成或者通过包括分散在半导体材料中的多个碳的同素异形体而形成。在第二有源层146中,半导体材料允许第二有源层146用作半导体。当第二有源层146包含多个碳的同素异形体时,多个碳的同素异形体允许载流子经由碳的同素异形体快速移动,由此加速电子迁移率。
参照图4,在第一有源层142中的碳的同素异形体所占的含量比可高于在第二有源层146中的碳的同素异形体所占的含量。例如,当第一有源层142和第二有源层146的每一个的半导体固体含量是100g时,第一有源层142的碳的同素异形体可形成为具有0.1g的含量,第二有源层146的碳的同素异形体可形成为具有0.01g的含量。相对较高的碳的同素异形体含量意味着碳的同素异形体的特性是用作导体。因此,通过增大形成有沟道的第一有源层142的碳的同素异形体的含量比,能够加速经由沟道移动的载流子迁移率。因此,具有能够改善有源层140的电子迁移率的优点。即使在第二有源层146的碳的同素异形体的含量比被形成为相对小于第一有源层142的碳的同素异形体的含量比时,在第二有源层146中也基本不形成沟道,因而第二有源层146可有助于在不显著影响电子迁移率的情形下向第一有源层142提供载流子。
基于100重量百分比的半导体材料的含量,第一有源层142中的碳的同素异形体的含量是0.05重量百分比至1重量百分比。尤其是,当碳的同素异形体的含量基于100重量百分比的半导体材料的含量等于或大于0.05重量百分比时,可改善有源层的电子迁移率,而当碳的同素异形体的含量基于100重量百分比的半导体材料的含量等于或小于1重量百分比时,能够防止晶体管的阈值电压在负(-)方向上移动。
碳的同素异形体可不包含在第二有源层146中,但是当碳的同素异形体包含在第二有源层146中时,第二有源层146中的碳的同素异形体的含量基于100重量百分比的半导体材料的含量是0.001重量百分比至0.01重量百分比。尤其是,当碳的同素异形体的含量基于100重量百分比的半导体材料含量等于或大于0.001重量百分比时,可改善有源层的电子迁移率;而当碳的同素异形体的含量基于100重量百分比的半导体材料含量等于或小于0.01重量百分比时,能够防止晶体管的阈值电压在负(-)方向上移动。作为参考,半导体材料的100重量百分比表示半导体材料固体的100重量百分比,碳的同素异形体的含量是指碳的同素异形体固体相对于100重量百分比的半导体材料固体的重量百分比。
第一有源层142可具有1nm至10nm的厚度。当第一有源层142的厚度等于或大于1nm时,能够防止沟道形成为具有较小厚度;而当第一有源层142的厚度等于或小于10nm时,能够防止有源层变厚。第二有源层146可具有1nm至10nm的厚度。当第二有源层146的厚度等于或大于1nm时,会易于向沟道提供载流子;而当第二有源层146的厚度等于或小于10nm时,能够防止有源层变厚。
同时,包含在第一有源层142或第二有源层146中的碳的同素异形体的含量比可形成斜度。
参照图3和5,当碳的同素异形体包含在第一有源层142和第二有源层146中时,第一有源层142和第二有源层146的含量比可随着第一有源层142和第二有源层146的碳的同素异形体变得远离栅极120而减小。由于第一有源层142邻近栅极120设置,所以在邻近于栅极120的区域中的第一有源层142中形成沟道。因此,通过使得碳的同素异形体的含量比在第一有源层142的沟道区域中最高,能够改善有源层的电子迁移率。此外,碳的同素异形体的含量比从第一有源层142向第二有源层146(此方向是逐渐远离栅极120的方向)逐渐减小。碳的同素异形体的电子迁移率提高特性能够在沟道区域中呈现最大效果,并且用于在除了沟道区域之外的区域中提供载流子。因此,碳的同素异形体的含量比在有源层140的沟道区域中最高,并且随着远离沟道区域而逐渐减小。
通过在上面形成有栅极绝缘膜130的基板110上涂覆上述碳的同素异形体-半导体组合物两次,形成上述有源层140,从而包括第一有源层142和第二有源层146。用于涂覆碳的同素异形体-半导体组合物的示例性方法可包括旋涂、狭缝涂覆、丝网印刷、喷墨印刷等,并且只要涉及涂覆溶液,任何方法都可使用。通过在250℃加热碳的同素异形体-半导体薄膜2小时,去除溶剂。然后,通过经由光刻方法将碳的同素异形体-半导体薄膜图案化,可制备本发明的有源层140。
与有源层140的一侧进行接触的源极150a和与有源层140的另一侧进行接触的漏极150b设置在有源层140上。源极150a和漏极150b可由单层或多层形成。当源极150a和漏极150b由单层形成时,其可由选自由钼(Mo)、铝(Al)、铬(Cr)、金(Au)、钛(Ti)、镍(Ni)、钕(Nd)、和铜(Cu)组成的集合的任一种或其合金形成。此外,当源极150a和漏极150b由多层形成时,其可由钼/铝钕、钼/铝、或钛/铝的双层,或者钼/铝钕/钼、钼/铝/钼、或钛/铝/钛的三层形成。
在本发明的上述有源层140中,当通过在半导体材料中分散碳的同素异形体而将电压施加至源极150a和漏极150b时,电子和空穴移动到有源层140的空穴。尤其是,由于碳的同素异形体分散在有源层140的沟道中,电子和空穴根据半导体材料中的半导体材料的电荷迁移率而移动,并且在与导体邻近设置的碳的同素异形体中非常快速地移动。由于电子和空穴与半导体和碳的同素异形体一起移动,能够显著改善电荷迁移率。尤其是,当半导体材料具有电子迁移率由于扩散(scattering)(这是在电子移动期间发生的现象)而降低的特性时,扩散在碳的同素异形体内部几乎不发生,因而能够消除电子迁移率降低的风险。
此外,由于本发明的有源层140包含小量的碳的同素异形体,所以几乎不会通过碳的同素异形体之间的接触部(或化学键合)而形成载流子移动的路径。因此,能够防止由于有源层140的半导体特性的劣化而导致的截止电流(OFF current)的增大。
同时,本发明的薄膜晶体管阵列基板可具有关于薄膜晶体管的各种结构。
参照图6,本发明的薄膜晶体管阵列基板被形成为具有底栅型结构,其中源极150a和漏极150b可设置在有源层140和栅极绝缘膜130之间。更具体地,栅极120设置在基板110上并且栅极绝缘膜130设置在栅极120上。彼此间隔开的源极150a和漏极150b可设置在栅极绝缘膜130上,并且有源层140可设置为与栅极绝缘膜130上的源极150a和漏极150b进行接触。尤其是,有源层140可布置成,使得第一有源层142与栅极120邻近设置,而第二有源层146远离栅极120。因此,允许在具有高含量比的碳的同素异形体的第一有源层142中形成沟道。
此外,参照图7,由顶栅结构形成的本发明的薄膜晶体管阵列基板的特性在于,栅极120、源极150a和漏极150b可设置在栅极绝缘膜130上。更具体地,有源层140设置在基板110上,栅极绝缘膜130设置在有源层140上。彼此间隔开的源极150a和漏极150b可设置在栅极绝缘膜130上并且与有源层140接触,栅极120可插置在源极150a和漏极150b之间。尤其是,有源层140可布置成,使得第一有源层142与栅极邻近设置,而第二有源层146设置为远离栅极120。因此,沟道被布置成形成在具有高含量比的碳的同素异形体的第一有源层142上。
此外,参照图8,由顶栅结构形成的本发明的薄膜晶体管阵列基板的特性在于,源极150a和漏极150b可设置在有源层140的下面。更具体地,彼此间隔开的源极150a和漏极150b可设置在基板110上,有源层140可设置为分别与基板110上的源极150a和漏极150b接触。栅极绝缘膜130可设置在有源层140上,栅极120可设置在栅极绝缘膜130上。尤其是,有源层140可布置成,使得第一有源层142邻近栅极120设置,第二有源层146设置为与栅极120间隔开。因此,沟道被布置成形成在具有高含量比的碳的同素异形体的第一有源层142上。
下文中,将参照图9和10描述包括本发明的薄膜晶体管阵列基板的显示装置。下面将描述包括根据第一实施方式的薄膜晶体管阵列基板的显示装置,并将省略任何重复描述。图9示出用于例示根据本发明示例性实施方式的液晶显示装置的剖视图,图10示出用于例示根据本发明示例性实施方式的有机发光显示装置的剖视图。
<显示装置>
参照图9,有机绝缘膜160设置在源极150a和漏极150b上。有机绝缘膜160用于将其下方的不规则部平坦化,并且可由诸如光学压克力(photoacryl)、聚酰亚胺、苯并环丁烯树脂、丙烯酸酯树脂等之类的有机材料形成。有机绝缘膜160包括暴露漏极150b的通孔165。尽管未图示,可在源极150a和漏极150b上设置由硅氧化物膜(SiOx)、硅氮化物膜(SiNx)或其多层形成的钝化膜。
像素电极170和公共电极180设置在有机绝缘膜160上。像素电极170通过形成在有机绝缘膜160上的通孔165连接至漏极150b。像素电极160由诸如氧化铟锡(ITO)和氧化铟锌(IZO)之类的透明导电材料形成。公共电极180由与像素电极170相同的材料形成。像素电极170和公共电极180交替布置,并且在像素电极170和公共电极180之间形成水平电场,由此驱动设置在像素电极170和公共电极180上的液晶层。
已经针对面内切换(IPS)液晶显示器(其中像素电极和公共电极设置在相同平面上)描述了本发明的示例性实施方式。但是,本发明不限于此,而是可在像素电极下面设置公共电极,或者公共电极可设置在与薄膜晶体管阵列基板相对的滤色器阵列基板上。
同时,参照图10,本发明的显示装置可以是包括有机发光二极管的有机发光显示器。更具体地,有机绝缘膜160位于源极150a和漏极150b上。有机绝缘膜160包括用于暴露漏极150b的通孔165。
像素电极170设置在有机绝缘膜160上。像素电极170通过有机绝缘膜160上的通孔165连接至漏极150b。堤层175设置在像素电极170上。堤层175可以是通过暴露像素电极170的一部分来限定像素的像素限定层。有机层190设置在堤层175和暴露的像素电极170上。有机层190包括通过电子和空穴的束缚来发光的发光层,并且可包括空穴注入层、空穴传输层、电子传输层或电子注入层。对置电极200设置在上面形成有机层190的基板110上。对置电极200是阴极,并且可由具有低功函数的镁(Mg)、钙(Ca)、铝(Al)、银(Ag)或其合金形成。因此,形成包括像素电极170、有机层190和对置电极200的有机发光二极管OLED。
封装层210设置在上面形成有机发光二极管OLED的基板110上。封装层210封装包括下面的有机发光二极管OLED的基板110,并且可由无机膜、有机膜或其多层结构组成。盖窗220设置在封装层210上,形成有机发光显示装置。
下文中,将描述关于根据本发明实施方式的包括碳的同素异形体和半导体材料的有源层的实验例。下面的实验例仅是本发明的示例性实施方式,本发明不限于此。
实验例1:有源层组合物的分析
将仅由半导体材料组成的有源层的组合物、以及混合了半导体材料和碳的同素异形体的有源层的组合物经受拉曼光谱分析。尤其是,石墨烯用作碳的同素异形体,并且相对于100重量百分比的半导体材料固体,混合0.1重量百分比的石墨烯。图11示出用于例示仅由半导体材料形成的有源层的拉曼光谱分析结果的曲线图,图12示出用于例示混合有半导体材料和碳的同素异形体的有源层的拉曼光谱分析结果的曲线图。
参照图11,仅由半导体材料组成的有源层的拉曼光谱分析结果仅仅显示出其中形成了有源层的基板的峰值。
同时,参照图12,混合了半导体材料和石墨烯的有源层的拉曼光谱分析结果显示出:除了基板峰值之外,在存在碳的同素异形体的条件下还具有G、D、2D峰值。通常,当在薄膜中存在石墨烯或碳纳米管时,G峰值、D峰值和2D峰值出现在拉曼光谱分析中。尤其是,G峰值的位置是1580cm-1,D峰值的位置是1340cm-1,2D峰值的位置是2700cm-1。G峰值称作在石墨烯的“g”之后的G峰值,是在石墨烯材料中共同发现的峰值;D峰值是由于晶体中的缺陷导致的峰值,是与石墨烯或碳纳米管的缺陷有关的峰值。由于2D峰值在具有1350cm-1能量的声子带来的非弹性扩散连续出现两次时发生,所以2D峰值出现在2700cm-1周围。通常,在单层石墨烯中,2D峰值高于G峰值;而在多层石墨烯中,2D峰值低于G峰值。在D峰值中,随着出现在石墨烯或碳纳米管中的缺陷数量的增大,峰值增大。因此,基于G、D和2D峰值的出现的拉曼光谱分析结果确认了碳的同素异形体的存在。
实验例2:薄膜晶体管的评估
<比较例1>
如图3所示,通过涂覆纯有源IGZO来形成有源层,制备底栅型薄膜晶体管。
<比较例2>
除了通过相对于100重量百分比的IGZO固体,将0.1重量百分比的石墨烯粉末与IGZO溶液混合来形成有源层之外,在与上述比较例1相同的工艺条件下制造薄膜晶体管。
<实施方式>
除了通过相对于100重量百分比的IGZO固体,将0.1重量百分比的石墨烯粉末与IGZO溶液混合来形成第一有源层并且通过在第一有源层上涂覆纯IGZO来形成第二有源层之外,在与上述比较例1相同的工艺条件下制造薄膜晶体管。
根据比较例1、比较例2和实施方式制造的薄膜晶体管的电流-电压曲线被测量,并显示在图13中;表示图13的漏极电流的平方根值的SQRT-电压被测量,并显示在图14中。阈值电压和电子迁移率如下面的表1所示。
[表1]
参照图13、图14和表1,在设置有仅由IGZO形成的有源层的比较例1中,阈值电压显示为-6±0.5V,电子迁移率显示为3.6±0.7cm2/Vs。在设置有混合了IGZO和石墨烯的单层有源层的比较例2中,阈值电压显示为-14±2V,电子迁移率显示为14.5±0.9cm2/Vs。在堆叠混合了IGZO和石墨烯的第一有源层以及仅由IGZO组成的第二有源层的实施方式中,阈值电压显示为-7±0.5V,电子迁移率显示为7.8±0.4cm2/Vs。
概括来说,在设置有仅由IGZO形成的有源层的比较例1中,阈值电压特性良好,但是电子迁移率低。此外,在设置有混合了IGZO和石墨烯的单层有源层的比较例2中,电子迁移率高但是阈值电压在负(-)方向上移动因而特性较差。同时,在堆叠混合了IGZO和石墨烯的第一有源层以及仅由IGZO组成的第二有源层的实施方式中,阈值电压相比比较例2而言较高,电子迁移率相比比较例1而言也较高。
因此,通过形成具有双层结构(包括半导体材料和碳的同素异形体)的有源层并使得多个碳的同素异形体包括在形成有沟道的第一有源层上,本发明具有能够改善薄膜晶体管的电子迁移率的优点。此外,通过形成相比第一有源层包括较小量的碳的同素异形体的第二有源层,本发明具有能够改善阈值电压特性的优点。
尽管已经参考多个示例性实施方式描述了实施方式,但应当理解,所属领域的普通技术人员能够设计出将落入本发明的原理范围内的大量其他修改和实施方式。更具体地,在本发明的说明书、附图和所附权利要求书的范围内的主题组合布置的组成部分和/或配置中,各种变化和修改是可能的。除了组成部分和/或配置中的变化和修改之外,替代使用对于所属领域技术人员来说也将是显而易见的。
Claims (24)
1.一种薄膜晶体管阵列基板,包括:
基板;
位于所述基板上的栅极;
包括第一有源层和第二有源层的有源层,所述第一有源层与所述栅极相对并且与所述栅极相邻并包括半导体材料和多个碳的同素异形体,所述第二有源层与所述第一有源层接触并包括半导体材料;
位于所述栅极和所述有源层之间的栅极绝缘膜;以及
分别与所述有源层接触的源极和漏极。
2.如权利要求1所述的薄膜晶体管阵列基板,其中所述第二有源层还包括多个碳的同素异形体,其中在所述第一有源层中的碳的同素异形体所占的含量比高于在所述第二有源层中的碳的同素异形体所占的含量比。
3.如权利要求1或2所述的薄膜晶体管阵列基板,其中所述碳的同素异形体分散在所述半导体材料的内部。
4.如权利要求1或2所述的薄膜晶体管阵列基板,其中在所述第一有源层中的碳的同素异形体的含量比随着远离所述栅极而降低。
5.如权利要求2所述的薄膜晶体管阵列基板,其中所述第二有源层中的碳的同素异形体的含量比随着远离所述栅极而降低。
6.如权利要求1或2所述的薄膜晶体管阵列基板,其中所述碳的同素异形体具有一维结构或二维结构。
7.如权利要求1或2所述的薄膜晶体管阵列基板,其中所述碳的同素异形体是选自由还原的氧化石墨烯(rGO)、非氧化石墨烯、石墨烯纳米带、以及碳纳米管(CNT)组成的集合中的一种,或其混合物。
8.如权利要求1或2所述的薄膜晶体管阵列基板,其中所述半导体材料是选自由陶瓷半导体、有机半导体、过渡金属硫族化合物和氧化半导体组成的集合中的一种,或其混合物。
9.如权利要求1或2所述的薄膜晶体管阵列基板,其中基于100重量百分比的所述半导体材料的含量,所述第一有源层中的碳的同素异形体的含量是0.05重量百分比至1重量百分比。
10.如权利要求2所述的薄膜晶体管阵列基板,其中基于100重量百分比的所述半导体材料的含量,所述第二有源层中的碳的同素异形体的含量是0.001重量百分比至0.01重量百分比。
11.如权利要求1或2所述的薄膜晶体管阵列基板,其中所述第一有源层和所述第二有源层的厚度分别在1nm至10nm的范围内。
12.一种显示装置,包括:
基板;
位于所述基板上的栅极;
包括第一有源层和第二有源层的有源层,所述第一有源层与所述栅极相对并且与所述栅极相邻并包括半导体材料和多个碳的同素异形体,所述第二有源层与所述第一有源层接触并包括半导体材料;
位于所述栅极和所述有源层之间的栅极绝缘膜;
分别与所述有源层接触的源极和漏极;
位于所述源极和所述漏极上的有机绝缘膜;以及
位于所述有机绝缘膜上的像素电极。
13.如权利要求12所述的显示装置,其中所述第二有源层还包括多个碳的同素异形体,其中在所述第一有源层中的碳的同素异形体所占的含量比高于在所述第二有源层中的碳的同素异形体所占的含量比。
14.如权利要求12或13所述的显示装置,其中所述碳的同素异形体分散在所述半导体材料的内部。
15.如权利要求12或13所述的显示装置,其中在所述第一有源层中的碳的同素异形体的含量比随着远离所述栅极而降低。
16.如权利要求13所述的显示装置,其中所述第二有源层中的碳的同素异形体的含量比随着远离所述栅极而降低。
17.如权利要求12或13所述的显示装置,其中所述碳的同素异形体具有一维结构或二维结构。
18.如权利要求12或13所述的显示装置,其中所述碳的同素异形体是选自由还原的氧化石墨烯(rGO)、非氧化石墨烯、石墨烯纳米带、以及碳纳米管(CNT)组成的集合中的一种,或其混合物。
19.如权利要求12或13所述的显示装置,其中所述半导体材料是选自由陶瓷半导体、有机半导体、过渡金属硫族化合物和氧化半导体组成的集合中的一种,或其混合物。
20.如权利要求12或13所述的显示装置,其中基于100重量百分比的所述半导体材料的含量,所述第一有源层中的碳的同素异形体的含量是0.05重量百分比至1重量百分比。
21.如权利要求13所述的显示装置,其中基于100重量百分比的所述半导体材料的含量,所述第二有源层中的碳的同素异形体的含量是0.001重量百分比至0.01重量百分比。
22.如权利要求12或13所述的显示装置,其中所述第一有源层和所述第二有源层的厚度分别在1nm至10nm的范围内。
23.如权利要求12或13所述的显示装置,还包括:
电连接至所述像素电极的有机发光二极管;
位于所述有机发光二极管上的封装层;以及
位于所述封装层上的盖窗。
24.如权利要求12或13所述的显示装置,还包括:
公共电极,所述公共电极被设置为与位于相同平面上的像素电极间隔开或者位于所述像素电极的下部;以及
设置在所述公共电极上的液晶层。
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US10529806B2 (en) | 2020-01-07 |
CN107887397B (zh) | 2021-12-14 |
KR102573690B1 (ko) | 2023-09-04 |
KR20180036891A (ko) | 2018-04-10 |
TWI666622B (zh) | 2019-07-21 |
TW201824224A (zh) | 2018-07-01 |
EP3301724B1 (en) | 2020-11-11 |
US20180097062A1 (en) | 2018-04-05 |
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