CN107887294A - 芯片通用批键合装置及方法 - Google Patents

芯片通用批键合装置及方法 Download PDF

Info

Publication number
CN107887294A
CN107887294A CN201610877683.8A CN201610877683A CN107887294A CN 107887294 A CN107887294 A CN 107887294A CN 201610877683 A CN201610877683 A CN 201610877683A CN 107887294 A CN107887294 A CN 107887294A
Authority
CN
China
Prior art keywords
chip
area
picks
batch
places
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610877683.8A
Other languages
English (en)
Other versions
CN107887294B (zh
Inventor
郭耸
朱岳彬
陈飞彪
夏海
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Micro Electronics Equipment Co Ltd
Original Assignee
Shanghai Micro Electronics Equipment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Micro Electronics Equipment Co Ltd filed Critical Shanghai Micro Electronics Equipment Co Ltd
Priority to CN201610877683.8A priority Critical patent/CN107887294B/zh
Priority to KR1020197012198A priority patent/KR102191261B1/ko
Priority to JP2019517245A priority patent/JP6847206B2/ja
Priority to PCT/CN2017/103332 priority patent/WO2018059375A1/zh
Priority to US16/338,673 priority patent/US10770320B2/en
Priority to TW106133489A priority patent/TWI655707B/zh
Publication of CN107887294A publication Critical patent/CN107887294A/zh
Application granted granted Critical
Publication of CN107887294B publication Critical patent/CN107887294B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67712—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrate being handled substantially vertically
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67742—Mechanical parts of transfer devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7565—Means for transporting the components to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75743—Suction holding means
    • H01L2224/75745—Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75753—Means for optical alignment, e.g. sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/758—Means for moving parts
    • H01L2224/75821—Upper part of the bonding apparatus, i.e. bonding head
    • H01L2224/75822—Rotational mechanism
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/758—Means for moving parts
    • H01L2224/75821—Upper part of the bonding apparatus, i.e. bonding head
    • H01L2224/75824—Translational mechanism
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Robotics (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

本发明涉及一种芯片通用批键合装置及方法，该装置包括物料取放区和传输工作区，其中：所述物料取放区包括用于提供芯片的蓝膜片取放区和用于存放基底的基底取放区，所述蓝膜片取放区和基底取放区分设于所述传输工作区的两端；所述传输工作区沿从所述蓝膜片取放区至基底取放区的方向依次包括芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区；所述传输工作区内设有芯片载板传输装置，所述芯片载板传输装置贯穿所述传输工作区，在所述芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区之间移动送料。本发明通过兼容性设计，使装置通用于两种贴片方式，拓展了设备的应用范围；另外，模块化的设计可以根据需求进行配置，增加了设备的市场梯度。

Description

芯片通用批键合装置及方法
技术领域
本发明涉及芯片键合领域，特别涉及一种芯片通用批键合装置及方法。
背景技术
倒装芯片键合工艺是将芯片与载片连接形成的一种互连形式，如图1所示，将载片1上的多个芯片2以载板5承载的方式批量键合到基底4上，多个芯片2在载板5上位置被精确放置并吸附，键合过程中芯片2与载板5间被牢固定位，芯片2与芯片2间距L被精确保持，因此单个芯片2的串行键合被多个芯片2的并行键合取代从而有效提高了设备产率。另外，由于电子产品朝着轻、薄和小型化的趋势发展，使得芯片键合技术的应用日益增多，将芯片键合工艺与晶圆级封装工艺相结合，能够制作出封装尺寸更小、性能更高的封装形式。如果将芯片键合工艺与TSV(硅通孔)工艺相结合，能够制作出成本和性能更有竞争力的芯片结构。目前市场上存在3种fan-out(扩散型)键合工艺，其中基于chip First的fan-out键合工艺是得到广泛应用的主流工艺形式。如图2a和2b所示，fan-out(扩散型)键合工艺主要有die-up(芯片上标记朝上)和die-down(芯片上标记朝下)两种贴片方式，其中，die-up贴片方式芯片2中标记3不与基底4接触，die-down贴片方式中，芯片2的标记3与基底4接触。针对上述两种贴片方式，需要采用不同的键合装置进行键合，即键合装置不能通用，增加了生产成本。
另一方面，键合技术能够在不缩小线宽的情况下，在有限面积内进行最大程度的芯片叠加与整合，同时缩减SoC晶片封装体积与线路传导长度，进而提升晶片传输效率。芯片-晶圆键合技术(chip-to-wafer，C2W)相对于晶圆-晶圆键合技术(wafer-to-wafer，W2W)具有更高的良率和更低的产品成本。因此，C2W技术如何在保证高键合精度的同时具有更高的产率和是业界努力的目标。
发明内容
本发明提供一种芯片通用批键合装置及方法，以解决上述技术问题。
为解决上述技术问题，本发明提供一种芯片通用批键合装置，包括物料取放区和传输工作区，其中：
所述物料取放区包括用于提供芯片的蓝膜片取放区和用于存放基底的基底取放区，所述蓝膜片取放区和基底取放区分设于所述传输工作区的两端；
所述传输工作区沿从所述蓝膜片取放区至基底取放区的方向依次包括芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区；
所述传输工作区内设有芯片载板传输装置，所述芯片载板传输装置贯穿所述传输工作区，在所述芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区之间移动送料。
较佳地，所述芯片载板传输装置包括第一运动台、安装于所述第一运动台上的加压装置以及安装于所述加压装置上的载板。
较佳地，所述芯片拾取及分离区内设有分离台、翻转手以及取放装置，所述芯片对准及精调区内设有精调单元，所述芯片批键合区内设有承载台。
较佳地，所述取放装置包括支架，所述支架上安装有可水平移动的移位装置，所述移位装置上安装有可垂向移动的升降装置，所述升降装置上固定安装有取放手。
较佳地，所述升降装置上安装有第一对准系统。
较佳地，所述精调单元包括第二运动台、以及安装于所述第二运动台上的精调机械手和第二对准系统。
较佳地，所述承载台上安装有第三对准系统。
较佳地，所述移位装置上安装有多个升降装置，每个所述升降装置下方分别安装有所述取放手。
较佳地，所述蓝膜片取放区内设有载片台和第一机械手，所述第一机械手拾取所述载片台上的芯片移送至所述分离台上。
较佳地，所述基底取放区内设有基片库和第二机械手，所述第二机械手拾取所述承载台上键合完成后的基底，并移送至所述基片库。
较佳地，所述分离台下方设有顶出机构，用于将放置于所述分离台上的芯片顶起。
本发明还提供了一种芯片通用批键合方法，应用于如上所述的芯片通用批键合装置中，包括如下步骤：
S1：将芯片传输并交接至所述蓝膜片取放区，将基底传输并交接至所述基底取放区；
S2：多个芯片在所述芯片拾取及分离区内被拾取并利用芯片载板传输装置同时传递至所述芯片对准及精调区进行位置精度调整；
S3：位置调整完成后，利用所述芯片载板传输装置传递至所述芯片批键合区完成批量键合。
较佳地，在步骤S2中，当要求芯片上的标记朝下键合时，所述芯片拾取及分离区内的翻转手拾取芯片，翻转后将所述芯片交接至所述芯片载板传输装置；当要求芯片上的标记朝上键合时，所述芯片拾取及分离区内的取放装置拾取芯片，经由所述芯片对准及精调区调整精度后交接至所述芯片载板传输装置。
与现有技术相比，本发明提供的芯片通用批键合装置及方法，该装置包括物料取放区和传输工作区，其中：所述物料取放区包括用于提供芯片的蓝膜片取放区和用于存放基底的基底取放区，所述蓝膜片取放区和基底取放区分设于所述传输工作区的两端；所述传输工作区沿从所述蓝膜片取放区至基底取放区的方向依次包括芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区；所述传输工作区内设有芯片载板传输装置，所述芯片载板传输装置贯穿所述传输工作区，在所述芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区之间移动送料。本发明通过兼容性设计，使装置通用于两种贴片方式，拓展了设备的应用范围；另外，模块化的设计可以根据需求进行配置，增加了设备的市场梯度。
附图说明
图1为倒装芯片批键合的工艺流程示意图；
图2a和2b分别为扩散型键合工艺的两种贴片方法的示意图；
图3为本发明实施例一中芯片通用批键合装置的主视图；
图4为本发明实施例一中芯片通用批键合装置的俯视图；
图5为本发明实施例一中芯片载板传输装置的结构示意图；
图6为本发明实施例一中取放装置的结构示意图；
图7为本发明实施例一中芯片通用批键合方法的流程示意图；
图8为本发明实施例二中芯片通用批键合装置的主视图；
图9为本发明实施例二中芯片通用批键合装置的俯视图；
图10为本发明实施例二中取放装置的结构示意图。
图1-2b中：1-载片、2-芯片、3-标记、4-基底、5-载板；
图3-10中：110-蓝膜片取放区、111-载片台、112-第一机械手、113-芯片、114-标记；120-基底取放区、121-基片库、122-第二机械手、123-基底；210-芯片拾取及分离区、211-分离台、212-翻转手、213-取放装置、214-支架、215-移位装置、216-升降装置、217-取放手、218-第一对准系统、219-顶出机构；220-芯片对准及精调区、221-第二运动台、222-精调机械手、223-第二对准系统；230-芯片批键合区、231-承载台、232-第三对准系统；300-芯片载板传输装置、310-第一运动台、320-加压装置、330-载板。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。需说明的是，本发明附图均采用简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
实施例一
本发明提供的芯片通用批键合装置，如图3和图4所示，包括物料取放区和传输工作区，其中：
所述物料取放区包括用于提供芯片113的蓝膜片取放区110和用于存放基底123的基底取放区120，所述蓝膜片取放区110和基底取放区120分设于所述传输工作区的两端，芯片113从蓝膜片取放区110上料，键合完成后，收集至基底取放区120；
所述传输工作区沿从所述蓝膜片取放区110至基底取放区120的方向依次包括芯片拾取及分离区210、芯片对准及精调区220、以及芯片批键合区230；
所述传输工作区内设有芯片载板传输装置300，所述芯片载板传输装置300贯穿所述传输工作区，在所述芯片拾取及分离区210、芯片对准及精调区220、以及芯片批键合区230之间移动送料。
本发明通过兼容性设计，使装置通用于die-up和die-down两种贴片方式，拓展了设备的应用范围；另外，模块化的设计可以根据需求进行配置，增加了设备的市场梯度；另外，本发明采用芯片批键合方式，平衡了芯片拾取、芯片位置精调和芯片键合的时间，使键合设备在保证键合精度的同时提高了产率。
较佳地，请重点参考图5，所述芯片载板传输装置300包括第一运动台310、安装于所述第一运动台310上的加压装置320以及安装于所述加压装置320上的载板330。所述载板330用于吸附、承载批量的芯片113，并将批量的芯片113键合到基底123上，加压装置320用于使载板330上吸附的批量的芯片113与基底123牢固结合。
较佳地，请重点参考图3和图4，所述芯片拾取及分离区210内设有分离台211、翻转手21以及取放装置213，所述芯片对准及精调区220内设有精调单元，所述芯片批键合区230内设有承载台231。具体地，分离台211上设有一用于承载一组芯片113(例如从1～n共n个芯片113)的载片，当然，每个芯片113上方均设有标记114，在die-down贴片方式时，采用翻转手212实现拾取和翻转芯片113的目的；在die-up贴片方式时，采用取放装置213拾取和放置芯片113，经过精调单元的位置精度调整后，由芯片载板传输装置300将芯片113移送至芯片批键合区230，与承载台231上的基底123进行批键合。
较佳地，请继续参考图3，所述分离台211下方设有顶出机构219，用于将放置于所述分离台211上的芯片113顶起，便于所述翻转手212或所述取放装置213的拾取。
较佳地，请重点参考图6，所述取放装置213包括支架214，所述支架214上安装有可水平移动的移位装置215，所述移位装置215上安装有可垂向移动的升降装置216，所述升降装置216上固定安装有取放手217，所述移位装置215带动升降装置216水平移动(X向)，升降装置216带动取放手217垂向(Z向)移动，便于取放装置213从分离台211上拾取芯片113以及将芯片113准确交接至精调单元。
较佳地，请继续参考图3，所述支架214上还安装有第一对准系统218，所述取放装置213在拾取分离台211上的芯片113时，先利用第一对准系统218对芯片113位置进行扫描，确保取放手217准确拾取芯片113。
较佳地，请继续参考图3，所述精调单元包括第二运动台221、以及安装于所述第二运动台221上的精调机械手222和第二对准系统223，所述第二运动台221带动精调机械手222和第二对准系统223在水平向(X向)移动，使第二对准系统223依次扫描多个芯片113的位置，利用精调机械手222按照扫描的位置信息精确放置到载板330上。
较佳地，请继续参考图3，所述承载台231上安装有第三对准系统232，所述第三对准系统232用于确定基底123上标记的位置，以及芯片113上的标记的位置，使二者完全对准键合。
较佳地，请继续参考图3和图4，所述蓝膜片取放区110内设有载片台111和第一机械手112，所述第一机械手112拾取所述载片台111上的芯片113移送至所述分离台211上；所述基底取放区120内设有基片库121和第二机械手122，所述第二机械手122拾取所述承载台231上键合完成后的基底123，并移送至所述基片库121。
请重点参考图7，本发明还提供了一种芯片通用批键合方法，应用于如上所述的芯片通用批键合装置中，包括如下步骤：
S1：将芯片113传输并交接至所述蓝膜片取放区110，具体地，第一机械手112抓取载片台111上的载片放置于分离台211；
S2：多个芯片113在所述芯片拾取及分离区210内被拾取并利用芯片载板传输装置300同时传递至所述芯片对准及精调区220进行位置精度调整；
S3：位置调整完成后，利用所述芯片载板传输装置300传递至所述芯片批键合区230完成批量键合。
本发明采用芯片批键合方式，平衡了芯片拾取、芯片位置精调和芯片键合的时间，使键合设备在保证键合精度的同时提高了产率。
较佳地，在步骤S2中，当要求芯片113上的标记114朝下键合时，所述芯片拾取及分离区210内的翻转手212拾取芯片113，翻转后将所述芯片113交接至所述芯片载板传输装置300，调整精度后送至承载台231上批键合；当要求芯片113上的标记114朝上键合时，所述芯片拾取及分离区210内的取放装置213拾取芯片113，经由所述芯片对准及精调区220调整精度后交接至所述芯片载板传输装置300，直接送至承载台231上批键合。本发明可通用于die-up和die-down两种贴片方式，拓展了应用范围。
实施例二
请重点参考图8至图10，本实施例相较于实施例一具有如下区别：所述移位装置215上安装有多个升降装置216，每个所述升降装置216下方分别安装有所述取放手217，也就是说，移位装置215在支架214上的一次移动，可同时带动多个芯片113移动，提高工作效率，当然，为了配合多个取放手217的同时取放，还可在芯片对准及精调区220内设置多个精调机械手222(如图8所示)，进一步提高工作效率。
综上所述，本发明提供的芯片通用批键合装置及方法，该装置包括物料取放区和传输工作区，其中：所述物料取放区包括用于提供芯片113的蓝膜片取放区110和用于存放基底123的基底取放区120，所述蓝膜片取放区110和基底取放区120分设于所述传输工作区的两端；所述传输工作区沿从所述蓝膜片取放区110至基底取放区120的方向依次包括芯片拾取及分离区210、芯片对准及精调区220、以及芯片批键合区230；所述传输工作区内设有芯片载板传输装置300，所述芯片载板传输装置300贯穿所述传输工作区，在所述芯片拾取及分离区210、芯片对准及精调区220、以及芯片批键合区230之间移动送料。本发明通过兼容性设计，使装置通用于两种贴片方式，拓展了设备的应用范围；另外，模块化的设计可以根据需求进行配置，增加了设备的市场梯度。
显然，本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包括这些改动和变型在内。

Claims (12)

1.一种芯片通用批键合装置，其特征在于，包括物料取放区和传输工作区，其中：
所述物料取放区包括用于提供芯片的蓝膜片取放区和用于存放基底的基底取放区，所述蓝膜片取放区和基底取放区分设于所述传输工作区的两端；
所述传输工作区沿从所述蓝膜片取放区至基底取放区的方向依次包括芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区；
所述传输工作区内设有芯片载板传输装置，所述芯片载板传输装置贯穿所述传输工作区，在所述芯片拾取及分离区、芯片对准及精调区、以及芯片批键合区之间移动送料。
2.如权利要求1所述的芯片通用批键合装置，其特征在于，所述芯片载板传输装置包括第一运动台、安装于所述第一运动台上的加压装置以及安装于所述加压装置上的载板。
3.如权利要求2所述的芯片通用批键合装置，其特征在于，所述芯片拾取及分离区内设有分离台、翻转手以及取放装置，所述芯片对准及精调区内设有精调单元，所述芯片批键合区内设有承载台。
4.如权利要求3所述的芯片通用批键合装置，其特征在于，所述取放装置包括支架，所述支架上安装有可水平移动的移位装置，所述移位装置上安装有可垂向移动的升降装置，所述升降装置上固定安装有取放手。
5.如权利要求4所述的芯片通用批键合装置，其特征在于，所述升降装置上安装有第一对准系统。
6.如权利要求5所述的芯片通用批键合装置，其特征在于，所述精调单元包括第二运动台、以及安装于所述第二运动台上的精调机械手和第二对准系统。
7.如权利要求6所述的芯片通用批键合装置，其特征在于，所述承载台上安装有第三对准系统。
8.如权利要求4所述的芯片通用批键合装置，其特征在于，所述移位装置上安装有多个升降装置，每个所述升降装置下方分别安装有所述取放手。
9.如权利要求3所述的芯片通用批键合装置，其特征在于，所述蓝膜片取放区内设有载片台和第一机械手，所述第一机械手拾取所述载片台上的芯片移送至所述分离台上。
10.如权利要求3所述的芯片通用批键合装置，其特征在于，所述基底取放区内设有基片库和第二机械手，所述第二机械手拾取所述承载台上键合完成后的基底，并移送至所述基片库。
11.如权利要求3所述的芯片通用批键合装置，其特征在于，所述分离台下方设有顶出机构，用于将放置于所述分离台上的芯片顶起。
12.一种芯片通用批键合方法，应用于如权利要求1所述的芯片通用批键合装置中，其特征在于，包括如下步骤：
S1：将芯片传输并交接至所述蓝膜片取放区，将基底传输并交接至所述基底取放区；
S2：多个芯片在所述芯片拾取及分离区内被拾取并利用芯片载板传输装置同时传递至所述芯片对准及精调区进行位置精度调整；
S3：位置调整完成后，利用所述芯片载板传输装置传递至所述芯片批键合区完成批量键合。
如权利要求12所述的芯片通用批键合方法，其特征在于，在步骤S2中，当要求芯片上的标记朝下键合时，所述芯片拾取及分离区内的翻转手拾取芯片，翻转后将所述芯片交接至所述芯片载板传输装置；当要求芯片上的标记朝上键合时，所述芯片拾取及分离区内的取放装置拾取芯片，经由所述芯片对准及精调区调整精度后交接至所述芯片载板传输装置。
CN201610877683.8A 2016-09-30 2016-09-30 芯片通用批键合装置及方法 Active CN107887294B (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CN201610877683.8A CN107887294B (zh) 2016-09-30 2016-09-30 芯片通用批键合装置及方法
KR1020197012198A KR102191261B1 (ko) 2016-09-30 2017-09-26 유니버셜 칩 배치-본딩 장치 및 방법
JP2019517245A JP6847206B2 (ja) 2016-09-30 2017-09-26 ユニバーサルチップバッチボンディング装置及び方法
PCT/CN2017/103332 WO2018059375A1 (zh) 2016-09-30 2017-09-26 芯片通用批键合装置及方法
US16/338,673 US10770320B2 (en) 2016-09-30 2017-09-26 Universal chip batch-bonding apparatus and method
TW106133489A TWI655707B (zh) 2016-09-30 2017-09-29 Chip universal batch bonding device and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610877683.8A CN107887294B (zh) 2016-09-30 2016-09-30 芯片通用批键合装置及方法

Publications (2)

Publication Number Publication Date
CN107887294A true CN107887294A (zh) 2018-04-06
CN107887294B CN107887294B (zh) 2020-04-10

Family

ID=61763750

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610877683.8A Active CN107887294B (zh) 2016-09-30 2016-09-30 芯片通用批键合装置及方法

Country Status (6)

Country Link
US (1) US10770320B2 (zh)
JP (1) JP6847206B2 (zh)
KR (1) KR102191261B1 (zh)
CN (1) CN107887294B (zh)
TW (1) TWI655707B (zh)
WO (1) WO2018059375A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109461667A (zh) * 2018-12-06 2019-03-12 深圳市佳思特光电设备有限公司 半导体芯片封装键合设备及实现方法
CN111554604A (zh) * 2020-04-30 2020-08-18 苏州均华精密机械有限公司 提高精度与速度的接合装置
CN117116838A (zh) * 2023-08-08 2023-11-24 广东工业大学 阵列水射流刺晶式Mini-LED巨量转移装置及方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201522998U (zh) * 2009-11-06 2010-07-07 华中科技大学 一种芯片拾取与翻转装置
CN103367208A (zh) * 2013-07-02 2013-10-23 华中科技大学 一种用于高密度芯片的倒装键合平台
CN107134427A (zh) * 2016-02-29 2017-09-05 上海微电子装备有限公司 芯片键合装置及方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3504166B2 (ja) 1998-11-25 2004-03-08 株式会社新川 フリップチップボンディング装置
CN2664198Y (zh) * 2003-08-18 2004-12-15 威盛电子股份有限公司 多芯片封装结构
JP4831091B2 (ja) 2008-02-21 2011-12-07 パナソニック株式会社 ダイボンディング装置及びダイボンディング方法
KR101503151B1 (ko) * 2013-08-23 2015-03-16 세메스 주식회사 다이 본딩 장치 및 이를 이용한 다이 본딩 방법
JP2015130414A (ja) 2014-01-08 2015-07-16 東レエンジニアリング株式会社 自動ボンディング装置
KR101614204B1 (ko) * 2014-04-29 2016-04-20 세메스 주식회사 다이 픽업 유닛, 이를 포함하는 다이 본딩 장치 및 방법
SE538792C2 (en) * 2015-02-06 2016-11-29 Stora Enso Oyj Apparatus and method for component assembly
WO2016135915A1 (ja) * 2015-02-26 2016-09-01 富士機械製造株式会社 部品実装機
CN107134418B (zh) 2016-02-29 2020-02-18 上海微电子装备（集团）股份有限公司 倒装芯片键合装置及键合方法
CN107134422A (zh) 2016-02-29 2017-09-05 上海微电子装备（集团）股份有限公司 芯片键合装置及方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201522998U (zh) * 2009-11-06 2010-07-07 华中科技大学 一种芯片拾取与翻转装置
CN103367208A (zh) * 2013-07-02 2013-10-23 华中科技大学 一种用于高密度芯片的倒装键合平台
CN107134427A (zh) * 2016-02-29 2017-09-05 上海微电子装备有限公司 芯片键合装置及方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109461667A (zh) * 2018-12-06 2019-03-12 深圳市佳思特光电设备有限公司 半导体芯片封装键合设备及实现方法
CN111554604A (zh) * 2020-04-30 2020-08-18 苏州均华精密机械有限公司 提高精度与速度的接合装置
CN111554604B (zh) * 2020-04-30 2023-11-21 苏州均华精密机械有限公司 提高精度与速度的接合装置
CN117116838A (zh) * 2023-08-08 2023-11-24 广东工业大学 阵列水射流刺晶式Mini-LED巨量转移装置及方法
CN117116838B (zh) * 2023-08-08 2024-01-30 广东工业大学 阵列水射流刺晶式Mini-LED巨量转移装置及方法

Also Published As

Publication number Publication date
US10770320B2 (en) 2020-09-08
JP6847206B2 (ja) 2021-03-24
JP2019530248A (ja) 2019-10-17
TWI655707B (zh) 2019-04-01
KR20190055218A (ko) 2019-05-22
WO2018059375A1 (zh) 2018-04-05
TW201814821A (zh) 2018-04-16
KR102191261B1 (ko) 2020-12-15
CN107887294B (zh) 2020-04-10
US20200013647A1 (en) 2020-01-09

Similar Documents

Publication Publication Date Title
CN104701199A (zh) 一种倒装芯片键合设备
TWI704633B (zh) 一種晶片鍵合裝置
CN108886002B (zh) 芯片封装设备及其方法
US9966357B2 (en) Pick-and-place tool for packaging process
TWI645489B (zh) 晶片接合裝置及其接合方法
CN111063628B (zh) 一种芯片键合装置
CN107887294A (zh) 芯片通用批键合装置及方法
CN107134418A (zh) 倒装芯片键合装置及键合方法
CN109390249A (zh) 半导体制造装置
CN107134427B (zh) 芯片键合装置及方法
CN107134423B (zh) 倒装芯片键合装置及其键合方法
CN110970322B (zh) 一种芯片贴片设备及芯片贴片方法
CN116960047B (zh) 一种多芯片倒装封装设备及封装方法
CN206806294U (zh) 一种芯片键合装置
CN108511353B (zh) 一种芯片键合装置及方法
CN108122787B (zh) 芯片键合装置和芯片键合方法
CN107665828A (zh) 一种自动键合装置及方法
CN107452644B (zh) 分体式芯片载板搬运键合装置
CN108511362B (zh) 一种芯片键合装置
JP2002026074A (ja) ボンディング装置及びボンディング方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant