CN107887266A - The processing method of device wafer - Google Patents
The processing method of device wafer Download PDFInfo
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- CN107887266A CN107887266A CN201710820875.XA CN201710820875A CN107887266A CN 107887266 A CN107887266 A CN 107887266A CN 201710820875 A CN201710820875 A CN 201710820875A CN 107887266 A CN107887266 A CN 107887266A
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- device wafer
- grinding
- back side
- processing method
- defect layer
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- 238000012545 processing Methods 0.000 description 22
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 238000005299 abrasion Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000003746 solid phase reaction Methods 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
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- 239000004372 Polyvinyl alcohol Substances 0.000 description 3
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- 235000013855 polyvinylpyrrolidone Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
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- 239000007767 bonding agent Substances 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
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- 229910001651 emery Inorganic materials 0.000 description 2
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- 241001083492 Trapa Species 0.000 description 1
- 235000014364 Trapa natans Nutrition 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
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- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- ZZUFCTLCJUWOSV-UHFFFAOYSA-N furosemide Chemical compound C1=C(Cl)C(S(=O)(=O)N)=CC(C(O)=O)=C1NCC1=CC=CO1 ZZUFCTLCJUWOSV-UHFFFAOYSA-N 0.000 description 1
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- 239000007787 solid Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Grinding Of Cylindrical And Plane Surfaces (AREA)
Abstract
The processing method that device wafer is provided, it can be ensured that device chip after segmentation removes defect and bending strength.The processing method of device wafer is processed to the device wafer formed with multiple devices on front.The processing method of device wafer includes：Step is kept, the face side of device wafer is kept using chuck table and exposes the back side；And go defect layer generation step, while chuck table and grinding pad is set to rotate and be provided to the device wafer liquid for not containing abrasive particle, while grinding pad is abutted with the back side of device wafer and generate and remove defect layer, wherein, the grinding pad contains the abrasive particle that particle diameter is 0.35~1.7 (μm) [median] according to 20~50 weight %, and the roughness (Ra) for implementing the device wafer back side after defect layer generation step is 0.8nm~4.5nm.
Description
Technical field
The present invention relates to the processing method of device wafer.
Background technology
In recent years, for miniaturization of device etc., the chip (hereinafter referred to as " device wafer ") after formation device is processed
Obtain relatively thin.But such as when being ground to device wafer and its thickness is as thin as below 100 μm, catch and device be harmful to
The metallic element such as Cu go defect effect to reduce (due to going defect layer to be removed), it is possible to produce the action defect of device.
In order to solve the problem, in the subsequent handling of device manufacture, formed at the back side of the chip formed with device pair
What the metallic elements such as Cu were caught removes defect layer.The description below has been recorded in patent document 1：Using lapping liquid and use grinding
Pad and cmp (CMP) is implemented to the chip being ground, then provide flushing liquor to replace lapping liquid, ground using this
Defect layer is removed in mill pad formation.
In addition, as the evaluation method for removing defect, there are following methods：In the rear side using metallic element to device wafer
After forcibly being polluted, the atomic weight of metallic element is measured in face side, in the metallic atom measured
In the case of the not up to defined testing number of atomicity, it is judged as defect fully (for example, referring to patent document 2).
Patent document 1：Japanese Unexamined Patent Publication 2009-94326 publications
Patent document 2：Japanese Unexamined Patent Publication 2012-238732 publications
But when device wafer is further thinned, the bending strength drop of the device chip when ensuring defect be present
Low trend.Therefore, when relatively thin ground shaper part chip, it is difficult to which realization takes into account ensuring with bending strength really for defect
Protect.
The content of the invention
Thus, it is an object of the invention to provide the processing method of following device wafer：The device being able to ensure that after segmentation
Part chip removes defect and bending strength.
Purpose is realized in order to solve above-mentioned problem, the processing method of device wafer of the invention is formed on front
There is the processing method of the device wafer of multiple devices, it is characterised in that the processing method of the device wafer includes the steps：
Step is kept, the face side of the device wafer is kept using chuck table and exposes the back side；And remove defect layer
Generation step, while the chuck table and grinding pad is rotated and be provided to the device wafer liquid for not containing abrasive particle,
While the grinding pad is abutted with the back side of the device wafer and generate and remove defect layer, wherein, the grinding pad is according to 20 weight %
~50 weight % contain the abrasive particle that particle diameter is 0.35 μm~1.7 μm [median], implement this and go after defect layer generation step
The roughness Ra at the back side of the device wafer is 0.8nm~4.5nm.
In accordance with the invention it is possible to ensure that the device chip after segmentation removes defect and bending strength.
Brief description of the drawings
Fig. 1 is the stereogram of the device wafer of the processing object of the processing method for the device wafer for showing embodiment 1.
Fig. 2 be the device wafer of embodiment 1 processing method in used grinding lapping device configuration example solid
Figure.
Fig. 3 is the stereogram of the configuration example for the Grinding structural unit for showing the grinding lapping device shown in Fig. 2.
Fig. 4 is the flow chart of the flow of the processing method for the device wafer for showing embodiment 1.
Fig. 5 is the figure of the grinding steps of the processing method for the device wafer for showing embodiment 1.
Fig. 6 is the figure for going defect layer generation step of the processing method for the device wafer for showing embodiment 1.
Fig. 7 is the figure of the singulation step of the processing method for the device wafer for showing embodiment 1.
Fig. 8 is the figure of the grinding steps of the processing method for the device wafer for showing embodiment 2.
Fig. 9 is the figure for going defect layer generation step of the processing method for the device wafer for showing embodiment 2.
Figure 10 be the processing method for the device wafer for showing each embodiment grinding pad in contained abrasive particle average grain
The figure of relation between the arithmetic average roughness of the bending strength and the back side of footpath and device chip.
Label declaration
7：Chuck table；51：Grinding pad；W：Device wafer；WS：Front；WR：The back side；DV：Device；G：Remove defect layer；
ST1：Keep step；ST5：Go defect layer generation step.
Embodiment
Referring to the drawings, the mode (embodiment) for implementing the present invention is described in detail.The present invention not by
Content described in following embodiment limits.In addition, include those skilled in the art in following described structural element
Content, substantially the same content that can be readily apparent that.In addition, following described structure can be with appropriately combined.In addition, can
To carry out various omissions, displacement or the change of structure without departing from the spirit and scope of the invention.
[embodiment 1]
The processing method of the device wafer of embodiments of the present invention 1 is illustrated with reference to the accompanying drawings.Fig. 1 is to show to implement
The stereogram of the device wafer of the processing object of the processing method of the device wafer of mode 1.Fig. 2 is that the device of embodiment 1 is brilliant
The stereogram of the configuration example of grinding lapping device used in the processing method of piece.Fig. 3 is to show the grinding grinding dress shown in Fig. 2
The stereogram of the configuration example for the Grinding structural unit put.
The processing method of the device wafer of embodiment 1 is to be formed to remove defect on the back side WR of the device wafer W shown in Fig. 1
Layer G and the method that device wafer W is divided into device chip DT (being represented by dotted lines in Fig. 1).As shown in figure 1, device wafer
W is the discoideus semiconductor wafer or optical device wafer using silicon as mother metal.It is in lattice on by positive WS in device wafer W
Formed with device DV in the region that a plurality of segmentation preset lines S divisions that sub- shape is formed form.That is, device wafer W is on positive WS
Formed with multiple device DV.Implement grinding etc. in the back side WR of the rear side to positive WS and be thinned to device wafer W
After defined thickness, overleaf WR sides form and remove defect layer G.It is the back of the body in device wafer W i.e. each device DV of back side WR to remove defect layer G
Layer formed with crystal defect, strain etc. (being referred to as defect site) on the WR of face, it is to go to defect site to causing metallic pollution at this
Impurity is captured, the layer of set.In embodiment 1, overleaf WR sides are formed and gone after defect layer G, and device wafer W is divided
Device chip DT into including comprising device DV.In embodiment 1, formed is in device wafer W positive WS device DV
Logical device.
The processing method of the device wafer of embodiment 1 at least uses the grinding as processing unit (plant) shown in Fig. 2 to grind
Device 1.Grinding lapping device 1 is in order that device wafer W back side WR is thinned and carries out grinding and in order that mill
Cut the device wafer W after processing back side WR accurately planarize and formed in device wafer W back side WR sides remove defect layer G and
It is ground the device of processing.As shown in Fig. 2 grinding lapping device 1 mainly there is apparatus main body 2, first to be ground component 3, the
Two grinding components 4, Grinding structural unit 5, such as four chuck tables 7, box 8,9, the paraposition components being arranged on rotary table 6
10th, component 11, cleaning element 13, carrying-in/carrying-out component 14 and control member (not shown) are moved into.
First grinding component 3 is used to make have the grinding emery wheel 31 of grinding grinding tool while rotating installed in the lower end of main shaft
While it is pressed against the device wafer that thick grinding position B chuck table 7 kept along the Z-direction parallel with vertical
On W back side WR, so as to carry out thick grinding to device wafer W back side WR.Similarly, the second grinding component 4 is used to make
The grinding emery wheel 41 with grinding grinding tool installed in the lower end of main shaft is rotated while being pressed against along Z-direction positioned at essence
On the device wafer W for the thick grinding terminates that grinding position C chuck table 7 is kept back side WR, so as to device wafer W
Back side WR carry out fine ginding processing.
In embodiment 1, Grinding structural unit 5 by as shown in Figure 3 installed in main shaft lower end grinding pad 51 be configured to
The retaining surface of chuck table 7 is opposed.Grinding structural unit 5 rotates grinding pad 51 while being pressed against along Z-direction to be located at
On the back side WR for the device wafer W that the fine ginding that the retaining surface of abrasion site D chuck table 7 is kept terminates.Grind structure
Part 5 is used to make grinding pad 51 press device wafer W back side WR along Z-direction, so as to the back side to device wafer W
WR is ground processing.
The grinding pad 51 of Grinding structural unit 5 includes particle diameter as 0.35~1.7 (μm) [median] according to 20~50 weight %
Abrasive particle.That is, grinding pad 51 is less than more than 0.35 μm 1.7 μm according to the weight % average grain diameters included below of more than 20 weight % 50
Abrasive particle.The particle diameter that aggregate-value in the size distribution that average grain diameter refers to obtain by laser diffraction/scattering method is 50%.It is tired
The particle diameter that evaluation is 50% refers to, granule number is counted since the small abrasive particle of particle size, reaches total particle number
Particle diameter when 50%.It is expected in grinding pad 51 contained abrasive particle using Mohs' hardness it is higher than the silicon for forming device wafer W, be adapted to life
Into the abrasive particle for removing defect layer G, such as GC (green silicon carbide), WA (white fused alumina), diamond can be used.
The one side of Grinding structural unit 5 by switching valve 12 from lapping liquid provide source 15 by with alkalescence lapping liquid from grinding pad
The nozzle 16 of 51 splits is supplied to device wafer W back side WR, while being implemented using grinding pad 51 to device wafer W back side WR
So-called CMP (Chemical Mechanical Polishing, cmp) processing, then while by switching valve 12
Source 17 is provided from liquid, and the liquid for not containing abrasive particle (being pure water in embodiment 1) is supplied to device wafer W from nozzle 16
Back side WR, while using grinding pad 51 device wafer W back side WR sides formed remove defect layer G.Now, device wafer W's is anti-
Curved intensity is maintained.In embodiment 1, device wafer W bending strength maintains more than 1000MPa, but the present invention is not
It is limited to this, sets it to value as can obtaining desired device strength.In addition, as shown in figure 3, Grinding structural unit 5
With X-axis mobile member 52, the X-axis mobile member 52 makes grinding pad 51 together with main shaft in and and device vertical with Z-direction
Moved in the parallel X-direction of the width of main body 2.In embodiment 1, defect layer G is removed using containing the suitable generation such as GC
Abrasive particle grinding pad 51, provide from lapping liquid provide source 15 provide without fine-grained alkaline lapping liquid while entering
Row grinding steps ST4.In addition, in grinding steps ST4, it can also use and remove defect layer G abrasive particle containing suitable generate such as GC
Grinding pad 51, and use and contain silica (SiO2) etc. the lapping liquid of solid phase reaction particulate be ground step ST4.
Rotary table 6 is provided in the discoid workbench on the upper surface of apparatus main body 2, is arranged in water
Plane internal rotation, rotation driving is carried out according to the opportunity of regulation.On the rotary table 6 such as with 90 degree of phase angle between
Such as four chuck tables 7 are equipped every ground.This four chuck tables 7 are the chuck works for having in upper surface vacuum chuck
Make platform construction, enter vacuum adsorbed to placed device wafer W and keep.These chuck tables 7 in grinding and
Using the axle parallel with vertical as rotary shaft during attrition process, pass through rotary drive mechanism rotation driving in the horizontal plane.
So, chuck table 7 has the holding in a manner of it can rotate to being kept as the device wafer W of machined object
Face.Such chuck table 7 is moved to carrying-in/carrying-out position A, thick grinding position successively by the rotation of rotary table 6
B, fine ginding position C, abrasion site D and carrying-in/carrying-out position A.
Box 8,9 be have multiple slots for the collector stored to device wafer W.One box 8 is to being ground
The device wafer W that guard block P (shown in Fig. 5) is pasted with positive WS before attrition process is stored, and another box 9 is to mill
The device wafer W after attrition process is cut to be stored.In addition, paraposition components 10 are for placing the device taken out from box 8 temporarily
Wafer W and the workbench for carrying out wherein heart contraposition.
Moving into component 11 has absorption layer, and it is to the device before the grinding attrition process that is aligned by paraposition components 10
Wafer W adsorb holding and move into the chuck table 7 positioned at carrying-in/carrying-out position A.Component 11 is moved into being maintained at
Device wafer W after the grinding attrition process on carrying-in/carrying-out position A chuck table 7 adsorb holding and take out of
To cleaning element 13.
Carrying-in/carrying-out component 14 is, for example, the robot picker with U-shaped hand 14a, by 14a pairs of U-shaped hand
Device wafer W adsorb holding and transport.Specifically, carrying-in/carrying-out component 14 by be ground attrition process before device wafer
W is taken out of to paraposition components 10 from box 8, and the device wafer W after grinding attrition process is moved into box 9 from cleaning element 13.
Cleaning element 13 is cleaned to the device wafer W after grinding attrition process and will be attached on the machined surface after grinding and grinding
Grindstone dust and the pollutant removal such as lapping rejects.
The above-mentioned structural element that control member is ground lapping device 1 to forming is respectively controlled.That is, control member makes
Grinding lapping device 1 performs the processing action to device wafer W.Control member is the computer for being able to carry out computer program.
Control member has：Arithmetic processing apparatus, it has CPU (central processing unit, central processing unit) such
Microprocessor；Storage device, it has ROM (read only memory, read-only storage) or RAM (random access
Memory, random access memory) as memory；And input/output interface device.The CPU of control member is on RAM
The computer program that ROM is stored is performed, generates the control signal for controlling grinding lapping device 1.The CPU of control member will
The control signal generated is exported by input/output interface device to each structural element of grinding lapping device 1.In addition, control
Component processed and the state of display processing action and the display member (not shown) being made up of liquid crystal display device etc., the behaviour of image etc.
Author's input link connection used when being registered to processing content information etc..Input link is by being arranged on display member
At least one composition in touch panel and keyboard etc..
Then, the processing method of the device wafer of embodiment 1 is illustrated.Fig. 4 is the device for showing embodiment 1
The flow chart of the flow of the processing method of chip.Fig. 5 is the grinding steps of the processing method for the device wafer for showing embodiment 1
Figure.Fig. 6 is the figure for going defect layer generation step of the processing method for the device wafer for showing embodiment 1.Fig. 7 is to show to implement
The figure of the singulation step of the processing method of the device wafer of mode 1.
As shown in figure 4, the processing method (hereinafter referred to as processing method) of device wafer, which includes, keeps step ST1, corase grind
Cut step ST2, fine ginding step ST3, grinding steps ST4, remove defect layer generation step ST5 and singulation step ST6.Keeping
In step ST1, first, operator by be accommodated with grinding attrition process before device wafer W box 8 and non-storage device chip
W box 9 is arranged on apparatus main body 2, and machining information is registered in control member.Operator is defeated to grinding lapping device 1
Enter processing action to start to indicate, start to be ground the processing action of lapping device 1.
In step ST1 is kept, the carrying-in/carrying-out component 14 for being ground lapping device 1 takes out device wafer W from box 8 and taken out of
To paraposition components 10, paraposition components 10 carry out device wafer W center contraposition, move into component 11 device aligned is brilliant
Piece W positive WS sides are moved into being positioned on carrying-in/carrying-out position A chuck table 7.In step ST1 is kept, grinding
Lapping device 1 is kept by guard block P using chuck table 7 to device wafer W positive WS sides, makes back side WR
Expose, using rotary table 6 by device wafer W transport successively to thick grinding position B, fine ginding position C, abrasion site D and
Carrying-in/carrying-out position A.In addition, in grinding lapping device 1, when being rotated by 90 ° rotary table 6, before being ground attrition process
Device wafer W is moved to carrying-in/carrying-out position A chuck table 7.
In corase grind cuts step ST2, grinding lapping device 1 is brilliant to device using the first grinding component 3 in thick grinding position B
Piece W back side WR carries out thick grinding, and in fine ginding step ST3, grinding lapping device 1 uses the in fine ginding position C
Two grinding components 4 carry out fine ginding processing to device wafer W back side WR.
In grinding steps ST4, grinding lapping device 1 rotates chuck table 7 and grinding pad 51 in abrasion site D,
And provide source 15 from lapping liquid by switching valve 12 as shown in Figure 5 on one side and provide grinding to device wafer W back side WR
Liquid is while making grinding pad 51 be abutted with device wafer W back side WR and carrying out CMP attrition process to device wafer W back side WR.
As lapping liquid described herein, the liquid of the particle for grinding can be free from or containing being improved for structure
The lapping liquid of the solid phase reaction particulate such as silica into the abrasiveness of the silicon of device wafer W.In addition, grinding pad 51 is except above-mentioned
Containing GC etc. it is suitable generate go defect layer G abrasive particle grinding pad outside or it is micro- containing solid phase reactions such as silica
Grain and grinding pad 51 obtained by being fixed.In this case, the particulates such as silica can not be contained in lapping liquid.
In defect layer generation step ST5 is removed, grinding lapping device 1 makes chuck table 7 and grinding pad 51 in abrasion site D
Rotation, and provided not to device wafer W back side WR while providing source 17 from liquid by switching valve 12 as shown in Figure 6
Liquid containing abrasive particle is while making grinding pad 51 be abutted with device wafer W back side WR and being given birth in device wafer W back side WR sides
Into removing defect layer G.Implement the back side WR of the device wafer W after defect layer generation step ST5 roughness (Ra) for 0.8~
4.5nm.That is, the arithmetic average roughness (Ra) for implementing the back side WR of the device wafer W after defect layer generation step ST5 is
More than 0.8nm below 4.5nm.
So, in embodiment 1, processing method is in grinding steps ST4 and goes to share grinding in defect layer generation step ST5
Pad 51 and chuck table 7.In embodiment 1, in grinding steps ST4 and go in defect layer generation step ST5, to grinding pad 51
It is positioned such that the center of the periphery covering device wafer W of grinding pad 51 and is protruded from device wafer W outer rim.
Lapping device 1 is ground after defect layer generation step ST5 is removed, the device for implementing defect layer generation step ST5 is brilliant
Piece W is positioned at carrying-in/carrying-out position A, is moved into cleaning element 13 using component 11 is moved into, is carried out clearly using cleaning element 13
Wash, moved into the device wafer W after cleaning to box 9 using carrying-in/carrying-out component 14.
In singulation step ST6, device wafer W is taken out from box 9 is interior, after positive WS peels off guard block P, in device
Formed on the positive WS of part wafer W by including polyvinyl alcohol (polyvinyl alcohol：) or polyvinylpyrrolidone PVA
(polyvinyl pyrrolidone：) etc. PVP the diaphragm (not shown) that water-soluble resin is formed, and by device wafer W's
Back side WR sides attracting holding is in the chuck table 21 of the laser machine 20 shown in Fig. 7.In singulation step ST6, in such as Fig. 7
The shown laser beam irradiation unit 22 for making laser machine 20 along segmentation preset lines S-phase to move on one side from laser irradiation singly
Member 22 after having carried out hemisect to segmentation preset lines S implementation ablations, applies to segmentation preset lines S irradiation laser LR
External force and device wafer W is melted into each device chip DT along segmentation preset lines S monolithics.Cut entirely in irradiation laser LR
In the case of cutting, in singulation step ST6, device wafer W monolithics are melted into each device chip DT, then removed not shown
Diaphragm, device wafer W positive WS is cleaned, diaphragm is cleaned and removed together with chip.
In embodiment 1, singulation step ST6 is using having used laser LR ablation by device wafer W monolithics
Each device chip DT is melted into, but in the present invention, in singulation step ST6, laser can be irradiated and in device wafer W
Portion forms modification layer, so as to which device wafer W monolithics are melted into each device chip DT, can also utilize and use cutting tool
Device wafer W monolithics are melted into each device chip DT by machining.
As described above, in the processing method of embodiment 1, in defect layer generation step ST5 is removed, using according to 20 weight %
Grinding pads 51 of below the weight % of the above 50 containing the abrasive particle that average grain diameter is less than more than 0.35 μm 1.7 μm, while providing not
Liquid containing abrasive particle is while being ground processing and generating and remove defect layer G.Also, device wafer W back side WR arithmetic average
Roughness (Ra) is more than 0.8nm below 4.5nm.As a result, the processing method of embodiment 1 is able to ensure that the device after segmentation
Part chip DT's removes defect and bending strength.
In addition, the processing method of embodiment 1 is in defect layer generation step ST5 is removed, using according to more than 20 weight % 50
Grinding pads 51 of below the weight % containing the abrasive particle that average grain diameter is less than more than 0.35 μm 1.7 μm, mill is not contained while providing
The liquid of grain can make the device wafer W back side WR arithmetic average roughness (Ra) be while be ground processing
More than 0.8nm below 4.5nm.Therefore, the processing method of embodiment 1 by holding the abrasive particle contained by grinding pad 51 in advance
Particle diameter, the arithmetic average roughness for removing the high back side WR of defect dependency relation that can be held and go after defect layer generation step ST5
(Ra).As a result, the processing method of embodiment 1 passes through the back side WR to removing the device wafer W after defect layer generation step ST5
Arithmetic average roughness (Ra) evaluated, simple method can be utilized to go the good and bad of defect to carry out device chip DT
Judge.
[embodiment 2]
The processing method of the device wafer of embodiments of the present invention 2 is illustrated with reference to the accompanying drawings.Fig. 8 is to show to implement
The figure of the grinding steps of the processing method of the device wafer of mode 2.Fig. 9 is the processing side for the device wafer for showing embodiment 2
The figure for going defect layer generation step of method.In addition, in Fig. 8 and Fig. 9, pair with the identical part of embodiment 1 mark identical label
And eliminate explanation.
In the processing method (hreinafter referred to as processing method) of the device wafer of embodiment 2, implement grinding steps ST4
It is different from embodiment 1 with the structure for the Grinding structural unit 5 for removing defect layer generation step ST5, it is in addition, identical with embodiment 1.
In the processing method (hreinafter referred to as processing method) of embodiment 2, implement grinding steps ST4 and go defect layer to give birth to
Into step ST5 Grinding structural unit 5 as shown in Figure 8 and Figure 9, be provided with path 18 centrally disposed, the offer path 18 will come from
Lapping liquid provides the lapping liquid in source 15 or the liquid from liquid offer source 17 is supplied to the back of the body with device wafer W of grinding pad 51
The center for the abradant surface that face WR is abutted.In addition, embodiment 2 processing method grinding steps ST4 and go defect layer generation step
In rapid ST5, the whole back side WR of the overall covering device wafer W using grinding pad 51 is positioned to grinding pad 51.
The processing method of embodiment 2 is in the same manner as embodiment 1, in defect layer generation step ST5 is removed, using according to 20
Grinding pads 51 of below the weight % of more than weight % 50 containing the abrasive particle that average grain diameter is less than more than 0.35 μm 1.7 μm, on one side
The liquid for not containing abrasive particle is provided while being ground processing and producing and remove defect layer G.Also, device wafer W back side WR calculation
Art mean roughness (Ra) is more than 0.8nm below 4.5nm.As a result, the processing method of embodiment 2 is able to ensure that segmentation
Device chip DT's afterwards removes defect and bending strength.
Then, the present inventor is confirmed to the effect of embodiment 1 and the processing method of embodiment 2.
First, the present inventor's grinding pad 51 different to the average grain diameter using abrasive particle implements defect layer generation step ST5
The back side WR's of device wafer W afterwards goes defect to be confirmed.The result for the confirmation for removing defect is shown in table 1.
【Table 1】
| Movement of the copper atom to face side | |
| Product 1 of the present invention | Nothing |
| Product 2 of the present invention | Nothing |
| Product 3 of the present invention | Nothing |
| Product 4 of the present invention | Nothing |
| Comparative example | Have |
Product 1 of the present invention has used carries out the life of defect layer using the grinding pad 51 containing the abrasive particle that average grain diameter is 1.7 μm
Into step ST5 and obtain back side WR arithmetic average roughness (Ra) be 4.2nm device wafer W.Product 2 of the present invention uses
Back side WR calculation is obtained using defect layer generation step ST5 is carried out containing average grain diameter for the grinding pad 51 of 0.6 μm of abrasive particle
Art mean roughness (Ra) is 2.2nm device wafer W.It is 0.4 μm that product 3 of the present invention, which has been used using containing average grain diameter,
The arithmetic average roughness (Ra) that the grinding pad 51 of abrasive particle carries out defect layer generation step ST5 and obtains back side WR is 1.4nm's
Device wafer W.Product 4 of the present invention has used carries out defect layer using the grinding pad 51 containing the abrasive particle that average grain diameter is 0.36 μm
Generation step ST5 and obtain back side WR arithmetic average roughness (Ra) be 0.8nm device wafer W.Comparative example has used profit
Back side WR arithmetic is obtained with defect layer generation step ST5 is carried out containing average grain diameter for the grinding pad 51 of 0.25 μm of abrasive particle
Mean roughness (Ra) is 0.7nm device wafer W.
In table 1, per unit area 1.0 is coated with to product 1~4 of the present invention and the device wafer W of comparative example back side WR
×1013[atoms/cm2] Cu titers (copper sulphate), it is with 350 DEG C of temperature that device is brilliant after Cu titers are dried
Piece W is heated 3 hours, becomes the state that copper atom easily spreads.Device wafer W is cooled down, uses TXRF (total reflections
Fluorescent x-ray analyzer：Technos Co., Ltd. manufactures) to the front of the back side WR that is coated with Cu titers opposite side
WS CuproBraze technology measures.Specifically, device wafer W positive WS is divided into the area divided according to 15mm × 15mm
Domain, for each measurement that CuproBraze technology is carried out to a position of regional, CuproBraze technology is exceeded to the situation identification of ormal weight
To there is the movement of copper atom, the situation below ormal weight is regarded as to the movement of no copper atom.It can be seen from the result of table 1,
In comparative example, movement of the copper atom to positive WS be present, on the other hand, in product 1 of the present invention into product 4 of the present invention, do not have
Movement of the copper atom to positive WS.Therefore, it can be seen from table 1, by using containing average grain diameter be more than 0.35 μm 1.7 μm with
Under the grinding pad 51 of abrasive particle implement defect layer generation step ST5, it can be ensured that remove defect.
In addition, the present inventor's grinding pad 51 different to the average grain diameter using abrasive particle implements the generation of defect layer
The bending strength of device chip DT after step ST5 and the device wafer W back side WR arithmetic average roughness (Ra) are carried out
Measurement.Show the result in Figure 10.
Figure 10 be the processing method for the device wafer for showing each embodiment grinding pad in contained abrasive particle average grain
The figure of relation between the arithmetic average roughness of the bending strength and the back side of footpath and device chip.In Fig. 10, transverse axis represents
The average grain diameter of contained abrasive particle in grinding pad 51, the longitudinal axis represent device chip DT bending strength.In addition, the water chestnut using Figure 10
Shape represents the back side WR of device wafer W arithmetic average roughness (Ra).
It can be seen from Figure 10, when grinding pad 51 abrasive particle average grain diameter from when tapering into for 2.2 μm, bending strength is gradual
Uprise.In addition, when grinding pad 51 abrasive particle average grain diameter from when tapering into for 2.2 μm, device wafer W back side WR arithmetic
Mean roughness (Ra) tapers into, and it can be seen from the result of table 1, goes defect gradually to reduce.
Here, using (Poligrind series (Co., Ltd.'s enlightening of grinding pad 51 containing the abrasive particle that average grain diameter is 2.2 μm
Cisco manufactures)) bending strength when implementing defect layer generation step ST5 is 900MPa.The use of containing average grain diameter it is 1.5 μm
Bending strength when implementing defect layer generation step ST5 of the grinding pad 51 of abrasive particle be 1058MPa, be and use
Equal bending strength during Poligrind series.Therefore, according to the situation and average grain diameter that Figure 10 average abrasive grain is 1.5 μm
Understood for the result of 0.6 μm of situation etc., by using according to the weight % of 20 weight %~50 contain average grain diameter for 1.7 μm with
Under abrasive particle grinding pad 51 implement remove defect layer generation step ST5, it can be ensured that device wafer W bending strength.
Therefore, it can be seen from table 1 and Figure 10 result, contain by using according to below the weight % of more than 20 weight % 50
Average grain diameter is that the grinding pad 51 of less than more than 0.35 μm 1.7 μm of abrasive particle is implemented to remove defect layer generation step ST5, implements defect
The arithmetic average roughness (Ra) of device wafer W back side WR after layer generation step ST5 is more than 0.8nm below 4.5nm, can
Ensure that the device chip DT's after segmentation removes defect and bending strength.In addition, it can be seen from table 1 and Figure 10 result, pass through profit
With according to grinding pads of below the weight % of more than 20 weight % 50 containing the abrasive particle that average grain diameter is less than more than 0.4 μm 1.7 μm
51 implement to remove defect layer generation step ST5, implement the arithmetic average of the device wafer W back side WR after defect layer generation step ST5
Roughness (Ra) is more than 1.4nm below 2.2nm, can more ensure that the device chip DT's after segmentation goes defect and bending resistance strong
Degree.
[variation 1]
The processing method of the device wafer of the variation 1 of the embodiments of the present invention is illustrated.In embodiment 1
In embodiment 2, device wafer W device DV is logical device, but in variation 1, device DV is that memory (deposit by flash
The memory such as reservoir or DRAM (Dynamic Random Access Memory, dynamic random access memory)) device.Become
In the processing method of the device wafer of shape example 1, using being ground before lapping device 1 is processed, laser LR ablation is utilized
The machining of processing or cutting tool forms the groove for being not up to back side WR from positive WS along segmentation preset lines S, by right
Back side WR corase grind is cut, fine ginding and be divided into after each device chip DT, be ground successively step ST4 and go defect layer give birth to
Into step ST5, overleaf WR is formed and is removed defect layer G.In variation, corase grind cut step ST2 or fine ginding step ST3 equivalent to
Singulation step ST6.The processing method of the device wafer of variation 1 is same with each embodiment, it can be ensured that the device after segmentation
Part chip DT's removes defect and bending strength.So, the device wafer W of processing method of the invention represents monolithic chemical conversion embodiment party
Each device core shown in the situation and monolithic chemical conversion variation 1 before each device chip DT shown in formula 1 and embodiment 2
Both situations after piece DT.
[variation 2]
The processing method of the device wafer of the variation 2 of the embodiments of the present invention is illustrated.The He of embodiment 1
Grinding lapping device 1 used, which has, in embodiment 2 carries out the first grinding component 3, progress fine ginding that corase grind cuts step ST2
The second of step ST3 is ground component 4 and is ground step ST4 and removes defect layer generation step ST5 Grinding structural unit 5, deforms
Grinding lapping device 1 used, which has, in example 2 carries out roughly grinding the first grinding component 3 for cutting step ST2, carries out fine ginding step
ST3 the second grinding component 4, the Grinding structural unit for not providing lapping liquid and step ST4 being ground using the grinding pad of dry type
And the Grinding structural unit 5 of each embodiment with carrying out defect layer generation step ST5 be equal go defect layer generate component.Variation
The processing method of 2 device wafer is in the same manner as each embodiment, it can be ensured that device chip DT after segmentation go defect and
Bending strength.
According to each embodiment and each variation, the manufacture method of following device chip can be obtained.
(note 1)
A kind of manufacture method of device chip, it includes the steps：
Defect layer generation step is gone, while providing the liquid for not containing abrasive particle while making rotation to the back side of the device wafer of rotation
The grinding pad turned abuts and generates and remove defect layer, wherein, the grinding pad contains particle diameter for 0.35~1.7 according to 20~50 weight %
The abrasive particle of (μm) [median]；And
Singulation step, device wafer monolithic is melted into each device chip along segmentation preset lines.
In addition, the present invention is not limited to above-mentioned embodiment, variation.I.e., it is possible to the purport of the present invention is not being departed from
In the range of various modifications and implement.In the present invention, in defect layer generation step ST5 is removed, following grinding pads can be used
51：As shown in Japanese Unexamined Patent Publication 2015-46550, silicon is mixed into liquid bonding agent, causes the solid phase reaction of solid phase reaction micro-
Grain and Mohs' hardness are higher than silicon and cause the abrasive particles of grinding, and liquid bonding agent is immersed in non-woven fabrics and is formed,
It is micro- for the grinding of more than 0.35 μm 1.7 (μm) [median] below containing particle diameter according to below the weight % of more than 20 weight % 50
Grain.
Claims (1)
1. a kind of processing method of device wafer, the device wafer on front formed with multiple devices, wherein,
The processing method of the device wafer includes the steps：
Step is kept, the face side of the device wafer is kept using chuck table and exposes the back side；And
Defect layer generation step is gone, while making the chuck table and grinding pad rotate and be provided to the device wafer and not contain mill
The liquid of grain, while make the grinding pad be abutted with the back side of the device wafer and generate and remove defect layer, wherein, the grinding pad according to
The weight % of 20 weight %~50 contains the abrasive particle that particle diameter is 0.35 μm~1.7 μm [median],
The roughness Ra for implementing the back side of the device wafer gone after defect layer generation step is 0.8nm~4.5nm.
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|---|---|---|---|
| JP2016191955A JP2018056384A (en) | 2016-09-29 | 2016-09-29 | Processing method for device wafer |
| JP2016-191955 | 2016-09-29 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101407035A (en) * | 2007-10-10 | 2009-04-15 | 株式会社迪思科 | Grinding method for wafer |
| JP2010225987A (en) * | 2009-03-25 | 2010-10-07 | Disco Abrasive Syst Ltd | Polishing method of wafer and polishing pad |
| JP2013244537A (en) * | 2012-05-23 | 2013-12-09 | Disco Corp | Method for working plate-like object |
| JP2013247132A (en) * | 2012-05-23 | 2013-12-09 | Disco Abrasive Syst Ltd | Method for processing plate-like object |
| JP2015046550A (en) * | 2013-08-29 | 2015-03-12 | 株式会社ディスコ | Polishing pad and processing method of wafer |
Family Cites Families (1)
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|---|---|---|---|---|
| JP6324958B2 (en) * | 2013-07-02 | 2018-05-16 | 富士紡ホールディングス株式会社 | Polishing pad and manufacturing method thereof |
-
2016
- 2016-09-29 JP JP2016191955A patent/JP2018056384A/en active Pending
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2017
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- 2017-09-13 KR KR1020170117184A patent/KR20180035671A/en not_active Application Discontinuation
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101407035A (en) * | 2007-10-10 | 2009-04-15 | 株式会社迪思科 | Grinding method for wafer |
| JP2010225987A (en) * | 2009-03-25 | 2010-10-07 | Disco Abrasive Syst Ltd | Polishing method of wafer and polishing pad |
| JP2013244537A (en) * | 2012-05-23 | 2013-12-09 | Disco Corp | Method for working plate-like object |
| JP2013247132A (en) * | 2012-05-23 | 2013-12-09 | Disco Abrasive Syst Ltd | Method for processing plate-like object |
| JP2015046550A (en) * | 2013-08-29 | 2015-03-12 | 株式会社ディスコ | Polishing pad and processing method of wafer |
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| KR20180035671A (en) | 2018-04-06 |
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Application publication date: 20180406 |