CN107885939A - A kind of method for improving monitoring pattern monitoring precision - Google Patents

A kind of method for improving monitoring pattern monitoring precision Download PDF

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Publication number
CN107885939A
CN107885939A CN201711099108.0A CN201711099108A CN107885939A CN 107885939 A CN107885939 A CN 107885939A CN 201711099108 A CN201711099108 A CN 201711099108A CN 107885939 A CN107885939 A CN 107885939A
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monitoring
region
pattern
chip
area
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CN107885939B (en
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曹云
朱忠华
魏芳
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Shanghai Huali Microelectronics Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/392Floor-planning or layout, e.g. partitioning or placement
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00Details relating to the type of the circuit
    • G06F2115/06Structured ASICs

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The present invention proposes a kind of method for improving monitoring pattern monitoring precision, comprises the following steps:Standard redundant pattern addition is carried out to each chip and scribe area;Calculate the average geometric feature of monitor area in the average figure and geometric properties or chip of monitoring chip domain;Obtain each chip array coordinate;Obtain monitoring pattern centre coordinate;By four circumferential X of monitoring pattern, Y extension technogenic influence radiuses, optimization region is formed;Optimization region and ambient chip and the overlapping region of scribe area are calculated respectively;Chip is deleted with adding the redundant pattern of program addition in the overlapping region of scribe area by standard;It is characterized as that desired value re-starts addition redundant pattern to chip and scribe area crossover region with the average geometric type of monitor area in chip.The present invention is a kind of geometry environment optimization method around monitoring pattern, figure and the geometric properties difference of chip internal monitor area around monitoring pattern can be reduced, so as to reduce the difference of monitoring pattern measuring value and chip internal monitor area.

Description

A kind of method for improving monitoring pattern monitoring precision
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, and more particularly to a kind of monitoring pattern that improves monitors precision Method.
Background technology
The process that advanced integrated circuit fabrication process typically all includes hundreds of steps, the slight errors of any link will all be led The failure of whole chip is caused, it is stricter in particular with the continuous diminution of circuit critical size, its requirement to technology controlling and process. In the process for making of existing semiconductor devices, it will usually to the process monitoring parameter of monitoring pattern in scribe region (such as Line width, thickness etc.) measured, so as to the technology stability in on-line monitoring chip internal region.Therefore the measurement of monitoring pattern It is worth technique machining status that can correctly inside effective reaction chip, directly affects the yield of product.
In the product processing of reality, because monitoring pattern is influenceed by its peripheral region geometry environment, cause it Measuring value produces change with the change of its peripheral region geometry environment.Such as the prison of monitoring chemical mechanical milling tech copper thickness Control figure can because the density of figure around it, effective line width and girth it is different and different.If monitoring pattern surrounding enviroment Geometry environment and chip internal area differentiation are larger, then can cause monitoring pattern measuring value and chip internal monitor area produce compared with Big difference, the real process situation of chip internal can not be accurately reflected so as to the measuring value of monitoring pattern, and then can not correctly referred to The adjustment of technique is led, the final yield for influenceing product
The content of the invention
In order to solve the above problems, the present invention proposes a kind of method for improving monitoring pattern monitoring precision, and it is a kind of prison Geometry environment optimization method around figure is controlled, it is special that figure and the geometry of chip internal monitor area around monitoring pattern can be reduced Difference is levied, so as to reduce the difference of monitoring pattern measuring value and chip internal monitor area.
In order to achieve the above object, the present invention proposes a kind of method for improving monitoring pattern monitoring precision, including following step Suddenly:
Standard redundant pattern addition is carried out to each chip and scribe area;
Calculate the average geometric feature of monitor area in the average figure and geometric properties or chip of monitoring chip domain;
Obtain each chip array coordinate;
Obtain monitoring pattern centre coordinate;
By four circumferential X of monitoring pattern, Y extension technogenic influence radiuses, optimization region is formed;
Optimization region and ambient chip and the overlapping region of scribe area are calculated respectively;
Chip is deleted with adding the redundant pattern of program addition in the overlapping region of scribe area by standard;
It is characterized as that desired value re-starts to chip and scribe area crossover region with the average geometric type of monitor area in chip Add redundant pattern.
Further, the average geometric feature includes:Average pattern density, average figure girth and average figure weight Line width.
Further, the monitoring pattern includes critical size monitoring pattern, thin_film thickness monitoring figure.
Further, the technogenic influence radius is that the figure maximum model that can not ignore technogenic influence is produced to target area Enclose.
Further, graphic monitoring region has identical geometric properties, and monitored space with monitoring pattern in the chip Domain is much larger than monitoring pattern.
Further, it is described to add redundant pattern again, the shape of its geometric properties, size and interval be it is variable, according to Corresponding change is carried out according to the geometric properties in target monitoring region.
Further, the redundant pattern of adding again meets following relation with geometric properties in monitor area:
Density:(DenOptimize regionx(D2-d2)+DenMonitoring patternx d2)/D2=DenChip monitoring region,
Girth:∑PI optimizes region+∑PJ monitoring patterns=∑ PK chip monitorings region,
Weight line width:∑LWI optimizes regionx AI optimizes region+∑LWJ monitoring patternsx AJ monitoring patterns
=∑ LWK chip monitorings regionx AK chip monitorings region,
Wherein DenOptimize regionTo optimize region redundant pattern density, D2To optimize area size, d2For monitoring pattern size, DenMonitoring patternFor monitoring pattern density, DenChip monitoring regionFor chip monitoring zone leveling density, PI optimizes regionIt is each in region to optimize The girth of redundant pattern, PJ monitoring patternsFor each figure girth of monitoring pattern, PK chip monitorings regionFor chip monitoring region each figure week It is long, LWI optimizes regionFor the line width of i-th of figure of redundant pattern in optimization area, AI optimizes regionFor i-th of figure of redundant pattern in optimization area Area, LWJ optimizes regionFor the line width of j-th of figure of redundant pattern in optimization area, AJ optimizes regionTo optimize j-th of redundant pattern in area The area of figure, LWK optimizes regionFor the line width of k-th of figure of redundant pattern in optimization area, AK optimizes regionFor redundant pattern the in optimization area The area of k figure.
The method proposed by the present invention for improving monitoring pattern monitoring precision, to certain area around monitoring pattern in scribe region Figure in domain carries out geological information inspection, optimizes the redundant pattern addition in the region according to inspection result so that after optimization Monitoring pattern around have and chip internal monitor area quite or the less geometry environment of gap, and then reduce scribe area Difference in domain between monitoring pattern measured value and chip internal monitor area, realize effective monitoring of the monitoring pattern to technique.
Brief description of the drawings
Fig. 1 show the method flow diagram of the raising monitoring pattern monitoring precision of present pre-ferred embodiments.
Fig. 2 show the optimization area schematic of present pre-ferred embodiments.
Fig. 3 show redundant pattern needed for the scribe area of present pre-ferred embodiments and optimizes area schematic.
Fig. 4 show redundant pattern needed for each chip of present pre-ferred embodiments and optimizes area schematic.
Embodiment
The embodiment of the present invention is provided below in conjunction with accompanying drawing, but the invention is not restricted to following embodiment.Root According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simple The form of change and non-accurately ratio is used, be only used for conveniently, lucidly aiding in illustrating the purpose of the embodiment of the present invention.
Fig. 1 is refer to, Fig. 1 show the method flow of the raising monitoring pattern monitoring precision of present pre-ferred embodiments Figure.The present invention proposes a kind of method for improving monitoring pattern monitoring precision, comprises the following steps:
Step S100:Standard redundant pattern addition is carried out to each chip and scribe area;
Step S200:Monitor area is average several in the average figure and geometric properties or chip of calculating monitoring chip domain What feature;
Step S300:Obtain each chip array coordinate;
Step S400:Obtain monitoring pattern centre coordinate;
Step S500:By four circumferential X of monitoring pattern, Y extension technogenic influence radiuses, optimization region is formed;
Step S600:Optimization region and ambient chip and the overlapping region of scribe area are calculated respectively;
Step S700:Chip is deleted with adding the redundant pattern of program addition in the overlapping region of scribe area by standard;
Step S800:It is characterized as desired value to chip and scribe area crossover region with the average geometric type of monitor area in chip Re-start addition redundant pattern.
According to present pre-ferred embodiments, the average geometric feature includes:Average pattern density, average figure girth and Average figure weight line width.The monitoring pattern includes critical size monitoring pattern, thin_film thickness monitoring figure.The technique shadow It is that the figure maximum magnitude that can not ignore technogenic influence is produced to target area to ring radius, such as putting down in chemical mechanical milling tech Smoothization length.
Graphic monitoring region has identical geometric properties with monitoring pattern in the chip, and monitor area is much larger than prison Control figure.Described to add redundant pattern again, shape, size and the interval of its geometric properties are variable, according to target monitoring The geometric properties in region carry out corresponding change.
Fig. 1 is present invention specific implementation flow chart, carries out standard redundant pattern addition to each chip and scribe area first, The average geometric information of monitored space figure in computing chip is needed according to monitoring, wherein geological information includes:Pattern density, figure Girth and figure weight line width, secondly using the surrounding of monitoring pattern as starting point, to X, Y-direction extends technogenic influence radius d, Rectangular or square redundant pattern optimization region as shown in Figure 2 is formed, wherein technogenic influence radius d is to add in monitored technique During work, monitoring pattern is by the maximum magnitude that around descriptive geometry feature is influenceed, during chemical mechanical milling tech Planarization length.
According to the arrangement coordinate of known each chip of chip array acquisition of information, it is assumed that the upper right angular coordinate of Fig. 2 chips 1 For (X1RT,Y1RT), bottom right angular coordinate is (X1RB,Y1RB), the top left co-ordinate of chip 2 is (X2LT,Y2LT), lower-left angular coordinate is (X2LB,Y2LB), monitoring pattern centre coordinate is (X0,Y0), monitoring pattern width is D, wherein understanding X1 according to Fig. 2RT=X1RB, X2LT=X2LBThen:
Optimize region maximum magnitude coordinate by being calculated,
The lower left corner:XmLB=(X0-D/2-d),YmLB=(Y0- D/2-d),
The upper right corner:XmRT=(X0+D/2+d),YmRT=(Y0+ D/2+d),
It is assumed that die size is much larger than optimization region
Y1RB<YmLB<Y1RT, Y2LB<YmLB<Y2LTAnd X1RT<X2LT
1) Xm is worked asLBLess than X1RTOr X1RBWhen, it can be deduced that:
Chip 1 and the overlapping region in redundant pattern optimization area are:
The lower left corner:XmLB=(X0- D/2-d), YmLB=(Y0- D/2-d),
The upper right corner:X1RTOr X1RB, YmRT=(Y0+ D/2+d),
The overlapping region lower left corner of scribe area and redundant pattern optimization area is:
The lower left corner:X1RTOr X1RB, YmLB=(Y0-D/2-d)。
2) Xm is worked asLBMore than X1RTOr X1RBWhen, chip 1 optimizes region no overlap with redundant pattern,
The crossover region lower left corner of scribe area and redundant pattern optimization region is:
The lower left corner:XmLB=(X0- D/2-d), YmLB=(Y0-D/2-d)。
3) Xm is worked asRTMore than X2LTOr X2LBWhen, it can be deduced that:
Chip 2 and the overlapping region in redundant pattern optimization area are:
The lower left corner:X2LTOr X2LB, YmLB=(Y0- D/2-d),
The upper right corner:XmRT=(X0+D/2+d),YmRT=(Y0+ D/2+d),
The overlapping region upper right corner of scribe area and redundant pattern optimization region is:
The upper right corner:X2LTOr X2LB, YmRT=(Y0+D/2+d)。
4) Xm is worked asRTLess than X2LTOr X2LBWhen, chip 2 optimizes region no overlap with redundant pattern,
The overlapping region upper right corner of scribe area and redundant pattern optimization region is:
The upper right corner:XmRT=(X0+D/2+d),YmRT=(Y0+ D/2+d),
The lower left corner for the scribe area for calculating gained is cut into region shared by monitoring pattern with the scope that the upper right corner is defined to obtain Go out the crossover region of scribe area and redundancy optimization region.
The chip 1 being calculated, chip 2 and the redundant pattern in scribe area crossover region (as shown in Figure 3 and Figure 4) are deleted Remove, with the average geometric information of monitored space figure in the average geometric information of figure in the above-mentioned chip being calculated or chip For desired value, redundant pattern addition is carried out to the crossover region of chip 1, chip 2 and scribe area again.Add with standard redundant pattern Unlike adding, the redundant pattern at standard redundant pattern addition fixed size and interval, and the present invention then can be several according to target What information, such as pattern density, figure girth and figure weight line width, adjustment add again the shape of redundant pattern, size and Interval so that the redundant pattern added again can optimize the descriptive geometry information in optimization region, i.e. pattern density, figure week Long and figure weight line width, so reduce in optimization region i.e. around monitoring pattern a range of descriptive geometry feature and The gap of the average geometric feature of monitor area, adds so as to ensure that in corresponding technique in the average geometric feature or chip of chip During work, processing performance and the chip internal of monitor area are consistent, and realize effective monitoring.Wherein monitoring pattern and surrounding The average geometric feature of monitor area should meet following relation in geometric properties and chip in optimization regional extent:
Density:(DenOptimize regionx(D2-d2)+DenMonitoring patternx d2)/D2=DenChip monitoring region,
Girth:∑PI optimizes region+∑PJ monitoring patterns=∑ PK chip monitorings region,
Weight line width:∑LWI optimizes regionx AI optimizes region+∑LWJ monitoring patternsx AJ monitoring patterns
=∑ LWK chip monitorings regionx AK chip monitorings region,
Wherein DenOptimize regionTo optimize region redundant pattern density, D2To optimize area size, d2For monitoring pattern size, DenMonitoring patternFor monitoring pattern density, DenChip monitoring regionFor chip monitoring zone leveling density, PI optimizes regionIt is each in region to optimize The girth of redundant pattern, PJ monitoring patternsFor each figure girth of monitoring pattern, PK chip monitorings regionFor chip monitoring region each figure week It is long, LWI optimizes regionFor the line width of i-th of figure of redundant pattern in optimization area, AI optimizes regionFor i-th of figure of redundant pattern in optimization area Area, LWJ optimizes regionFor the line width of j-th of figure of redundant pattern in optimization area, AJ optimizes regionTo optimize j-th of redundant pattern in area The area of figure, LWK optimizes regionFor the line width of k-th of figure of redundant pattern in optimization area, AK optimizes regionFor redundant pattern the in optimization area The area of k figure.
In summary, the method proposed by the present invention for improving monitoring pattern monitoring precision, to monitoring pattern in scribe region Figure in surrounding certain area carries out geological information inspection, optimizes the redundant pattern addition in the region according to inspection result, So that have around monitoring pattern after optimization and chip internal monitor area quite or the less geometry environment of gap, and then The difference between monitoring pattern measured value and chip internal monitor area in scribe region is reduced, realizes monitoring pattern to technique Effective monitoring.
Although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention.Skill belonging to the present invention Has usually intellectual in art field, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Cause This, the scope of protection of the present invention is defined by those of the claims.

Claims (7)

  1. A kind of 1. method for improving monitoring pattern monitoring precision, it is characterised in that comprise the following steps:
    Standard redundant pattern addition is carried out to each chip and scribe area;
    Calculate the average geometric feature of monitor area in the average figure and geometric properties or chip of monitoring chip domain;
    Obtain each chip array coordinate;
    Obtain monitoring pattern centre coordinate;
    By four circumferential X of monitoring pattern, Y extension technogenic influence radiuses, optimization region is formed;
    Optimization region and ambient chip and the overlapping region of scribe area are calculated respectively;
    Chip is deleted with adding the redundant pattern of program addition in the overlapping region of scribe area by standard;
    It is characterized as that desired value re-starts addition to chip and scribe area crossover region with the average geometric type of monitor area in chip Redundant pattern.
  2. 2. the method according to claim 1 for improving monitoring pattern monitoring precision, it is characterised in that the average geometric is special Sign includes:Average pattern density, average figure girth and average figure weight line width.
  3. 3. the method according to claim 1 for improving monitoring pattern monitoring precision, it is characterised in that the monitoring pattern bag Include critical size monitoring pattern, thin_film thickness monitoring figure.
  4. 4. the method according to claim 1 for improving monitoring pattern monitoring precision, it is characterised in that the technogenic influence half Footpath is that the figure maximum magnitude that can not ignore technogenic influence is produced to target area.
  5. 5. the method according to claim 1 for improving monitoring pattern monitoring precision, it is characterised in that figure in the chip Monitor area has identical geometric properties with monitoring pattern, and monitor area is much larger than monitoring pattern.
  6. 6. the method according to claim 1 for improving monitoring pattern monitoring precision, it is characterised in that described to add redundancy again Figure, shape, size and the interval of its geometric properties are variable, and the geometric properties according to target monitoring region are carried out correspondingly Change.
  7. 7. the method according to claim 6 for improving monitoring pattern monitoring precision, it is characterised in that described to add redundancy again Figure meets following relation with geometric properties in monitor area:
    Density:(DenOptimize regionx(D2-d2)+DenMonitoring patternx d2)/D2=DenChip monitoring region,
    Girth:∑PI optimizes region+∑PJ monitoring patterns=∑ PK chip monitorings region,
    Weight line width:∑LWI optimizes regionx AI optimizes region+∑LWJ monitoring patternsx AJ monitoring patterns=∑ LWK chip monitorings regionx AK chip monitorings region,
    Wherein DenOptimize regionTo optimize region redundant pattern density, D2To optimize area size, d2For monitoring pattern size, DenMonitoring patternFor monitoring pattern density, DenChip monitoring regionFor chip monitoring zone leveling density, PI optimizes regionIt is each in region to optimize The girth of redundant pattern, PJ monitoring patternsFor each figure girth of monitoring pattern, PK chip monitorings regionFor chip monitoring region each figure week It is long, LWI optimizes regionFor the line width of i-th of figure of redundant pattern in optimization area, AI optimizes regionFor i-th of figure of redundant pattern in optimization area Area, LWJ optimizes regionFor the line width of j-th of figure of redundant pattern in optimization area, AJ optimizes regionTo optimize j-th of redundant pattern in area The area of figure, LWK optimizes regionFor the line width of k-th of figure of redundant pattern in optimization area, AK optimizes regionFor redundant pattern the in optimization area The area of k figure.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108710772A (en) * 2018-06-04 2018-10-26 上海华力微电子有限公司 A kind of arrangement method of monitoring pattern in scribe area
CN112180691A (en) * 2020-09-30 2021-01-05 上海华力集成电路制造有限公司 On-line monitoring method for spliced chips
CN114091291A (en) * 2022-01-24 2022-02-25 晶芯成(北京)科技有限公司 Monitoring method and system for semiconductor layout

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110173586A1 (en) * 2010-01-14 2011-07-14 International Business Machines Corporation Method for creating electrically testable patterns
CN102944984A (en) * 2012-11-29 2013-02-27 上海集成电路研发中心有限公司 Method for monitoring and compensating photoetching and splicing precisions of large-sized chip products
CN103676490A (en) * 2012-09-20 2014-03-26 中芯国际集成电路制造(上海)有限公司 Method for monitoring weak point forming reasons
CN103855044A (en) * 2014-03-31 2014-06-11 上海华力微电子有限公司 Method for adding redundant graphics
CN104091800A (en) * 2014-07-25 2014-10-08 上海华力微电子有限公司 Forming method for SRAM detection structure map
CN104183512A (en) * 2013-05-21 2014-12-03 中芯国际集成电路制造(上海)有限公司 Wafer monitoring method
US20150295572A1 (en) * 2005-06-07 2015-10-15 Renesas Electronics Corporation Semiconductor integrated circuit device
US20160071260A1 (en) * 2014-09-09 2016-03-10 Kla-Tencor Corporation Enhanced Patterned Wafer Geometry Measurements Based Design Improvements for Optimal Integrated Chip Fabrication Performance
CN106534727A (en) * 2016-11-30 2017-03-22 上海华力微电子有限公司 Circuit and method for monitoring relevant capacitance of CIS (CMOS Image Sensor) pixel units
US9703913B2 (en) * 2012-07-13 2017-07-11 Skyworks Solutions, Inc. Racetrack layout for radio frequency shielding

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150295572A1 (en) * 2005-06-07 2015-10-15 Renesas Electronics Corporation Semiconductor integrated circuit device
US20110173586A1 (en) * 2010-01-14 2011-07-14 International Business Machines Corporation Method for creating electrically testable patterns
US9703913B2 (en) * 2012-07-13 2017-07-11 Skyworks Solutions, Inc. Racetrack layout for radio frequency shielding
CN103676490A (en) * 2012-09-20 2014-03-26 中芯国际集成电路制造(上海)有限公司 Method for monitoring weak point forming reasons
CN102944984A (en) * 2012-11-29 2013-02-27 上海集成电路研发中心有限公司 Method for monitoring and compensating photoetching and splicing precisions of large-sized chip products
CN104183512A (en) * 2013-05-21 2014-12-03 中芯国际集成电路制造(上海)有限公司 Wafer monitoring method
CN103855044A (en) * 2014-03-31 2014-06-11 上海华力微电子有限公司 Method for adding redundant graphics
CN104091800A (en) * 2014-07-25 2014-10-08 上海华力微电子有限公司 Forming method for SRAM detection structure map
US20160071260A1 (en) * 2014-09-09 2016-03-10 Kla-Tencor Corporation Enhanced Patterned Wafer Geometry Measurements Based Design Improvements for Optimal Integrated Chip Fabrication Performance
CN106534727A (en) * 2016-11-30 2017-03-22 上海华力微电子有限公司 Circuit and method for monitoring relevant capacitance of CIS (CMOS Image Sensor) pixel units

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
N.TNTAN等: "Design an Integrated Microprocessor Supervisory Chip for Monitoring Power Failure", 《IEEE XPLORE》 *
李亮: "新结构4H-SiC MESFET设计与实验研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》 *
范江: "一种有效监控制版图形尺寸的方法", 《半导体技术》 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108710772A (en) * 2018-06-04 2018-10-26 上海华力微电子有限公司 A kind of arrangement method of monitoring pattern in scribe area
CN108710772B (en) * 2018-06-04 2022-07-01 上海华力微电子有限公司 Arrangement method of monitoring graphs in scribing region
CN112180691A (en) * 2020-09-30 2021-01-05 上海华力集成电路制造有限公司 On-line monitoring method for spliced chips
CN112180691B (en) * 2020-09-30 2024-01-09 上海华力集成电路制造有限公司 On-line monitoring method for spliced chip
CN114091291A (en) * 2022-01-24 2022-02-25 晶芯成(北京)科技有限公司 Monitoring method and system for semiconductor layout

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