CN107862371A - Vehicle entrucking counting control system - Google Patents
Vehicle entrucking counting control system Download PDFInfo
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- CN107862371A CN107862371A CN201711133999.7A CN201711133999A CN107862371A CN 107862371 A CN107862371 A CN 107862371A CN 201711133999 A CN201711133999 A CN 201711133999A CN 107862371 A CN107862371 A CN 107862371A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06M—COUNTING MECHANISMS; COUNTING OF OBJECTS NOT OTHERWISE PROVIDED FOR
- G06M1/00—Design features of general application
- G06M1/27—Design features of general application for representing the result of count in the form of electric signals, e.g. by sensing markings on the counter drum
- G06M1/272—Design features of general application for representing the result of count in the form of electric signals, e.g. by sensing markings on the counter drum using photoelectric means
Abstract
A kind of vehicle entrucking counting control system, including controller unit, human and machine interface unit and 1 tunnel or multichannel entrucking belt driver element, count signal generation unit, anti-jamming circuit unit.Entrucking product is counted automatically during the system entrucking, avoids the problem of artificial counting easily goes wrong；Count pulse can filter out narrow pulse interference automatically, ensure that the accuracy of counting；Filtering out the jamproof effect of burst pulse can be adjusted by adjusting the parameter in multichannel anti-jamming circuit unit.
Description
Technical field
The present invention relates to logistics field, especially a kind of vehicle entrucking counting control system.
Background technology
In manufacturing enterprises such as chemical fertilizer, cement, feed, grain depots, it is required for shipping substantial amounts of bagged product, entrucking process daily
Middle generally use manually counts by the mode of bag statistics, and after entrucking bag number to be achieved, notice belt conveyor shuts down.Manually
Counting easily goes wrong, and causes companies losses or dispute occurs with delivery of cargo personnel；Artificial counting efficiency is low, and cost is high.
The content of the invention
In the presence of solving the problems, such as that existing bagged product entrucking counts, the invention provides a kind of vehicle entrucking meter
Number control system, including controller unit, human and machine interface unit, L roads entrucking belt driver element, L roads count signal produce list
Member, L roads anti-jamming circuit unit.The L is the integer more than or equal to 1.
Entrucking belt driver element in L roads is connected with controller unit, for driving entrucking belt system in L roads to run；It is man-machine
Boundary element is connected with controller unit, starts to fill for setting and showing entrucking quantity, start the operation of L road entruckings belt system
Car；L roads count signal generation unit branch is arranged on L roads entrucking belt system, is produced respectively and is exported the initial arteries and veins of L roads counting
Punching；L roads count the input pulse end that inceptive impulse delivers to L roads anti-jamming circuit unit respectively；L roads anti-jamming circuit unit it is defeated
Go out pulse ends and be connected to controller unit.
After starting the operation beginning entrucking of L road entruckings belt system, controller unit is defeated according to L roads anti-jamming circuit unit
Go out pulse to count vehicle entrucking quantity, after the entrucking quantity for reaching setting, stop the operation of L road entruckings belt system.
The L roads count signal generation unit is optoelectronic switch sensor.The controller unit is programmable control
Device processed.
The L roads anti-jamming circuit unit is same anti-jamming circuit unit；The anti-jamming circuit unit includes
Shift register, 1 number counter of sampled value, 0 number counter of sampled value, compare threshold setting device, the first digital comparator,
Second value comparator, rest-set flip-flop, oscillator.
Shift register includes serial input terminal, N parallel-by-bits output end, sample clock pulse input, shift register
Serial input terminal be anti-jamming circuit unit input pulse end, the N parallel-by-bit output end output sequence numbers of shift register
According to；The input of 1 number counter of sampled value is sequence data, is exported as 1 number statistical value of sampled value；0 number statistics of sampled value
The input of device is sequence data, is exported as 0 number statistical value of sampled value；The output for comparing threshold setting device is to compare threshold value；The
The input of one digital comparator is 1 number statistical value of sampled value and compares threshold value, is exported as the first set signal；Second value ratio
Input compared with device for 0 number statistical value of sampled value and compares threshold value, exports as the second set signal；The input of rest-set flip-flop is the
One set signal and the second set signal, output end are the output pulse ends of anti-jamming circuit unit；During oscillator output sampling
Clock.
The sequence data is nearest n times sampled value of the shift register at sample clock pulse edge to input pulse,
The sampled value is binary data data 0 or 1, and the N is the integer more than or equal to 2.The relatively threshold value is more than N/2
(N divided by 2) and the integer less than or equal to N.
The function of 1 number counter of sampled value is that 1 number statistical value of sampled value of output is the sequence data of input
In " 1 " number quantitative value；The function of 0 number counter of sampled value is that 0 number statistical value of sampled value of output is defeated
The quantitative value of the number of " 0 " in the sequence data entered.
The function of first digital comparator is, when 1 number statistical value of sampled value, which is more than or equal to, compares threshold value, output
The first set signal it is effective, the first set invalidating signal otherwise exported；The function of the second value comparator is, when adopting
For 0 number statistical value of sample value more than or equal to when comparing threshold value, the second set signal of output is effective, the second set letter otherwise exported
It is number invalid.
First set signal is the set signal of rest-set flip-flop, and the second set signal is the reset signal of rest-set flip-flop；It is defeated
Go out pulse to export from the in-phase output end of rest-set flip-flop, export pulse or exported from the reversed-phase output of rest-set flip-flop.
The beneficial effects of the invention are as follows：1 tunnel or multichannel entrucking product are counted automatically during entrucking, avoid artificial counting
The problem of easily going wrong；Count pulse can filter out positive narrow pulse interference and negative narrow pulse interference automatically, ensure that counting
Accuracy；Filtering out the jamproof effect of burst pulse can be by changing the digit of shift register parallel output terminal, either
The size that threshold value is compared in change is adjusted.
Brief description of the drawings
Fig. 1 is vehicle entrucking counting control system embodiment block diagram；
Fig. 2 is count signal generation unit embodiment；
Fig. 3 is anti-jamming circuit unit embodiment；
Fig. 4 is N=5 shift register embodiments；
1 number counter embodiment of sampled value when Fig. 5 is N=5；
0 number counter embodiment of sampled value when Fig. 6 is N=5；
Fig. 7 compares the embodiment of threshold setting device and the first digital comparator when being N=5；
Fig. 8 is rest-set flip-flop embodiment；
Fig. 9 is oscillator embodiment；
Input/output pulse anti-jamming effectiveness schematic diagram when Figure 10 is N=5.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
Vehicle entrucking counting control system embodiment block diagram when be L=2 as shown in Figure 1, for controlling and driving has 2 tunnels to fill
The loading system of car belt conveyor, including 2 road count signal generation units, No. 2 anti-jamming circuit units, controller unit
10th, 2 tunnel entrucking belt driver elements 11, the road count signal generation unit of human and machine interface unit 12,2 are that 1# count signals produce list
Member, 2# count signal generation units, No. 2 anti-jamming circuit units are 1# anti-jamming circuits unit and 2# anti-jamming circuit units.
The embodiment of 1# count signal generation units is illustrated in figure 2, using Omron correlation optoelectronic switch, light projector
201 model E3ZG-T61-S；The model E3ZG-T61-S of light-receiving device 202, its output end OUT1 use NPN triode collection
Electrode open circuit output, resistance R201 be its collector resistance, the 1# counting inceptive impulse P10 of 1# count signal generation units from by
The OUT1 ends output of light device 202.In Fig. 5 ,+VCC is the power supply of optoelectronic switch, and GND is publicly.1# count signals produce
Unit can also use other correlation optoelectronic switch, reflective photoelectric switches, and the pulse output form of optoelectronic switch can also
It is the output type of other forms.The circuit and structure of 2# count signal generation units are identical with 1# count signal generation units.
This 2 road count signal generation unit of 1#, 2# is separately mounted on 2 tunnel entrucking belt conveyors, is respectively used to entrucking product warp
Inceptive impulse P11, P21 are counted by being produced during 2 tunnel entrucking belt conveyor entrucking.
During L=2 in vehicle entrucking counting control system embodiment, 1# anti-jamming circuits unit and 2# anti-jamming circuit units
Using with mutually isostructural anti-jamming circuit unit.Inceptive impulse P11, P21 are counted respectively from 1# anti-jamming circuits unit, 2#
The input pulse end input of anti-jamming circuit unit, 1# anti-jamming circuits unit, the output pulse ends of 2# anti-jamming circuit units
Output count pulse P12, P22, P12, P22 are connected to controller unit 10 respectively, that is, 2 countings for being connected to PLC are defeated
Enter end.
It is illustrated in figure 3 anti-jamming circuit unit embodiment.In Fig. 3, shift register 101 includes serial input terminal, N positions
Parallel output terminal, sample clock pulse input, input pulse P1 input from the serial input terminal of shift register 101, displacement
The serial input terminal of register 101 is the input pulse end of anti-jamming circuit unit；Sample clock pulse CLK is from shift register
101 sample clock pulse input input, the sequence data X1 of the N parallel-by-bits output end output N positions of shift register 101；
The input of 1 number counter 102 of sampled value is sequence data X1, is exported as 1 number statistical value Y1 of sampled value；0 number of sampled value
The input of counter 103 is sequence data X1, is exported as 0 number statistical value Y2 of sampled value；Compare the output of threshold setting device 104
To compare threshold value Y0；The input of first digital comparator 105 is 1 number statistical value Y1 of sampled value and compare threshold value Y0, exports and is
First set signal SE1；The input of second value comparator 106 is 0 number statistical value Y2 of sampled value and compares threshold value Y0, is exported
For the second set signal RE1；The input of rest-set flip-flop 107 is the first set signal SE1 and the second set signal RE1, exports and is
The output pulse ends of anti-jamming circuit unit, the output for exporting pulse ends are output pulse P2；Oscillator 108 exports sampling clock
Pulse CLK.
In following anti-jamming circuit unit embodiment, N=5.
Fig. 4 is the embodiment of 5 bit shift registers.In Fig. 4,5 d type flip flops FF1, FF2, FF3, FF4, FF5 form 5
Serial shift register, FF1 input D are the serial input terminal of shift register, are connected to input pulse P1；FF1、FF2、
After FF3, FF4, FF5 input end of clock CLK parallel connections, the shift pulse input of shift register, i.e. shift register are formed
Sample clock pulse input, and be connected to sample clock pulse CLK；FF1, FF2, FF3, FF4, FF5 output end Q difference
For x11, x12, x13, x14, x15, in Fig. 4, sequence data X1 is made up of x11, x12, x13, x14, x15.Sequence data X1 is
Nearest n times sampled value of rising edge of the shift register in sample clock pulse CLK edges to input pulse P1.
When N is other numerical value, the quantity of d type flip flop in Fig. 4 can be increased and decreased to realize the function of shift register.D in Fig. 4
Trigger can be replaced with other triggers, for example, realizing the function of shift register using N number of JK flip-flop.Displacement
Register can also be realized using single or multiple special multibit shift registers, for example, using 1 74HC164 or
Person is 1 74HC595, it is possible to achieve the function of the shift register of 8 is not more than, using multi-disc 74HC164 either multi-discs
74HC595, it is possible to achieve the function of the shift register more than 8.
The embodiment of 1 number counter of sampled value when Fig. 5 is N=5.The function of 1 number counter of sampled value is, output
1 number statistical value Y1 of sampled value is the quantitative value of the number of " 1 " in the sequence data X1 inputted.In Fig. 5,1 number system of sampled value
Gauge is made up of 1 full adder FA1, FA2, FA3, and 1 in Fig. 5 full adder includes 1 addend input A, 1 addend
Input B, carry input Ci, and 1 result output end S, 1 carry output Co.1 full adder FA1 realize x11,
The statistics of the number of " 1 " in x12, x13,2 binary system statistical results that n2, n1 are FA1 export.21 full adder FA2,
FA3 forms 2 binary adders, and FA2, FA3 are using n2, n1 as an addend, using x14 as another addend, by x15
It is added as low order carry, obtains 3 binary systems output y13, y12, y11, y13, y12, y11 are 1 number of sampled value
Statistical value Y1；It is 0 using x14 as the high position that during another addend, another addend inputs from FA3 B ends.It is connected to and adopts
During the input of 1 number counter of sample value, x11, x12, x13, x14, x15 link position mutually can be exchanged arbitrarily.N positions sequence
Column data X1 is N bit binary datas, and 1 number counter of sampled value is actually in a statistics N bit binary data " 1 "
The statistics adder of number.
0 number counter of sampled value is by the structure with 1 number counter of sampled value and forms identical statistics adder and N
Bit Inverting device forms；The input of N bit Inverting devices is N bit sequence data X1, is exported as N bit Inverting sequence datas.When Fig. 6 is N=5
The embodiment of 0 number counter of sampled value.The function of 0 number counter of sampled value is 0 number statistical value Y2 of sampled value of output
The quantitative value of the number of " 0 " in the sequence data X1 of input.In Fig. 6,0 number counter of sampled value is included by 5 phase inverters
The statistics adder of 5 bit Inverting devices of FN1, FN2, FN3, FN4, FN5 composition and 31 full adder FA4, FA5, FA6 compositions, 5
The function of bit Inverting device is that 5 bit sequence data X1 x11, x12, x13, x14, x15 is anti-phase one by one, and the number to " 0 " is entered
Row statistics is converted to be counted to the number of " 1 ".1 full adder in Fig. 6 also include 1 addend input A, 1
Addend input B, carry input Ci, and 1 result output end S, 1 carry output Co.1 full adder FA4 is realized
The statistics of the number of " 0 " in x11, x12, x13,2 binary system statistical results that m2, m1 are FA4 export.21 full adders
FA5, FA6 form 2 binary adders, and FA5, FA6, will using m2, m1 as an addendAs another addend,
WillIt is added as low order carry, obtains 3 binary systems output y23, y22, y21, y23, y22, y21 are sampled value
0 number statistical value Y2；WillDuring as another addend, the high position that another addend inputs from FA6 B ends is 0.Even
When being connected to the input of 0 number counter of sampled value, x11, x12, x13, x14, x15 link position can be mutually any mutual
Change.
0 number counter of sampled value of 1 number counter sum of sampled value can also be realized using other circuit forms
1 adder functions in function, for example, 4 adder 74HC283 are integrated using carry look ahead, or 4 binary systems are simultaneously
Traveling position full adder CD4008, or 3 bit-serial adder CD4032, or the combinational logic circuit of gate circuit composition replace
All or part of 1 adder changed in Fig. 5, Fig. 6.
Fig. 7 compares the embodiment of threshold setting device and the first digital comparator when being N=5, in Fig. 7, compare threshold value setting
Device is made up of 3 binary system toggle switch SW1, and+VCC is power supply, GND for publicly, its 3 binary systems output y03,
Y02, y01 ratio of components are compared with threshold value Y0.Due to N=5, Y0 can only in 3,4,5 value, in the present embodiment, compare threshold value Y0 values
For 4, i.e., y03, y02, y01 value are 1,0,0.Comparing threshold setting device can be by multidigit binary system toggle switch, either
BCD toggle switch, or multiple regular taps add pull-up resistor, or the multiple pull-up resistors and electricity of the output of control 0,1
Short out contact, and other circuits that can export multidigit binary system setting value form.
The first digital comparator, FC1 model 74HC85 are formed by tetrad numerical value comparator FC1 in Fig. 7.Adopt
1 number statistical value Y1 of the sample value output of 3 binary systems y13, y12, y11 are respectively connecting to FC1 A2, A1, A0 input, compare
Threshold value the Y0 output of 3 binary systems y03, y02, y01 are respectively connecting to FC1 B2, B1, B0 input, and input A3, B3 connect
0.FC1 input A>B IN and A<B IN connect 0, and input A=B IN connect 1.FC1 output terminals A<B OUT outputs first
Set signal SE1.The function that the first digital comparator is realized in Fig. 7 is compared when 1 number statistical value Y1 of sampled value is more than or equal to
During threshold value Y0, output SE1 is low level, and otherwise SE1 is high level.SE1 is that low level is effective in Fig. 7.
When N values are larger, the 2 or multi-disc 74HC85 more bit binary value comparators of composition can be selected to realize first
The function of digital comparator；The first numerical value can also be realized using 1 or multi-disc tetrad numerical value comparator CD4063
The function of comparator, or realize using other combinational logic circuits the function of the first digital comparator.Second value ratio
Identical with the first digital comparator compared with the realization principle circuit of device, its function is, when 0 number statistical value Y2 of sampled value is more than or equal to
When comparing threshold value Y0, output RE1 is low level, and otherwise RE1 is high level；RE1 is that low level is effective.RE1 can also select height
Level is effective.
Fig. 8 is rest-set flip-flop embodiment.In Fig. 8, NAND gate FA8, FA9 composition rest-set flip-flop, the first set signal SE1 and
The second equal low levels of set signal RE1 are effective.When SE1 is effective, RE1 is invalid, the output arteries and veins that will be exported from in-phase output end FA8
Rush P2 and be set to 1；When SE1 is invalid, RE1 is effective, output pulse P2 is set to 0；As SE1 and RE1 invalid, output pulse P2's
State is constant.Rest-set flip-flop can also use the rest-set flip-flop of other forms.
It is same phase relation between output pulse P2 and input pulse P1 in Fig. 8.If output pulse P2 is changed to from anti-phase defeated
Go out end, i.e. NAND gate FA9 outputs, then function is changed into, and when SE1 is effective, RE1 is invalid, output pulse P2 is set into 0；Work as SE1
It is invalid, when RE1 is effective, output pulse P2 is set to 1；As SE1 and RE1 invalid, output pulse P2 state is constant；Now
It is inverted relationship between output pulse P2 and input pulse P1.
Fig. 9 is oscillator embodiment.In Fig. 9, CMOS NOT gates FN6 and FN7, resistance R91, electric capacity C91 composition multi-harmonic-oscillations
Device, sample clock pulse CLK export from FN7 output end, and CLK frequency can be by adjusting resistance R91, electric capacity C91 value
To change.Oscillator can also be realized using other kinds of multivibrator.
In above-mentioned N=5 embodiment, compare threshold value Y0 values for 4.When 1 number statistical value Y1 of sampled value is more than or equal to 4
When, output SE1 is effective, and output pulse P2 is set into 1, and its essence is when the number of " 1 " in 5 bit sequence data X1 is more than or equal to 4
When, output SE1 is effective, and output pulse P2 is set into 1；When 0 number statistical value Y2 of sampled value is more than or equal to 4, output RE1 has
Effect, output pulse P2 is set to 0, its essence is when the number of " 0 " in 5 bit sequence data X1 is more than or equal to 4, output RE1 is
Effectively, output pulse P2 is set to 0.Due to comparing threshold value Y0 for the integer more than N/2 and less than or equal to N, the first set signal
SE1 and the second set signal RE1 can not possibly effectively simultaneously, and therefore, the output of rest-set flip-flop is not in that logic state is not known
Situation.
Input/output pulse anti-jamming effectiveness schematic diagram when Figure 10 is N=5.15 sample clock pulses are given in Figure 10
CLK is to input pulse P1 sampled result, and obtained output pulse P2.If sampled in Fig. 10 before CLK sampled point 1
5 obtained sequence data X1 sampled values are 0, and output pulse P2 is 0.In Figure 10, sampled points 3 of the input pulse P1 in CLK
It is preceding to there is positive pulse interference after sampled point 4, cause X1 to obtain interference sample value 1 in sampled point 3, the sampling of sampled point 4；Input
Pulse P1 CLK sampled point 5 to occurring positive narrow pulse interference between sampled point 6, but the positive narrow pulse width is less than sampling
Cycle and between 2 sampled points, sequence data X1 sampled result is not influenceed, i.e. it is just narrow to have filtered out this automatically for sampling process
Impulse disturbances.Input pulse P1 starts to become 1 from 0 after CLK sampled point 8, and 2 edges occur during 0 change 1 trembles
Dynamic, 2nd therein positive burst pulse shaking interference is sampled process and filtered out automatically, sampled point 9, the value of sampled point 10 be respectively 1,
0.In Figure 10, sequence data X1 is 0011 in the sampled value that sample clock pulse CLK sampled point 1 obtains to sampled point 15
0 0 0 0 1 0 1 1 1 1 1.If Y0 values are 4, the situation of several sampled points is observed, in sampled point 3, Y1 is equal to 1, Y2 etc.
It is effective in 4, RE1, P2 0；In sampled point 4, Y1 is equal to 2, Y2 and is equal to 3, and SE1, RE1 are invalid, and P2 is maintained 0；In sampled point
5, Y1, which are equal to 2, Y2, is equal to 3, and SE1, RE1 are invalid, and P2 is maintained 0；In sampled point 6, Y1 is equal to 2, Y2 and is equal to 3, and SE1, RE1 are equal
Invalid, P2 is maintained 0；In sampled point 7, Y1 is equal to 2, Y2 and is equal to 3, and SE1, RE1 are invalid, and P2 is maintained 0；In sampled point 8, Y1
It is effective equal to 4, RE1 equal to 1, Y2, P2 0；In sampled point 12, Y1 is equal to 3, Y2 and is equal to 2, and SE1, RE1 are invalid, and P2 is maintained
0；, the P2 1 effective equal to 1, SE1 equal to 4, Y2 in sampled point 13, Y1；Obviously, in continuous 5 sequence datas X1 values, directly
To Figure 10 sampled point 13, just meet that the number of " 1 " in 5 bit sequence data X1 is more than or equal to 4 condition, the first set signal
SE1 is effective, and output pulse P2 becomes 1 by 0.In sampled point 14 to sampled point 15, the number for being satisfied by X1 " 1 " is more than or equal to 4
Condition, the first set signal SE1 remain effective.
What Figure 10 was provided is anti-positive pulse interference effect of the anti-jamming circuit unit when input pulse P1 is 0, and defeated
Enter condition and process that pulse P1 is changed into 1 from 0.Due to the symmetry of circuit, anti-jamming circuit unit is when input pulse P1 is 1
Anti- negative pulse interference effect, and input pulse P1 is changed into 0 condition and process from 1, when with input pulse P1 being 0 it is anti-just
Impulse disturbances effect, and input pulse P1 be changed into from 01 condition it is identical with process.It is located at adopting for sample clock pulse CCLK
CLK is 1 to input pulse P1 5 sampled values before sampling point 31, and output pulse P2 is 1, and sampled point 31 to sampled point 45 is adopted
1 N bit sequence data X1, sampled value number statistical value Y1 and output pulse P2 that sample obtains are shown in Table 1,0 number statistical value of sampled value
Y2 is equal to 5-Y1 (5 subtract Y1).
The sampled point 31-45 of table 11 N bit sequence data X1, sampled value number statistical value Y1 and output pulse P2
The situation of sampled point in table 1 is observed, is more than or equal to Y0 in sampled point 31-32, Y1, SE1 is effective, and RE1 is invalid, P2 quilts
It is set to 1；In sampled point 33-41, Y1 is less than Y0 and Y2 is less than Y0, and SE1, RE1 are invalid, and P2 is maintained 1；In sampled point 42-45,
Y2 is more than or equal to Y0, and RE1 is effective, and SE1 is invalid, and P2 is set to 0.
By export be same phase relation between pulse P2 and input pulse P1 exemplified by be described further.Anti-jamming circuit list
The course of work of member is, when the number of " 1 " in Y1 >=Y0, i.e. sequence data X1 is more than or equal to Y0, output pulse P2 is set to
1；When the number of " 0 " in Y2 >=Y0, i.e. sequence data X1 is more than or equal to Y0, output pulse P2 is set to 0.Due to comparing threshold value
Y0 is the integer more than N/2 and less than or equal to N, and therefore, the number of " 1 " is more than or equal to Y0 and sequence data X1 in sequence data X1
In the number of " 0 " be more than or equal to Y0 this 2 conditions and will not be met simultaneously.When input pulse P1, output pulse P2 are 0,
In the sampling of continuous n times, as long as single or multiple positive pulses disturb the sampled result to be formed not cause in sequence data X1 " 1 "
Number be more than wait Y0, then export pulse P2 will not be changed into 1；When input pulse P1, output pulse P2 are 1, adopted in continuous n times
In sample, as long as single or multiple negative pulses disturb the sampled result to be formed not cause in sequence data X1 the number of " 0 " to be more than
Equal to Y0, then 0 will not be changed into by exporting pulse P2.When P1, P2 are low level, as long as the positive pulse occurred in P1 makes continuously
Have in N number of P1 sampled values more than or equal to Y0 when being 1, the positive pulse corresponding with positive pulse in the P1 can be exported from P2；When
When P1, P2 are high level, as long as it is 0 that the negative pulse occurred in P1, which makes in continuous N number of P1 sampled values to have more than or equal to Y0,
When, the negative pulse corresponding with negative pulse in the P1 can be exported from P2.When input pulse P1 has been changed into 1 via 0, or by
1 is changed into after 0, and output pulse P2 needs the number of " 1 " in sequence data X1 to be more than or equal in Y0, or sequence data X1
The number of " 0 " is more than or equal to after Y0 conditions satisfaction, output pulse P2 just is become into 1 from 0, or will export pulse P2 and become from 1
0, there is the delay in several sampling pulse cycles.When value becomes big to Y0 in span, anti-jamming circuit unit will export arteries and veins
Rush P2 and become 1 from 0, and it is harsher from the condition of 1 change 0, and anti-jamming effectiveness is more preferable, but exports pulse P2 relative to input pulse
P1 time delay is bigger；When value becomes small to Y0 in span, anti-jamming circuit unit will export pulse P2 and become 1 from 0,
And broadened from the condition of 1 change 0, anti-jamming effectiveness diminishes, but exports pulse P2 and become relative to input pulse P1 time delay
It is small.When N value becomes big, anti-jamming circuit unit will export pulse P2 and become 1 from 0, and become strict from the condition of 1 change 0, resist
Interference effect improves, but exports pulse P2 and become big relative to input pulse P1 time delay；When N value becomes small, resist dry
Disturb circuit unit and output pulse P2 is become 1 from 0, and broadened from the condition of 1 change 0, anti-jamming effectiveness diminishes, but exports pulse P2
Time delay relative to input pulse P1 diminishes.
The cycle of sample clock pulse will be according to anti-interference input pulse P1 pulse width, pace of change and disturbing pulse
Width determine.Because in vehicle entrucking counting control system, the transport angles of entrucking goods differ, partial cargo, such as water
Mud bag etc. also has situations such as deformation, may be narrow in the forward position of count pulse, rear edge generation shaking interference when passing through optoelectronic switch
Pulse.According to the speed of service of transmission belt and the size of entrucking goods, effective count pulse width of formation in 200ms extremely
1000ms, and caused narrow disturbing pulse is less than 1/10th of corresponding effectively count pulse width.Therefore, sample clock pulse
Cycle selected in 30ms between 40ms, N values in the range of 3 to 7.
1 L roads anti-jamming circuit unit shift register, sampled value number counter, 0 number counter of sampled value, compare
Whole in threshold setting device, the first digital comparator, second value comparator, rest-set flip-flop, oscillator, or part work(
PAL, GAL, CPLD, FPGA, or other PLDs, logic unit can be used to realize.
During L=2,2 tunnel entrucking belt conveyors by 2 motors in 2 tunnel entrucking belt driver elements 11 and its
Motor-drive circuit is driven.
Human and machine interface unit 12 be used for set treat entrucking count goods quantity, display treat entrucking count goods quantity and
Remaining entrucking counts the quantity of goods, and the operation for starting 2 tunnel entrucking belt conveyors starts entrucking etc..Human and machine interface unit 12
It is preferred that touch-screen, can also select other input equipments, such as button, keyboard, BCD dial-up dish etc., and selection others
Output Display Unit, for example, liquid crystal display, light-emitting diode display etc..Controller unit 10 selects PLC in Fig. 1 embodiments.Controller
Unit can also select other controllers such as single-chip microcomputer, ARM.According to being actually needed for loading system, vehicle entrucking tally control
System can also include being used for system control with managing upper industrial computer.
It is the routine techniques that those skilled in the art are grasped in addition to the technical characteristic described in specification.For example, according to
Entrucking belt conveyor is actually needed in loading system, selects the motor in entrucking belt driver element, designs phase
The motor-drive circuit answered realizes corresponding function；According to being actually needed for loading system, select human and machine interface unit and with control
Device unit processed, which is attached, realizes corresponding function；Selection control unit is simultaneously designed to its peripheral circuit, interface circuit,
Realize corresponding function；Etc., it is the routine techniques that those skilled in the art are grasped.
Claims (9)
- A kind of 1. vehicle entrucking counting control system, it is characterised in that：Resist including controller unit, human and machine interface unit, L roads entrucking belt driver element, L roads count signal generation unit, L roads Disturb circuit unit；Entrucking belt driver element in L roads is connected with controller unit, for driving entrucking belt conveyor in L roads to run；Human and machine interface unit is connected with controller unit, for setting and showing entrucking quantity, start L road entruckings Belt Conveying dress Put operation and start entrucking；L roads count signal generation unit branch is arranged on L roads entrucking belt conveyor, is produced respectively and is exported the counting of L roads Inceptive impulse；L roads count the input pulse end that inceptive impulse delivers to L roads anti-jamming circuit unit respectively；L roads anti-jamming circuit list The output pulse ends of member are connected to controller unit；After starting the operation beginning entrucking of L road entruckings belt conveyor, controller unit is defeated according to L roads anti-jamming circuit unit Go out pulse to count vehicle entrucking quantity, after the entrucking quantity for reaching setting, stop L road entruckings belt conveyor fortune OK；The L is the integer more than or equal to 1.
- 2. vehicle entrucking counting control system according to claim 1, it is characterised in that：L roads count signal produces Unit is optoelectronic switch sensor.
- 3. vehicle entrucking counting control system according to claim 1, it is characterised in that：The controller unit is to compile Cyclelog.
- 4. the vehicle entrucking counting control system according to any one of claim 1-3, it is characterised in that：The L roads resist It is same anti-jamming circuit unit to disturb circuit unit；The anti-jamming circuit unit includes 1 shift register, sampled value number counter, 0 number counter of sampled value, compared Threshold setting device, the first digital comparator, second value comparator, rest-set flip-flop, oscillator.
- 5. vehicle entrucking counting control system according to claim 4, it is characterised in that：Shift register includes serial defeated Enter end, N parallel-by-bits output end, sample clock pulse input, the serial input terminal of shift register is anti-jamming circuit unit Input pulse end, the N parallel-by-bit output end output sequence data of shift register；The input of 1 number counter of sampled value is Sequence data, export as 1 number statistical value of sampled value；The input of 0 number counter of sampled value is sequence data, is exported as sampling 0 number statistical value of value；The output for comparing threshold setting device is to compare threshold value；The input of first digital comparator is sampled value 1 Count statistical value and compare threshold value, export as the first set signal；The input of second value comparator is 0 number statistical value of sampled value With compare threshold value, export as the second set signal；The input of rest-set flip-flop is the first set signal and the second set signal, is exported Hold the output pulse ends for anti-jamming circuit unit；Oscillator exports sample clock pulse；The sequence data is nearest n times sampled value of the shift register at sample clock pulse edge to input pulse, described Sampled value is binary data data 0 or 1, and the N is the integer more than or equal to 2.
- 6. vehicle entrucking counting control system according to claim 5, it is characterised in that：The relatively threshold value is more than N/ 2 and less than or equal to N integer.
- 7. vehicle entrucking counting control system according to claim 6, it is characterised in that：Described 1 number statistics of sampled value The function of device is that 1 number statistical value of sampled value of output is the quantitative value of the number of " 1 " in the sequence data inputted；It is described to adopt The function of 0 number counter of sample value is that 0 number statistical value of sampled value of output is the number of " 0 " in the sequence data of input Quantitative value.
- 8. vehicle entrucking counting control system according to claim 6, it is characterised in that：First digital comparator Function is that, when 1 number statistical value of sampled value, which is more than or equal to, compares threshold value, the first set signal of output is effective, otherwise exports The first set invalidating signal；The function of the second value comparator is compared when 0 number statistical value of sampled value is more than or equal to During threshold value, the second set signal of output is effective, the second set invalidating signal otherwise exported.
- 9. vehicle entrucking counting control system according to claim 8, it is characterised in that：First set signal triggers for RS The set signal of device, the second set signal are the reset signal of rest-set flip-flop；Export in-phase output end of the pulse from rest-set flip-flop Output, export pulse or exported from the reversed-phase output of rest-set flip-flop.
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| CN201711133999.7A CN107862371B (en) | 2017-11-16 | 2017-11-16 | Vehicle loading counting control system |
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