CN107833567A - Display based on FPGA and signal switching and parameter configuration method thereof - Google Patents
Display based on FPGA and signal switching and parameter configuration method thereof Download PDFInfo
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- CN107833567A CN107833567A CN201711025203.6A CN201711025203A CN107833567A CN 107833567 A CN107833567 A CN 107833567A CN 201711025203 A CN201711025203 A CN 201711025203A CN 107833567 A CN107833567 A CN 107833567A
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- 230000000694 effects Effects 0.000 claims description 6
- 238000005070 sampling Methods 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims 1
- 230000003044 adaptive effect Effects 0.000 description 5
- 238000010276 construction Methods 0.000 description 3
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- 238000005192 partition Methods 0.000 description 3
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
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Abstract
The invention provides a display based on an FPGA and a signal switching and parameter configuration method thereof, wherein parameters required to be configured of the FPGA are stored through a flash, the stored parameters in the flash are configured into the FPGA through an MCU, and a clksel signal of a P LL module is controlled to select an input clock of a P LL module, after the power-on, the FPGA needs to load a netlist file, after the netlist file is loaded, the MCU controls the clksel signal of the P LL module to select the input clock of the P LL module, firstly, a clock of an external crystal oscillator XAT L is selected as the input clock of the P LL module, after the MCU finishes the configuration of all the parameters, the MCU switches the input clock of the P LL module to a data recovery clock, and the data recovery clock is a data synchronization clock recovered by external data through a data receiving module.
Description
Technical field
The present invention relates to a kind of display based on FPGA and its signal switching method and method for parameter configuration, solve
The instability problem of FPGA parameter configurations, the precision of FPGA parameter configurations is added, shortens the available machine time, added and be
The stability of system.
Background technology
At present, domestic display has had below 5M and the special SOC circuit platforms of 8M displays, can meet from smaller screen to
The basic function demand of large screen display.But, can not due to there is no floating-point operation in SOC in terms of the special function of display
Carry out complicated DICOM (Digital Imaging and Communications in Medicine, i.e. Digital imaging in medicine
And communication) etc. criterion calculation, therefore can not realize DICOM built in display calibrate automatically, contrast enhancing, the consultation of doctors giant-screen show
The functions such as adaptive partition GAMMA, Demura for showing.Domestic medical producer is due to using SOC platform, without above-mentioned function,
The image quality and functional requirement of high-end display can not be met, can not also form the personality superiority and competitiveness of enterprise's display.
And the platform of the company such as leading BARCO, EZIO of display industry uses FPGA designed, designed algorithms, is respectively provided with this function.
In order to adapt to the display screen of various models, FPGA parameter be able to must be configured freely；Rapidly and accurately will
Quantity of parameters be configured in FPGA corresponding modules be display normal work premise.Therefore, it is necessary to designed for this problem
A solution.
The content of the invention
Technical problem solved by the invention is to provide a kind of display based on FPGA and its signal switching method and ginseng
Number collocation method, it can realize that DICOM built in display is calibrated automatically, contrast strengthens, the adaptive of large screen display of holding a consultation
The functions such as subregion GAMMA, Demura, and the parameter of each module can be configured rapidly and accurately in FPGA.
Technical scheme provided by the present invention is：
A kind of display based on FPGA, including flash, MCU, FPGA, crystal oscillator XATL and SOC；
The flash is used to deposit the parameter that FPGA needs to configure；MCU is used to storage parameter configuration to arrive in flash
FPGA register module (REG_WR), and during by controlling the clksel signals of PLL modules to select the input of PLL modules
Clock；
The crystal oscillator XATL is used to provide clock for FPGA electric initial stage over the display；
The SOC is connected with FPGA, for sending video signal data to FPGA；
FPGA carries out image with the vision signal received according to the parameter of configuration and shown.
Present invention also offers a kind of signal switching method of the display based on FPGA, the display shows for above-mentioned
Show device, its signal switching method is：
After upper electricity, FPGA needs to load net meter file, after net meter file has loaded, MCU control PLL modules
Clksel signals select the input clock of PLL modules；Input of the external crystal-controlled oscillation XATL clock as PLL modules is selected first
Clock；After MCU is by all parameter configurations, the input clock of PLL modules is switched to data recovery clock Clk_ by MCU
Phy, Clk_phy are the data sync clocks that external data is recovered by data reception module (RX_PHY).
Present invention also offers a kind of method for parameter configuration of the display based on FPGA, comprise the following steps
After upper electricity, FPGA needs to load net meter file, after net meter file has loaded, MCU control PLL modules
Clksel signals select the input clock of PLL modules；Input of the external crystal-controlled oscillation XATL clock as PLL modules is selected first
Clock；By MCU by the parameter configuration being stored in flash into FPGA；
After MCU is by all parameter configurations, the input clock of PLL modules is switched to data recovery clock by MCU
Clk_phy, Clk_phy clock are the data sync clocks that external data is gone out by RX_PHY module recoverys；
After input clock has been switched, PLL modules are resetted, after waiting the locking of PLL modules, lock letters can be sent out
Number, represent the clock stables of input and output；After MCU receives the lock signals of PLL modules, to the functional module in FPGA
(Function Module) solution resets, and the module formally enters mode of operation, now register module (REG_WR) and function mould
The sampling clock of block (Function Module) is synchronous with the clock that soc sends data；Parameters and reception of the FPGA according to configuration
The vision signal sent to SOC carries out image and shown；In image display status, FPGA parameter is configured by MCU, it is real
When watch and image quality effect and being debugged, shorten the construction cycle.
Beneficial effect：
A kind of display based on FPGA provided by the invention, can realize that DICOM built in display is calibrated, contrasted automatically
The functions such as degree strengthens, adaptive partition GAMMA, Demura of consultation of doctors large screen display；
The signal switching method of display provided by the invention, at upper electric initial stage, external crystal-controlled oscillation XATL clock was selected to make
For the input clock of PLL modules, data recovery clock Clk_phy unstable state can be avoided；When MCU matches somebody with somebody all parameters
After putting, data recovery clock Clk_phy has stablized, and now the input clock of PLL modules is switched to data recovery by MCU
Clock Clk_phy, can guarantee that FPGA internal modules sampling clock sent with front end SOC data clock it is synchronous, ensure that data are adopted
The accuracy of sample.
The method for parameter configuration of the display of the offer of the present invention, at upper electric initial stage, using external crystal-controlled oscillation XATL clock
As the input clock of PLL modules, FPGA is configured according to the configuration parameter to be prestored in flash, parameter configuration it is quick and
Accurately；In image display status, using input clocks of the outer data recovery clock Clk_phy as PLL modules, pass through MCU pairs
FPGA parameter is configured, real-time viewing effect, this facilitate that the debugging of image quality effect, shortens the construction cycle；Calibration is accurate
True rate is high, reaches the level of International Medical industry-leading company, leads over the rival of domestic medical treatment, can be widely used for diagnosing
Display.
Brief description of the drawings
Fig. 1 is the present invention program；
Fig. 2 is existing conventional design layout.
Embodiment
The present invention is described in more detail below in conjunction with the drawings and specific embodiments.
The invention discloses a kind of display based on FPGA and its signal switching and method for parameter configuration, display to include
Flash, MCU, FPGA, crystal oscillator XATL and SOC；
The parameter that FPGA needs to configure is stored in plug-in flash, and after upper electricity, parameter configuration is arrived into FPGA's by MCU
Register module REG_WR；
After upper electricity, FPGA needs to load net meter file, takes around 500ms or so；
After net meter file has loaded, the clksel signals of MCU control PLL modules select the input clock of PLL modules；
As shown in figure 1, input clock of the external crystal-controlled oscillation XATL clock as PLL modules is selected first；Clock line such as Fig. 1 red institute
Show.At upper electric initial stage, the clock stable from external crystal-controlled oscillation XATL, clock transfer was given to each module by PLL modules, it is ensured that
Each module normal work in FPGA；
After MCU is by all parameter configurations, the input clock of PLL modules is switched to data recovery clock by MCU
Clk_phy, Clk_phy are the data sync clocks that external data is gone out by RX_PHY module recoverys.
As shown in figure 1, Clk_phy clock is the data sync clock that external data is gone out by RX_PHY module recoverys；
FPGA video signal data comes from SOC, can just send stable data after needing initialization after the upper electricity of SOC, initially
The time of change is determined by the number of initialization data.Which results in data recovery clock Clk_phy after power-up not
Certainty.And the present invention uses external crystal-controlled oscillation clock to avoid data recovery clock Clk_phy not as work clock first
Stable state.FPGA transmits data configuration parameter by I2C, in the present embodiment configuration complete all parameters need 3.6S when
Between.According to test and producer's parameter, now data recovery clock Clk_phy stablized.If do not switch back into data syn-chronization
Clock, can cause FPGA internal modules sampling clock sent with front end SOC data clock it is asynchronous, cause data sampling mistake.
Because the switching of clock can cause the losing lock of PLL modules, after input clock has been switched, to PLL modules
(reset is the basic skills for locking PLL modules) is resetted, after waiting the locking of PLL modules, lock signals can be sent out, represented
The clock stable of input and output；It is (including adaptive to Function Module after MCU receives the lock signals of PLL modules
Answer subregion GAMMA, Demura module etc.) solution reset (release and reset operation, make it be operated in normal condition), the module is formal
Into mode of operation, now the sampling clock of REG_WR modules and Function Module modules and SOC send the clock of data
It is synchronous；FPGA parameter can be configured by MCU, real-time viewing effect, this facilitate that image quality in image display status
The debugging of effect, shortens the construction cycle., can should by adjusting the parameter of the modules such as adaptive partition GAMMA, Demura
System is very easily transplanted in other schemes.
As shown in Fig. 2 being conventional design layout, upper electric initial stage, the stabilization time of SOC signals does not know, the number parsed
It is unstable according to synchronised clock clk_phy.FPGA parameter configurations malfunction after causing electricity, the wrong phenomenons such as flower screen, blank screen occur.
Technical scheme provided by the invention solves the instability problem of FPGA parameter configurations, adds FPGA parameters and matches somebody with somebody
The precision put；Available machine time=loading netlist time (500ms)+SOC signal stabilization times in conventional scheme are (rule of thumb
Value is set as 3s)+parameter configuration the time (3.6s), and in the present invention, while parameter configuration, signal tends towards stability, and saves
The waiting signal stable time, so available machine time=loading netlist time (500ms)+parameter configuration time in the present invention
(3.6s), it is thus of the invention to shorten the available machine time relative to conventional design layout, add the stability of system.
Claims (3)
1. a kind of display based on FPGA, it is characterised in that including flash, MCU, FPGA, crystal oscillator XATL and SOC；
The flash is used to deposit the parameter that FPGA needs to configure；MCU is used to storage parameter configuration to arrive FPGA's in flash
Register module, and select the input clock of PLL modules by controlling the clksel signals of PLL modules；
The crystal oscillator XATL is used to provide clock for FPGA electric initial stage over the display；
The SOC is connected with FPGA, for sending video signal data to FPGA；
FPGA carries out image with the vision signal received according to the parameter of configuration and shown.
2. a kind of signal switching method of the display based on FPGA, the display is above-mentioned display, and its signal switches
Method is：
After upper electricity, FPGA needs to load net meter file, after net meter file has loaded, the clksel letters of MCU control PLL modules
Number select the input clock of PLL modules；Input clock of the crystal oscillator XATL clock as PLL modules is selected first；When MCU will
After all parameter configurations, the input clock of PLL modules is switched to data recovery clock Clk_phy, Clk_phy by MCU is
The data sync clock that external data is recovered by data reception module.
3. a kind of method for parameter configuration of the display based on FPGA, comprises the following steps
After upper electricity, FPGA needs to load net meter file, after net meter file has loaded, the clksel letters of MCU control PLL modules
Number select the input clock of PLL modules；Input clock of the external crystal-controlled oscillation XATL clock as PLL modules is selected first；It is logical
MCU is crossed by the parameter configuration being stored in flash into FPGA；
After MCU is by all parameter configurations, the input clock of PLL modules is switched to data recovery clock Clk_ by MCU
Phy, Clk_phy clock are the data sync clocks that external data is gone out by RX_PHY module recoverys；
After input clock has been switched, PLL modules are resetted, after waiting the locking of PLL modules, lock signals can be sent out,
Represent the clock stable of input and output；After MCU receives the lock signals of PLL modules, the functional module in FPGA is demultiplexed
Position, the module formally enters mode of operation, now register module and the sampling clock of functional module and soc send data when
Clock is synchronous；FPGA carries out image with the vision signal for receiving SOC transmissions according to the parameter of configuration and shown；Shape is shown in image
State, FPGA parameter is configured by MCU, watch image quality effect in real time and debugged.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711025203.6A CN107833567A (en) | 2017-10-27 | 2017-10-27 | Display based on FPGA and signal switching and parameter configuration method thereof |
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| CN201711025203.6A CN107833567A (en) | 2017-10-27 | 2017-10-27 | Display based on FPGA and signal switching and parameter configuration method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108733404A (en) * | 2018-05-28 | 2018-11-02 | 电子科技大学 | A kind of accurate reverse engineering approach for FPGA firmwares |
| CN108898995A (en) * | 2018-08-14 | 2018-11-27 | 安徽世阳光电有限公司 | A kind of display without adjusting screen |
| CN110719373A (en) * | 2019-09-16 | 2020-01-21 | 烽火通信科技股份有限公司 | Anti-hang-up xDSL system and method |
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Application publication date: 20180323 |