CN107861896A - A kind of display system and its display methods - Google Patents
A kind of display system and its display methods Download PDFInfo
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- CN107861896A CN107861896A CN201610840474.6A CN201610840474A CN107861896A CN 107861896 A CN107861896 A CN 107861896A CN 201610840474 A CN201610840474 A CN 201610840474A CN 107861896 A CN107861896 A CN 107861896A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
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Abstract
The invention discloses a kind of display system and its display methods, the display system includes display；SOC, for providing the 3rd signal；Fpga chip, SOC and display are coupled to, secondary signal is produced for producing the first signal and processing being carried out to the 3rd signal；Controller, fpga chip is coupled to, for the working condition according to fpga chip, selection sends signal by the first path of fpga chip or the second path；Wherein, after fpga chip loads netlist, controller selection sends the first signal by first path to display, display is shown the picture corresponding to the first signal；After the completion of the data processing function configuration of fpga chip, controller selection sends secondary signal by the second path to display, display is shown the picture corresponding to secondary signal.The present invention can gate different signal transmission paths and send vision signal to display order, can significantly shorten blank screen stand-by period and available machine time, improve the experience of user.
Description
Technical field
The invention belongs to display technology field, more particularly to a kind of display system and its display methods.
Background technology
What the independent SOC circuit platform of medical display generally use and SOC+fpga chip combined at present is flat
Platform.
Although it can individually meet the basic function demand of display using the display of SOC, in medical display
In terms of special function, as the DICOM of diagnostic display unit is corrected automatically, contrast strengthens, the adaptive of large screen display of holding a consultation
The functions such as subregion GAMMA, Demura can not all be realized on SOC, it is impossible to meet the image quality and function need of advanced medical display
Ask.
The function that numerous SOCs can not be realized has been transplanted to by FPGA using the display of SOC and fpga chip
Realized in chip, shorten the time of SOC initialization.The LOGO display interfaces of medical display are by SOC
One subprogram is controlled, but the principal element that actual influence LOGO is shown is fpga chip.
Due to including the functional modules such as substantial amounts of functional processing module, dicom, cps, demura inside FPGA design,
Need substantial amounts of parameter to be configured before the work of these functional modules, according to different screens, in advance calculate substantial amounts of data
It is good, then it is stored in flash, when FPGA works, MCU takes out data from flash, by spi bus, is configured to FPGA
In.The SPI trouble free services clock for the MCU that present scheme uses is 5.3Mhz, configures the parameter needs of all FPGA modules
Time be 3.6s, the FPGA netlist file load time is about 500ms, thus FPGA prepare good berth the theoretical shortest time
For 4.1s., all can having time interval between every instruction transmission in order to ensure the stability of the transmission of signal.According to above-mentioned Fig. 1
Shown traditional starting procedure and operation, 7s is needed altogether from upper electricity to display LOGO.This means about 7s is shown after start
Device is in black state, and LOGO shows time 3s, so working interface takes around 10s from starting shooting to showing.This will bring
The Consumer's Experience that client is mutually on duty.
The content of the invention
The problem of existing for prior art, it is an object of the invention to provide one kind can shorten the blank screen stand-by period,
Available machine time, the display system and its display methods for improving Consumer's Experience.
Other characteristics and advantage of the disclosure will be apparent from by following detailed description, or partially by the disclosure
Practice and acquistion.
According to an aspect of this disclosure, there is provided a kind of display system, including：
Display；
SOC, for providing the 3rd signal；
Fpga chip, the SOC and the display are coupled to, for producing the first signal and believing the described 3rd
Number carry out processing and produce secondary signal；
Controller, the fpga chip is coupled to, for the working condition according to the fpga chip, selection passes through described
The first path of fpga chip or the second path send signal；
Wherein, after the fpga chip loads netlist, controller selection is by the first path to institute
State display and send first signal, the display is shown the picture corresponding to first signal；As the FPGA
After the completion of the data processing function configuration of chip, the controller selection sends institute by second path to the display
Secondary signal is stated, the display is shown the picture corresponding to the secondary signal.
In a kind of exemplary embodiment of the disclosure, the picture corresponding to first signal is LOGO pictures or pure color
Picture, the picture corresponding to the secondary signal are host work picture.
In a kind of exemplary embodiment of the disclosure, the fpga chip also includes：
Interface module, the 3rd signal sent for receiving the SOC；
Image processing module, the 3rd signal transferred for receiving the interface module, and to the 3rd signal
Corresponding data are handled, to produce the secondary signal；
Figure module, after loading netlist when the fpga chip, produce first signal.
In a kind of exemplary embodiment of the disclosure, first signal includes clock signal and RGB data signal；Institute
Stating figure module includes：
Counting unit, for being counted according to clock；
Timing generation unit, according to the count information of the counting unit, produce the clock signal；
Data generating unit, according to the clock signal and the count information, produce the RGB data signal.
In a kind of exemplary embodiment of the disclosure, after the completion of the interface module configuration of the fpga chip,
The controller selection sends the 3rd signal by the 3rd path of the fpga chip to the display, makes described aobvious
Show that device shows the picture corresponding to the 3rd signal.
In a kind of exemplary embodiment of the disclosure, the figure module is coupled to the display and forms described first
Path；Described image processing module is coupled to the display and forms second path；The interface module is coupled to described
Display forms the 3rd path.
According to an aspect of this disclosure, there is provided a kind of display methods of display system, the display system include SOC cores
Piece, fpga chip, controller and display, the display methods include：
The netlist for carrying out the fpga chip simultaneously is controlled to load by the controller initial with the SOC
Change；
After the fpga chip loads netlist, the first signal is produced by the fpga chip, and described in transmission
First signal is to the display；
The picture corresponding to first signal is shown in the display while configures the interface work(of the fpga chip
Energy and data processing function；
After the completion of the data processing function configuration of the fpga chip, by the fpga chip to the SOC
The 3rd signal transacting sent produces secondary signal；
Being controlled by the controller switches to the secondary signal to send to the display first signal.
In a kind of exemplary embodiment of the disclosure, after the completion of the data processing function configuration of the fpga chip,
Producing secondary signal to the 3rd signal transacting by the fpga chip includes：
After the completion of the data processing function configuration of the fpga chip, the SOC and the fpga chip are established
Connection；
3rd signal is sent to the fpga chip by the SOC；
The secondary signal is produced to the 3rd signal transacting of reception by the fpga chip.
In a kind of exemplary embodiment of the disclosure, after the fpga chip loads netlist, by described
Fpga chip, which produces the first signal, to be included：
After the fpga chip loads netlist, counted according to clock；
According to the count information of clock, clock signal is produced；
According to the clock signal and the count information, the RGB data signal is produced；And
The clock signal and the RGB data signal are combined, produces first signal.
According to an aspect of this disclosure, there is provided a kind of display methods of display system, the display system include SOC cores
Piece, fpga chip, controller and display, the display methods include：
The netlist for carrying out the fpga chip simultaneously is controlled to load by the controller initial with the SOC
Change；
After the fpga chip loads netlist, the first signal is produced by the fpga chip, and described in transmission
First signal is to the display；
The picture corresponding to first signal is shown in the display while configures the interface work(of the fpga chip
Energy；
After the completion of the interface function configuration of the fpga chip, the 3rd signal that the SOC is sent is received；
Being controlled by the controller switches to the 3rd signal to send to the display first signal.
In a kind of exemplary embodiment of the disclosure, in addition to：
The data processing function of the fpga chip is configured while the interface function for configuring the fpga chip；Wherein match somebody with somebody
The time required to being more than the interface function for configuring the fpga chip the time required to putting the data processing function of the fpga chip；
After the completion of the data processing function configuration of the fpga chip, by the fpga chip to the SOC
The 3rd signal transacting sent produces secondary signal；
Being controlled by the controller switches to the secondary signal to send to the display the 3rd signal.
The time required to the present invention is according to each module work in fpga chip, different signal transmission paths is gated to display
Order sends vision signal, can significantly shorten system boot and show needed for LOGO pictures, blue picture and host work picture
Time, improve the experience of user.
It should be appreciated that the general description and following detailed description of the above are only exemplary, this can not be limited
It is open.
Brief description of the drawings
Its example embodiment is described in detail by referring to accompanying drawing, above and other target, feature and the advantage of the disclosure will
Become more fully apparent.
Fig. 1 shows the flow chart of prior art startup display method；
Fig. 2 schematically shows the structural representation of the display system according to disclosure example embodiment；
Fig. 3 schematically shows the structural representation of the display system according to the embodiment of the disclosure one；
Fig. 4 schematically shows the structural representation of figure module in the display system according to the embodiment of the disclosure one；
Fig. 5 schematically shows the flow chart of the display methods according to the embodiment of the disclosure one；
Fig. 6 schematically shows the flow chart of the display methods according to the embodiment of the disclosure one；
Fig. 7 schematically shows the flow chart of the display methods according to one actual embodiment of the disclosure；
Fig. 8 schematically shows the flow chart of the display methods according to one actual embodiment of the disclosure.
Embodiment
Example embodiment is described more fully with referring now to accompanying drawing.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to example set forth herein；On the contrary, these embodiments are provided so that the disclosure will more
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Accompanying drawing is only the disclosure
Schematic illustrations, be not necessarily drawn to scale.Identical reference represents same or similar part in figure, thus
Repetition thereof will be omitted.
In addition, described feature, structure or characteristic can be incorporated in one or more implementations in any suitable manner
In mode.In the following description, there is provided many details fully understand so as to provide to embodiment of the present disclosure.So
And it will be appreciated by persons skilled in the art that the technical scheme of the disclosure can be put into practice and omit one in the specific detail
Or more, or other methods, constituent element, device, step etc. can be used.In other cases, it is not shown in detail or describes
Known features, method, apparatus, realization, material or operation are to avoid that a presumptuous guest usurps the role of the host and so that each side of the disclosure becomes mould
Paste.
Some block diagrams shown in accompanying drawing are functional entitys, not necessarily must be with physically or logically independent entity phase
It is corresponding.These functional entitys can be realized using software form, or in one or more hardware modules or integrated circuit in fact
These existing functional entitys, or these functions reality is realized in heterogeneous networks and/or processor device and/or microcontroller device
Body.
Fig. 2 schematically shows the structural representation of the display system according to disclosure example embodiment.
As shown in Fig. 2 the display system of the present invention, including display 10, fpga chip 20, controller 30 and SOC
40。
The major function of SOC 40 for provide multiple interfaces, with external host (not shown) and fpga chip
20 connections, external host is connected by the input interface that SOC 40 is provided with the input of SOC 40, and to SOC
40 send the 3rd signal SG3.After the completion of the power on configuration of SOC 40, the 3rd signal SG3 that external host is sent can be through
SOC 40 is transferred to fpga chip 20.
Fpga chip 20 is coupled between display 10 and SOC, and transmits vision signal to display 10.FPGA cores
Piece 20 can produce the first signal SG1 and secondary signal SG2, and under the control of the controller 30 optionally by the first signal
SG1 or secondary signal SG2 are sent to display 10, to show different pictures on display 10.SOC 40 is sent to
3rd signal SG3 of fpga chip 20 obtains secondary signal SG2 by processing.Wherein, the picture corresponding to the first signal SG1 can
Think LOGO pictures or pure color picture.Picture corresponding to secondary signal SG2 can be host work picture.Following examples will
Using picture corresponding to the first signal SG1 as LOGO pictures or blue picture, picture corresponding to secondary signal SG2 is drawn for host work
Illustrated exemplified by face, but the invention is not limited in this.For example, when controller control fpga chip 20 is selected the first signal
When SG1 is sent to display 10, blue picture is shown after LOGO pictures are shown on display 10.When controller controls fpga chip
When secondary signal SG2 is sent to display 10 by 20 selections, normal host work picture is shown on display 10.
Controller 30 is coupled to the fpga chip 20, and it can be MCU (micro-control unit), the present invention not as
Limit.Controller 30 can select to pass through corresponding signal in fpga chip 20 and pass according to the different working condition of fpga chip 20
Defeated path, corresponding vision signal is sent to display 10.Wherein, the working condition of fpga chip 20 adds including fpga chip 20
Contained network table is finished, the configuration of the data processing function of fpga chip is completed etc..Wherein, the working condition of fpga chip 20 can basis
The corresponding signal that controller 30 receives the feedback of fpga chip 20 is judged.After fpga chip 20 loads netlist, feedback
Judge signal to controller 30 1, for controller 30 after the judgement signal is received, selection passes through first path to the display
10 send the first signal SG1, display 10 is shown blue picture after showing LOGO pictures.When the data processing of fpga chip 20
After the completion of functional configuration, it can equally feed back to controller 30 1 and judge signal, controller 30 is after the judgement signal is received, selection
Secondary signal SG2 is sent to the display 10 by the second path, the display 10 is shown host work picture.
The process that fpga chip 20 loads netlist is that the mistake of each functional module in fpga chip 20 is built according to net meter file
Journey, such as interface module 201, image processing module 202, figure module 203, the work of figure module 203 are created according to net meter file
It is not as needing substantial amounts of parameter to be configured before the work of image processing module 202.Fpga chip 20 loads netlist and finished,
Then figure module 203 can work in basic representation fpga chip 20, and figure module 203 can produce the first signal SG1.FPGA
The time that chip 20 loads netlist generally only needs 500ms, that is to say, that in system boot about 500ms or so, in controller
First path under 30 control between figure module 203 and display 10 is strobed, the first signal caused by figure module 203
SG1 can be to be sent to display 10, it is possible to shows blue picture after showing LOGO pictures in the display 10, shortens
The blank screen stand-by period.In addition, before fpga chip 20 initially enters normal operating conditions, when no secondary signal SG2 is accessed
When show blue picture always, so effectively reduce inoperative power consumption.
The data processing function configuration process of fpga chip 20 mainly to image processing module 202, such as dicom,
The Parameter Configuration process of the functional modules such as cps, demura, with image processing module 202 it is dicom, cps in the present embodiment,
Illustrated exemplified by the functional modules such as demura, but the invention is not limited in this.Needed before the work of these functional modules big
The parameter of amount is configured, and according to different screens, is in advance calculated substantial amounts of data, is then stored in flash, FPGA cores
When piece 20 works, controller 30 takes out data from flash, by spi bus, is configured in fpga chip 20, configures institute
The time that the parameter for having the image processing module 202 of fpga chip needs is about 3.6s, and the net meter file of fpga chip 20 loads
Time is about 500ms, and while LOGO pictures are shown, controller 30 configures image processing module 202 in fpga chip 20
Supplemental characteristic.That is in system boot about 3.6s or so, the He of image processing module 202 under the control of the controller 30
The second path between display 10 is strobed, and the secondary signal SG2 that image processing module 202 exports can be aobvious to be sent to
Show device 10, it is possible to host work picture is shown in the display 10, the time required to shortening display host work picture.
The time required to the present embodiment is according to each module work in fpga chip, different signal transmission paths is gated to display
Device order sends the first signal SG1 and secondary signal SG2, can significantly shorten system boot and show LOGO pictures, blue picture
The time required to host work picture, the experience of user is improved.
In one embodiment, fpga chip 20 includes interface module 201, image processing module 202 and figure module 203.
Interface module 201 is used for the 3rd signal SG3 for receiving the transmission of SOC 40.Wherein, the 3rd signal SG3 is corresponding leads
Machine work picture, display 10 can show host work picture wherein after the 3rd signal SG3 is received.
Image processing module 202 is used for the 3rd signal SG3 that receiving interface module 201 transfers, and to the 3rd SG3 pairs of signal
The data answered are handled, to produce secondary signal SG2.
Figure module 203 is used to after fpga chip 20 loads netlist, produce the first signal SG1.
As shown in figure 4, figure module 203 includes counting unit 2031, timing generation unit 2032 and data generating unit
2033。
Wherein, first signal SG1 is by clock signal HS, VS, DE and RGB data signal caused by figure module 203
DATA is formed.The input of figure module 203 can be with incoming clock signal CLK, control signal REG_CTL and reset signal RST.
The MCU that control signal REG_CTL comes is used to control whether to start figure module 203.When fpga chip has loaded net meter file, just
A signal can be fed back to MCU, after MCU obtains the signal, will be sent out by control signal REG_CTL to figure module 203
Order, start figure module 203, export the first signal SG1.
Counting unit 2031 is used to be counted according to clock.Timing generation unit 2032 is according to the counting unit 2031
Count information, produce clock signal HS, VS, DE.Data generating unit 2033 is according to clock signal HS, VS, DE and the meter
Number information, produces RGB data signal DATA.Clock signal HS, VS, DE and RGB data signal DATA can form LOGO figure and
Blueness figure.
Fig. 3 schematically shows the structural representation of the display system according to the practical embodiments of the disclosure one.As shown in figure 3,
The display system of the present invention, including display 10, fpga chip 20, controller 30 and SOC 40.
The major function of SOC 40 for provide multiple interfaces, with external host (not shown) and fpga chip
20 connections, external host (not shown) are connected by the input interface that SOC 40 is provided and the input of SOC 40
Connect, and the 3rd signal SG3 is sent to SOC 40.The output interface and SOC that fpga chip 20 is provided by SOC 40
The output connection of chip 40.After the completion of the power on configuration of SOC 40, the 3rd signal SG3 that external host is sent can be through SOC
Chip 40 is transferred to interface module 201.Interface module 201 export the 3rd signal SG3 can under the control of the controller 30,
By the 3rd path of gating directly by access display 10, to show host work picture.
Due to being shorter than the time required to the parameter configuration of SOC 40 needed for image processing module 202 in fpga chip 20 configures
Time, the present embodiment can further shorten system boot to the time of display host work picture.
Fig. 5 schematically shows the flow chart of the display methods according to the embodiment of the disclosure one.
As shown in figure 5, the display methods of the present invention comprises the following steps：
Step S610：The netlist loading for carrying out the fpga chip simultaneously and the SOC cores are controlled by the controller
The initialization of piece.
Step S620：After the fpga chip loads netlist, the first signal is produced by the fpga chip, and
First signal is sent to the display.
Step S630：The picture corresponding to first signal is shown in the display while configures the fpga chip
Interface function and data processing function.
Step S640：After the completion of the data processing function configuration of the fpga chip, by the fpga chip to institute
The 3rd signal transacting for stating SOC transmission produces secondary signal.
Step S650：Being controlled by the controller switches to the secondary signal to send to described first signal
Display.
The display details of display methods elaborates in the display system of above-described embodiment in the present embodiment,
This is repeated no more.
Fig. 6 schematically shows the flow chart of the display methods according to the embodiment of the disclosure one.
As shown in fig. 6, the display methods of the present invention comprises the following steps：
Step S710：The netlist loading for carrying out the fpga chip simultaneously and the SOC cores are controlled by the controller
The initialization of piece.
Step S720：After the fpga chip loads netlist, the first signal is produced by the fpga chip, and
First signal is sent to the display.
Step S730：The picture corresponding to first signal is shown in the display while configures the fpga chip
Interface function.
Step S740：After the completion of the interface function configuration of the fpga chip, the SOC is sent the 3rd is received
Signal.The time required to configuration data processing function being usually shorter than the time required to fpga chip configuration interface function.
Step S750：Being controlled by the controller switches to the 3rd signal to send to described first signal
Display.
The present embodiment can further shorten system boot to display main frame work compared with the display methods of Fig. 5 embodiments
Make the time of picture.
In one embodiment, display methods of the invention also includes：
The data processing function of the fpga chip is configured while the interface function for configuring the fpga chip；
After the completion of the data processing function configuration of the fpga chip, by the fpga chip to the SOC
The 3rd signal transacting sent produces secondary signal；
Being controlled by the controller switches to the secondary signal to send to the display the 3rd signal.
Fig. 7 schematically shows the flow chart of the display methods according to one actual embodiment of the disclosure.
As shown in fig. 7, the display methods of the present invention includes：
1) netlist, the SOC loading procedure of the fpga chip are loaded；
2) data processing function of the fpga chip is configured by the controller；
3) after the fpga chip loads netlist, the first signal is produced by the fpga chip, and send institute
The first signal is stated to the display；
4) LOGO pictures and blue picture are shown by the display；
5) SOC sends data by the 3rd signal, and has detected whether that main frame accesses display；
6) when detected main frame access display, and the fpga chip data processing function configuration after the completion of, lead to
Cross the fpga chip and produce secondary signal, and switch to the secondary signal to send to the display first signal
Device, host work picture is shown by the display.If not detected that main frame accesses display, display continues
Show blue picture.
The real work flow of the present embodiment is：It is electric in start, FPGA loading net meter files, 500ms is taken around, is loaded
Complete can afterwards shows LOGO graph cards, is completed from upper electricity to display LOGO graph cards within 1s, when the design is by start blank screen
Between shorten to 1s or so.While LOGO is shown, MCU configures each module parameter data of FPGA, and FPGA prepares just after 3.6s
Thread.Meanwhile Soc chips enter line program loading and initialization after upper electricity, data company is carried out with Soc when FPGA configures achievement
Connect, if the unstable progress FPGA of connection RX ends (interface module) reset, during the entire process of reparation, FPGA function module
(FPGA image processing modules) is not connected to screen, the problem of avoiding screen flicker.Configured and the company of foundation in Soc and FPGA
While connecing, the first path of another " figure module+screen " is in display LOGO, after LOGO shows 3s, screen display blueness
Working interface.After Soc and FPGA, which is established, to be stably connected with, start normal operating conditions.When no any signal access
When show blue working interface always.After FPGA function module, which configures, to be completed, another " SOC+ image procossing is switched to
Second path of module+screen ", to show host work interface.
Fig. 8 schematically shows the flow chart of the display methods according to one actual embodiment of the disclosure.
As shown in figure 8, the display methods of the present invention includes：
1) netlist of the fpga chip is loaded by the controller；
2) interface function and data processing function of the fpga chip are configured by the controller；
3) after the fpga chip loads netlist, the first signal is produced by the fpga chip, and send institute
The first signal is stated to the display；
4) LOGO pictures and blue picture are shown by the display；
5) after the completion of the interface function configuration of the fpga chip, external host is switched to send first signal
To the 3rd signal of the fpga chip, and the 3rd signal is sent to the display；
6) host work picture is shown by the display, now the image real time transfer function in fpga chip can not
Use；
7) after the completion of the data processing function configuration of the fpga chip, the second letter is produced by the fpga chip
Number, and switch to the secondary signal to send to the display the 3rd signal；
8) host work picture is shown by the display, now the institute of fpga chip is functional can be used.
The real work flow of the present embodiment is：It is electric in start, FPGA loading net meter files, 500ms is taken around, is loaded
Complete can afterwards shows LOGO graph cards, is completed from upper electricity to display LOGO graph cards within 1s, when the design is by start blank screen
Between shorten to 1s or so.While LOGO is shown, MCU configures each module parameter data of FPGA, and FPGA prepares just after 3.6s
Thread.Meanwhile Soc chips enter line program loading and initialization after upper electricity, carried out when FPGA interface module configures achievement with Soc
Data connect, if the unstable progress FPGA of connection RX ends (interface module) reset, during the entire process of reparation, and FPGA functions
Module (FPGA image processing modules) is not connected to screen, the problem of avoiding screen flicker.Configured and built in Soc and FPGA
While vertical connection, the first path of another " figure module+screen " is in display LOGO, after LOGO shows 3s, screen display
The working interface of blueness.After Soc and FPGA, which is established, to be stably connected with, start normal operating conditions.When no any signal connects
Blue working interface is shown when entering always.After FPGA and SOC stable connections, switch to " SOC+ interface modules+screen "
3rd path, to show host work interface.After FPGA image processing modules, which configure, to be completed, switch to " at SOC+ images
Second path of reason module+screen ".
The processing of each step does not indicate that or limited the time sequencing of these processing in above-described embodiment.In addition, it is also easy to manage
Solution, these processing for example can be performed either synchronously or asynchronously in multiple modules.
Through the above description of the embodiments, those skilled in the art is it can be readily appreciated that example described herein is implemented
Mode can be realized by software, can also be realized by way of software combines necessary hardware.Therefore, according to the disclosure
The technical scheme of embodiment can be embodied in the form of software product, the software product can be stored in one it is non-volatile
Property storage medium (can be CD-ROM, USB flash disk, mobile hard disk etc.) in or network on, including some instructions are to cause a calculating
Equipment (can be personal computer, server, mobile terminal or network equipment etc.) is performed according to disclosure embodiment
Method.
The illustrative embodiments of the disclosure are particularly shown and described above.It should be appreciated that the disclosure is unlimited
In detailed construction described herein, set-up mode or implementation method；On the contrary, the disclosure is intended to cover included in appended claims
Spirit and scope in various modifications and equivalence setting.
Claims (10)
- A kind of 1. display system, it is characterised in that including：Display；SOC, for providing the 3rd signal；Fpga chip, the SOC and the display are coupled to, for producing the first signal and the 3rd signal being entered Row processing produces secondary signal；Controller, the fpga chip is coupled to, for the working condition according to the fpga chip, selection passes through the FPGA The first path of chip or the second path send signal；Wherein, after the fpga chip loads netlist, the controller selection is shown by the first path to described Show that device sends first signal, the display is shown the picture corresponding to first signal；When the fpga chip Data processing function configuration after the completion of, controller selection sends described the by second path to the display Binary signal, the display is set to show the picture corresponding to the secondary signal.
- 2. display system as claimed in claim 1, it is characterised in that the picture corresponding to first signal is LOGO pictures Or pure color picture, the picture corresponding to the secondary signal are host work picture.
- 3. display system as claimed in claim 1, it is characterised in that the fpga chip also includes：Interface module, the 3rd signal sent for receiving the SOC；Image processing module, the 3rd signal transferred for receiving the interface module, and it is corresponding to the 3rd signal Data handled, to produce the secondary signal；Figure module, after loading netlist when the fpga chip, produce first signal.
- 4. display system as claimed in claim 3, it is characterised in that first signal includes clock signal and RGB data Signal；The figure module includes：Counting unit, for being counted according to clock；Timing generation unit, according to the count information of the counting unit, produce the clock signal；Data generating unit, according to the clock signal and the count information, produce the RGB data signal.
- 5. display system as claimed in claim 3, it is characterised in that when the interface module of the fpga chip configures Cheng Hou, the controller selection send the 3rd signal to the display by the 3rd path of the fpga chip, made The display shows the picture corresponding to the 3rd signal.
- 6. display system as claimed in claim 5, it is characterised in that the figure module is coupled to the display and forms institute State first path；Described image processing module is coupled to the display and forms second path；The interface module coupling The 3rd path is formed in the display.
- 7. a kind of display methods of display system, the display system includes SOC, fpga chip, controller and display, Characterized in that, the display methods includes：The netlist loading and the initialization of the SOC for carrying out the fpga chip simultaneously are controlled by the controller；After the fpga chip loads netlist, the first signal is produced by the fpga chip, and send described first Signal is to the display；The display show the picture corresponding to first signal and meanwhile configure the fpga chip interface function and Data processing function；After the completion of the data processing function configuration of the fpga chip, the SOC is sent by the fpga chip The 3rd signal transacting produce secondary signal；Being controlled by the controller switches to the secondary signal to send to the display first signal.
- 8. the display methods of display system as claimed in claim 7, it is characterised in that when fpga chip loading netlist is complete Bi Hou, producing the first signal by the fpga chip includes：After the fpga chip loads netlist, counted according to clock；According to the count information of clock, clock signal is produced；According to the clock signal and the count information, the RGB data signal is produced；AndThe clock signal and the RGB data signal are combined, produces first signal.
- 9. a kind of display methods of display system, the display system includes SOC, fpga chip, controller and display, Characterized in that, the display methods includes：The netlist loading and the initialization of the SOC for carrying out the fpga chip simultaneously are controlled by the controller；After the fpga chip loads netlist, the first signal is produced by the fpga chip, and send described first Signal is to the display；The picture corresponding to first signal is shown in the display while configures the interface function of the fpga chip；After the completion of the interface function configuration of the fpga chip, the 3rd signal that the SOC is sent is received；Being controlled by the controller switches to the 3rd signal to send to the display first signal.
- 10. the display methods of display system as claimed in claim 9, it is characterised in that also include：The data processing function of the fpga chip is configured while the interface function for configuring the fpga chip；Wherein configure institute The time required to being more than the interface function for configuring the fpga chip the time required to stating the data processing function of fpga chip；After the completion of the data processing function configuration of the fpga chip, the SOC is sent by the fpga chip The 3rd signal transacting produce secondary signal；Being controlled by the controller switches to the secondary signal to send to the display the 3rd signal.
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Address after: 266100 Zhuzhou Road, Laoshan District, Shandong, No. 151, No. Patentee after: Hisense Visual Technology Co., Ltd. Address before: 266100 Zhuzhou Road, Laoshan District, Shandong, No. 151, No. Patentee before: QINGDAO HISENSE ELECTRONICS Co.,Ltd. |