CN113674704A

CN113674704A - Image display control method and device and display equipment

Info

Publication number: CN113674704A
Application number: CN202110941965.0A
Authority: CN
Inventors: 夏建龙; 王伟; 查林
Original assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Current assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Priority date: 2021-08-17
Filing date: 2021-08-17
Publication date: 2021-11-19

Abstract

The application discloses an image display control method and device and display equipment, which are used for shortening the time from power-on to image display of a product and improving user experience. The application provides a display control device, includes: the independent LOGO module is used for sending a preset image to the image data selection module after the device is powered on; the image data selection module is used for selecting to send the preset image sent by the independent LOGO module to a display screen for display through the sending module under the control of the MCU when the initialization of the input equipment is not finished; the input equipment is used for being connected with the display control device and displaying the input video image through the display screen through the display control device.

Description

Image display control method and device and display equipment

Technical Field

The present application relates to the field of electrical technologies, and in particular, to an image display control method and apparatus, and a display device.

Background

With the increasing consumption level, the cabin systems of automobiles are continuously upgraded, and particularly, display systems represented by large display screens are continuously optimized.

The display screen is used as a display terminal, only displays input signals of the front-end equipment and displays the input signals along with the input equipment. The front-end input device generally requires a relatively long initialization time at the initial power-on stage. During this period, the display screen generally waits for the initialization of the front-end input device to be completed in a black screen state, that is, after the system is powered on, the display screen displays images slowly, and the user experience is poor.

Disclosure of Invention

The embodiment of the application provides an image display control method and device and display equipment, which are used for shortening the time from power-on to image display of a product and improving user experience.

An embodiment of the present application provides a display control apparatus, including:

the independent LOGO module is used for sending a preset image to the image data selection module after the device is powered on;

the image data selection module is used for selecting to send the preset image sent by the independent LOGO module to a display screen for display through the sending module under the control of the MCU when the initialization of the input equipment is not finished;

the input equipment is used for being connected with the display control device and displaying the input video image through the display screen through the display control device.

Sending a preset image to an image data selection module after the device is powered on through an independent LOGO module in the display control device; when the initialization of the input equipment is not completed, the image data selection module selects to send the preset image sent by the independent LOGO module to the display screen for display under the control of the MCU, so that the time from power-on to image display of a product is shortened, a user does not feel that the image displayed by the display screen is slow, and the user experience is improved.

Optionally, the method further comprises:

the independent backlight control module is used for sending backlight control data to the backlight data selection module after the device is powered on;

and the backlight data selection module is used for selecting and utilizing the backlight control data sent by the independent backlight control module to control the brightness of the backlight lamp under the control of the MCU when the initialization of the input equipment is not completed.

Optionally, the method further comprises:

the receiving module is used for receiving a low-voltage differential signal LVDS of the video image sent by the input equipment, analyzing a data synchronous clock from the LVDS, sending the data synchronous clock to the clock selection module, converting the LVDS into a video graphic array VGA signal and sending the video graphic array VGA signal to the backlight processing module;

the clock selection module is used for selecting an external crystal oscillator clock of the display control device as a rear-end working clock under the control of the MCU when the initialization of the input equipment is not completed; when the initialization of the input device is completed, under the control of the MCU, selecting the data synchronization clock sent by the receiving module as a back-end working clock, where the back-end includes: the backlight processing module, the independent LOGO module, the independent backlight control module and the sending module.

Optionally, the method further comprises:

and the time sequence detection module is used for detecting whether the time sequence signals analyzed by the receiving module are stable or not and informing the MCU of the detection result, if so, the MCU determines that the initialization of the input equipment is finished, otherwise, the MCU determines that the initialization of the input equipment is not finished.

Optionally, the method further comprises:

and the resetting module is used for resetting the modules in the display control device under the control of the MCU.

The display control system provided by the embodiment of the application comprises the display control device and the MCU.

The display equipment provided by the embodiment of the application comprises the display control device, a display screen, a backlight lamp and the MCU.

The display control method provided by the embodiment of the application comprises the following steps:

after the FPGA is electrified, sending a preset image to an image data selection module through an independent LOGO module arranged in the FPGA;

when the initialization of the input equipment is not finished, under the control of a Micro Control Unit (MCU), a preset image sent by the independent LOGO module is selected by an image data selection module and sent to a display screen for display by a sending module;

the input equipment is used for being connected with the FPGA and displaying input video images through a display screen through the FPGA.

Optionally, after the FPGA is powered on, the method further includes:

sending backlight control data to a backlight data selection module through an independent backlight control module arranged in the FPGA;

when the initialization of the input equipment is not finished, the backlight control data sent by the independent backlight control module is selected to control the brightness of the backlight lamp through the backlight data selection module arranged in the FPGA under the control of the MCU.

Optionally, the method further comprises:

receiving a low-voltage differential signal LVDS of a video image sent by the input equipment through a receiving module arranged in the FPGA, analyzing a data synchronous clock from the LVDS, sending the data synchronous clock to a clock selection module arranged in the FPGA, converting the LVDS into a VGA signal of a video graphic array, and sending the VGA signal to a backlight processing module arranged in the FPGA;

when the initialization of the input equipment is not completed, selecting an external crystal oscillator clock of the FPGA as a rear-end working clock by the clock selection module under the control of the MCU; when the initialization of the input device is completed, the clock selection module selects the data synchronization clock sent by the receiving module as a back-end working clock under the control of the MCU, and the back-end comprises: the backlight processing module, the independent LOGO module, the independent backlight control module and the sending module.

Another embodiment of the present application provides a computing device, which includes a memory and a processor, wherein the memory is used for storing program instructions, and the processor is used for calling the program instructions stored in the memory and executing any one of the above methods according to the obtained program.

Another embodiment of the present application provides a computer storage medium having stored thereon computer-executable instructions for causing a computer to perform any one of the methods described above.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram illustrating a specific architecture of a vehicle-mounted display according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a standalone LOGO module provided in an embodiment of the present application;

fig. 3 is a schematic diagram of an image reconstructed by the timing control module and displayed in an enlarged manner by the image enlarging module according to the embodiment of the application;

fig. 4 is a schematic view of an overall processing flow of image display control according to an embodiment of the present application;

fig. 5 is a schematic flowchart of an image display control method on the FPGA side according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The embodiment of the application can be applied to the display screen in the field of automobile cabins, and the backlight system of 576-partitioned Mini LED lamps is accurately controlled by adopting the backlight control technology based on the FPGA on the vehicle-mounted display screen, so that the picture contrast is improved, the gray scale number is increased, and the power consumption is effectively reduced.

The embodiment of the application provides a display control method and device and a vehicle-mounted display, which are used for solving the problems of overlong time from power-on to display and poor user experience on the vehicle-mounted display based on an FPGA (Field Programmable Gate Array). The time from power-on to image display is shortened, and the user experience is improved.

The method and the device are based on the same application concept, and because the principles of solving the problems of the method and the device are similar, the implementation of the device and the method can be mutually referred, and repeated parts are not repeated.

The display device provided by the embodiment of the application is, for example, a vehicle-mounted display, and the architecture diagram of the display device is shown in fig. 1. The front-end input device sends a video signal to an FPGA (field programmable gate array) end in the form of LVDS (Low-Voltage Differential Signaling), and the FPGA is matched with an MCU (micro controller Unit) to process the input video signal and control the image display of a display screen and the brightness and darkness of a backlight.

And the first flash is connected with the MCU and used for storing parameters. And the MCU calls parameters in the first flash to configure the parameters to modules such as a backlight processing module in the FPGA. The backlight processing module belongs to a general module and supports a plurality of working modes and functions. The system can work in different states by configuring different parameters. For example: in the embodiment of the present application, the backlight is 576-division, and the operation parameters of the backlight control module need to be set to 576-division. Other parameters are similar and will not be described in detail here.

And the second flash is connected with the FPGA and used for storing the downloaded netlist file of the FPGA.

Overall data flow direction: the LVDS signals input by the input device are processed by the receiving module and converted into VGA (Video Graphics Array) signals (HS, VS, DE, DATA). The backlight processing module extracts effective signals in the VGA image according to a backlight processing algorithm, processes the image, and transmits the processed image to a display screen through the image data selection module and the sending module respectively. In synchronization with the above, the backlight processing module generates backlight control data according to the input image information, and sends the backlight control data to the backlight data selection module, and controls the brightness of the backlight lamp through the backlight data selection module.

The display in the embodiment of the application is composed of an image display part and a backlight display part. The backlight portion is composed of M × N lamps. The backlight control algorithm can control the brightness of the corresponding backlight lamp according to the brightness of the previous image. The valid signal is relative to the algorithm, e.g., the valid signal is the maximum of brightness in the M x N region.

The backlight processing module generates backlight control data according to input image information, and specifically, may be implemented according to a backlight processing algorithm, for example:

if an area image is pure white, the backlight data is 100% brightness.

The image of one area is pure black, and the backlight control data controls the brightness of the backlight at 0%.

The backlight lamp is controlled to be bright and dark by the backlight control chip. And controlling the brightness of the backlight lamp by configuring parameters in the backlight control chip.

Clock: the external crystal oscillator can generate an independent fixed crystal oscillator clock. The receiving module analyzes the data synchronization clock from the LVDS data at the front end. And the clock selection module is used for selecting the working clock required by the rear-end module according to the requirement. Specifically, when the initialization of the front-end input device is not completed and the input signal is unstable, a clock from an external crystal oscillator needs to be selected; when the initialization of the front-end input device is completed, the data synchronization clock is switched to.

MCU: and the MCU is used as a control unit and is cooperated with the FPGA internal module to coordinate and control the whole system. The MCU can control the source of the working clock, and particularly can select whether the working clock comes from an external crystal oscillator or a data synchronous clock. When the initialization of the front-end input equipment is not finished and the input signal is unstable, a clock from an external crystal oscillator needs to be selected; when the initialization of the front-end input equipment is completed and the input signal is stable, the data synchronization clock is switched to. The detection result (whether the input signal is stable) of the timing detection module is sent to the MCU. The MCU can control the reset module to reset the FPGA internal module. The MCU can read and write a register in the FPGA, and the state of the register determines whether to reset or not. For example: register write 1, reset occurs. Write 0 is in normal operation. The internal module, for example, includes: the device comprises a receiving module, a backlight processing module, a sending module and the like.

The MCU controls the image data selection module and the backlight data selection module in a parameter writing mode. For example, a parameter register named sel _ reg is arranged in the image data selection module; when sel _ reg is 1. The image data selection module selects the image data sent by the backlight processing module and sends the image data to the sending module. When sel _ reg is 0, the image data selection module selects the image data sent by the independent LOGO module and sends the image data to the sending module.

A time sequence detection module: the time sequence detection module can detect whether the time sequence signals analyzed by the receiving module are stable or not, so that whether initialization of the front-end input equipment is completed or not and whether the input signals are stable or not are judged, and if the initialization is stable, the MCU is triggered to control the source of the working clock to be the data synchronization clock.

Independent LOGO module: the module is used for generating a preset LOGO picture. After the FPGA loads the netlist (the netlist is a file necessary for the FPGA to work and is equivalent to a program of the MCU), the FPGA works independently without depending on an input signal of a front-end input device, and sends an image (namely a preset LOGO picture) to a display screen at the rear end for display.

Independent backlight control module: backlight control data is generated to independently control the state of the backlight. After the FPGA loads the netlist, the FPGA works independently without depending on an input signal of front-end input equipment to control the brightness of a backlight lamp of the display screen.

The time of loading the netlist by the FPGA and the time of initializing the MCU are within 1 s. While the initialization time of the front-end input device is often on the order of tens or tens of seconds. If according to the traditional display flow, after the system is powered on, the display screen has no display time of tens of seconds or even tens of seconds. And this application embodiment make full use of FPGA and start fast advantage after the electricity, be shaded and the display screen all has independent control unit, lets FPGA work back, goes to independently light the display screen through independent backlight control module wherein and independent LOGO module, shortens to go up the time that the image shows, and after FPGA was gone up the electricity promptly, the inside independent LOGO module of FPGA just begins to work, sends the LOGO image and shows for the rear end. And when the LOGO image is sent, the independent backlight control module can light the backlight of the LOGO image. During initialization of the front-end input device, the display screen end can always display images generated by the internal independent LOGO. When the front-end input device normally sends a signal, the MCU controls the image data selection module to switch the display of the display screen end to the image of the front-end input device (namely, the image data from the backlight processing module) for displaying, and simultaneously controls the backlight data selection module to select the backlight control data from the backlight processing module for backlight control.

The specific structure of the independent LOGO module in the embodiment of the application is shown in FIG. 2, and the independent LOGO module is internally provided with a time sequence generation module for generating VGA signals capable of driving a display screen to display. The designed LOGO characters (namely preset images) can be stored in the ROM, the ROM read-write module can extract LOGO image data from the ROM, an image is formed through the time sequence control module, and specifically the time sequence control module can send the LOGO image according to the format sent by the image, so that an image is formed.

Because the internal storage resources of the FPGA are limited, the reduced LOGO image information is stored in the ROM. The image information recombined by the time sequence control module is amplified by the image amplification module to a set size, so that the image is displayed on the display screen, as shown in fig. 3, the image "Hisense" displayed on the rightmost side is the image displayed on the display screen after being amplified by the image amplification module. The method can effectively reduce the requirement on the internal storage of the FPGA and reduce the design cost.

The input signals of the independent LOGO module are two, namely a clock signal (CLK) from the clock selection module and a Reset Signal (RST) from the reset module. The output signals of the independent LOGO module are four types, and are output to the image DATA selection module, and the four types of signals are VGA signals (i.e., field sync signal VS), HS (line sync signal), DE (DATA validity signal), and DATA signals, respectively, where DATA represents RGB (red, green, and blue three primary colors).

The overall processing flow of the technical scheme provided by the embodiment of the application is shown in fig. 4, after the overall system is powered on, the FPGA is powered on and loaded with the netlist, the system enters a working state, then the MCU is powered on and the program is loaded, the system also starts to work, and the front-end input device starts to initialize. The independent LOGO module in the FPGA extracts LOGO image information from the ROM, amplifies the LOGO image information, and sends the amplified image to the rear end, namely the amplified image is finally sent to a display screen for display through the image data selection module and the sending module respectively (on the premise that initialization of input equipment is not completed). Meanwhile, the MCU controls the image data selection module and the backlight data selection module, thereby realizing the switching of the image data and the backlight data. The MCU controls the backlight system to be powered on, namely the independent backlight control module is controlled to light the backlight lamp, and the display screen starts to display the LOGO image. The MCU resets the receiving module at a preset time point and starts to receive a stable signal sent by the input equipment at the front end. The time sequence detection module detects whether a signal sent by the front-end input equipment is stable. If the stability of the input signal of the front end is detected, the input signal is fed back to the MCU. The MCU switches the LOGO signal displayed by the display screen end to the display image of the front-end input device. In the switching process, the problem of wire drawing flicker can occur due to the fact that the front end clock and the rear end clock are asynchronous. To solve this problem, a way of turning off the backlight is used to mask the instantaneous problem of the flicker of the drawn wire. The MCU controls the power failure of the backlight lamp, then the working clock is switched to the data synchronization clock by controlling the clock selection module, and the image data and the backlight data are switched to the backlight processing module. The whole system unifies a clock and can start normal work, the MCU controls the backlight lamp to be electrified, a display picture is switched from LOGO to an input device picture, and the display picture formally enters a working state.

In summary, referring to fig. 5, a display control method provided in an embodiment of the present application includes:

s101, after the FPGA is electrified, sending a preset image to an image data selection module through an independent LOGO module arranged in the FPGA;

s102, when the initialization of the input equipment is not finished, under the control of a Micro Control Unit (MCU), a preset image sent by the independent LOGO module is sent to a display screen for display through a sending module by a selection module of image data;

Optionally, after the FPGA is powered on, the method further includes:

Optionally, the method further comprises:

and detecting whether the time sequence signal analyzed by the receiving module is stable through a time sequence detection module in the FPGA, and informing the MCU of a detection result, wherein if the time sequence signal is stable, the MCU determines that the initialization of the input equipment is finished, otherwise, the MCU determines that the initialization of the input equipment is not finished.

Optionally, the method further comprises:

and through a reset module in the FPGA, under the control of the MCU, resetting the module in the FPGA.

The display control device provided in the embodiment of the present application is, for example, the FPGA described above.

The display control system provided by the embodiment of the application comprises the FPGA and the MCU.

The display device provided by the embodiment of the application comprises the FPGA, the MCU, the display screen, the backlight lamp and other devices. Specifically, for example, an in-vehicle display may be used.

It should be noted that, in the embodiment of the present application, the division of the unit or the module is schematic, and may be only one logic function division, and there may be another division manner in actual implementation. In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The embodiment of the present application provides a computing device, which may specifically be a desktop computer, a portable computer, a smart phone, a tablet computer, a Personal Digital Assistant (PDA), and the like. The computing device may include a Central Processing Unit (CPU), memory, input/output devices, etc., the input devices may include a keyboard, mouse, touch screen, etc., and the output devices may include a Display device, such as a Liquid Crystal Display (LCD), a Cathode Ray Tube (CRT), etc.

The memory may include Read Only Memory (ROM) and Random Access Memory (RAM), and provides the processor with program instructions and data stored in the memory. In the embodiments of the present application, the memory may be used for storing a program of any one of the methods provided by the embodiments of the present application.

The processor is used for executing any one of the methods provided by the embodiment of the application according to the obtained program instructions by calling the program instructions stored in the memory.

Embodiments of the present application provide a computer storage medium for storing computer program instructions for an apparatus provided in the embodiments of the present application, which includes a program for executing any one of the methods provided in the embodiments of the present application.

The computer storage media may be any available media or data storage device that can be accessed by a computer, including, but not limited to, magnetic memory (e.g., floppy disks, hard disks, magnetic tape, magneto-optical disks (MOs), etc.), optical memory (e.g., CDs, DVDs, BDs, HVDs, etc.), and semiconductor memory (e.g., ROMs, EPROMs, EEPROMs, non-volatile memory (NAND FLASH), Solid State Disks (SSDs)), etc.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A display control apparatus, characterized by comprising:

2. The display control apparatus according to claim 1, further comprising:

3. The display control apparatus according to claim 2, further comprising:

4. The display control apparatus according to claim 3, characterized by further comprising:

5. The display control apparatus according to claim 1, further comprising:

6. A display control system comprising the display control apparatus according to any one of claims 1 to 5 and the MCU.

7. A display device comprising the display control apparatus according to any one of claims 1 to 5, a display screen, a backlight, and the MCU.

8. A display control method, comprising:

9. The display control method of claim 8, wherein after the FPGA is powered on, the method further comprises:

10. The display control method according to claim 8, characterized in that the method further comprises: