CN103488607A - Communication system and communication method for SOC (system on chip) processor and FPGA (field-programmable gate array) chip on embedded linux platform - Google Patents
Communication system and communication method for SOC (system on chip) processor and FPGA (field-programmable gate array) chip on embedded linux platform Download PDFInfo
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Abstract
The invention discloses a communication system and a communication method for an SOC (system on chip) processor and an FPGA (field-programmable gate array) chip on an embedded linux platform. The communication system comprises the SOC processor and the FPGA chip. External memory interfaces (EMIF) of the SOC processor are electrically connected with IO (input/output) pins of the FPGA chip in modes including an FPGA and RAM (random access memory) mode and an FPGA FIFO (first input first output) mode. The communication system and the communication method have the advantages that an embedded linux operating system runs on the SOC processor, and equipment of the FPGA chip is driven, so that the efficient and high-speed data communication method can be provided for the FPGA chip and the SOC processor in the embedded field; the SOC processor can be expanded after FPGA hardware is programmed by users, so that various user-defined complicated functions can be realized; the communication system and the communication method have huge application potential in the wireless communication field, the multi-channel high-speed data acquisition and display field and the automatic control field.
Description
Technical field
The present invention relates to linux kernel-driven, SOC processor and FPGA hardware programmable technology, particularly communication system and the communication means of SOC processor and fpga chip under a kind of embedded Linux platform.
Background technology
The SOC processor is widely used in fields such as information household appliances, Industry Control with its high-performance, low-power consumption, the characteristics such as multi-functional.In embedded Control, single-chip microcomputer+FPGA, DSP+FPGA are common solutions.The FPGA(field programmable gate array) have the advantages such as programming is convenient, integrated level is high, speed is fast, the Electronic Design personnel can realize by the method for hardware programming the research and development of the various functions of fpga chip.High-end SOC processor (as Leonardo da Vinci's series processors, the OMAP series processors of TI company is double-core ARM+DSP framework), travelling speed is fast, can realize very complicated function, usually on processor platform, is all moving embedded OS.Linux is with its kernel refining, efficient, and open source and the advantage such as free, be widely used in embedded SOC field.Data communication interface common on the SOC processor has: UART, USB, I2C, SPI, GPIO, SDIO, Ethernet interface etc.When chip producer is linux and transplants for its SOC processor, for providing to drive, these common interfaces support, so that the embedded Linux developer develops this class application interface is comparatively simple.In the system board level is integrated, SOC processor operation linux system can be communicated by letter by general I2C, SPI, GPIO, UART Interface realization low speed data with FPGA, realizes that in FPGA the difficulty of I2C, SPI, GPIO, UART interface is general; The speed of SDIO interface, but its communication interface realizes comparatively complexity in FPGA; And Ethernet interface is applicable to telecommunication, be not suitable for being applied to the board level system of SOC processor+FPGA integrated in.
Summary of the invention
Technical matters to be solved by this invention is, for the deficiencies in the prior art, to provide the integrated SOC processor of simple under a kind of embedded Linux software platform, at a high speed applicable system board level and communication system, the method for fpga chip.
For solving the problems of the technologies described above, technical scheme of the present invention is: the communication system of SOC (system on a chip) SOC processor and fpga chip under a kind of embedded Linux platform, comprise SOC processor, fpga chip, the external memory interface EMIF of described SOC processor and the electrical connection of the input and output pin of fpga chip.
The pin of the external memory interface EMIF of described SOC processor comprises input pin, chip selection signal pin EM_CS, write data signal pin EM_WE, reading data signal pin EM_OE, read-write enable signal pin EM_R/W, address pin ADDR, data pin EM_D.
The external memory interface EMIF of described SOC processor and the input and output pin electric connecting mode of fpga chip comprise FPGA RAM memory mode and FPGA First Input First Output pattern.
Described fpga chip inside comprises realizes EMIF control module and distributed block ram module.
Described distributed block ram module carries out exchanges data for buffer memory fpga chip and SOC processor.
Described EMIF control module, for carrying out the sequential coupling of SOC processor and fpga chip distributed block ram module.
The communication means of the communication system of SOC (system on a chip) SOC processor and fpga chip under a kind of embedded Linux platform, described method comprises the following steps:
Under FPGA First Input First Output pattern, the internal counter in the EMIF control module is low effectively according to write data signal EM_WE() or reading data signal EM_OE(effectively low) automatically produce address and offer the distributed block ram module;
Under FPGA RAM memory mode, the address wire width that the EMIF control module provides the SOC processor matches the address width of distributed block ram module;
Under FPGA First Input First Output pattern or FPGA RAM memory mode, the EMIF control module all needs the SOC processor to provide one almost to expire signal almost_full, one almost empty almost_empty signal be connected to the input pin GPIO[1:0 of SOC processor], when writing number and reading, the SOC processor detects almost_full, the almost_empty signal, could write data to FPGA while only having the almost_full invalidating signal, could read data while only having the almost_empty invalidating signal.
The FPGA device drives supports form with module to embedded Linux system dynamic load and unloading;
The insmod module loading realizes the initialization driven, and the unloading of rmmod module realizes the release of resource.
The present invention adopts said structure and method, have the following advantages: 1, operation embedded Linux operating system realize the device drives of FPGA on the SOC processor, for FPGA and SOC processor realize that in built-in field the efficient high-speed data communication provides a kind of method; 2, in actual applications, can expand the SOC processor by the user after to the FPGA hardware programming and realize various user-defined sophisticated functionss.This invention shows that at wireless communication field, multi-channel high-speed data collection field, automation field application potential are huge.
The accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation;
The electrical connection diagram that Fig. 1 is FPGA RAM memory mode and SOC processor in the present invention;
Fig. 2 is FPGA RAM memory mode and SOC processor interface functional block diagram in the present invention;
The electrical connection diagram that Fig. 3 is FPGA fifo mode and SOC processor in the present invention;
Fig. 4 is FPGA fifo mode and SOC processor interface functional block diagram in the present invention;
Fig. 5 is the processor asynchronous FPGA sequential chart of reading of SOC in the present invention;
Fig. 6 is the processor asynchronous FPGA sequential chart of writing of SOC in the present invention;
Fig. 7 is that in the present invention, the DBRAM module is write several reading sequential charts;
Fig. 8 is FPGA driver module initialization flowchart in the present invention;
Fig. 9 is that in the present invention, several operational flowcharts are write in the FPGA driving;
Figure 10 is that in the present invention, FPGA drives the reading operational flowchart;
Figure 11 is that in the present invention, FPGA drives the mmap operational flowchart;
Embodiment
SOC (system on a chip) SOC(System on Chip under a kind of embedded Linux platform as shown in Figure 1) processor and field programmable gate array chip (are Field-Programmable Gate Array, fpga chip) communication system, comprise SOC processor, fpga chip, input and output (Input/Output, IO) the pin electrical connection of the external memory interface EMIF of SOC processor and fpga chip.The external memory interface of SOC processor (EMIF interface) has the fireballing advantage that reads and writes data.
Under Linux, device driver is an intermediate software layer between application program and hardware, and device driver is the details that application program has shielded hardware.In application program, hardware device is a device file, and application program can be operated hardware device as the operation ordinary file, and device driver is the part of kernel, and the function that it is mainly realized has: equipment is carried out to initialization and release; Data are sent to hardware and from the hardware reading out data from kernel; Read the data that application program sends device file to, the mistake that the data of loopback application requests and detection and treatment facility occur.Linux is divided into two the most basic large classes by equipment: a class is character device; Another kind of is block device.The main differentiation of character device and block device is whether used buffer technology.Character device be take single byte and is carried out the order read/write operation as unit, does not usually use buffer technology.SOC processor operation embedded Linux system in the present invention, must realize the FPGA device drives based on SOC processor EMIF interface in order to allow application layer software carry out data interaction with FPGA.The present invention is for the minimise data transmission delay, and the form driven with character device has realized the FPGA device drives under built-in Linux.
In the present invention, the FPGA device drives supports form with module to embedded Linux system dynamic load and unloading.The insmod module loading realizes the initialization driven, and the unloading of rmmod module realizes the release of resource.In the initialization that FPGA drives, will complete the SOC processor the pin multiplexing configuration, the work such as EMIF read-write sequence is set, and to system registry handling function method: read FPGA read (); Write FPGA write(); The FPGA internal memory shines upon mmap () etc. linearly.
The external memory interface EMIF(External Memory Interface of SOC processor) pin comprises input pin, chip selection signal pin EM_CS(is effectively low), write data signal pin EM_WE(is effectively low), reading data signal pin EM_OE(is effectively low), EM_R/W(is high for reading for read-write enable signal pin, hang down for writing), address pin ADDR[22:0] (address width is slightly different according to different CPU), data pin EM_D[7:0] (data width can be 8, 16 or 32).The SOC processor is realized the asynchronous data read-write by controlling external memory interface.
The IO pin electric connecting mode of the external memory interface EMIF of SOC processor and fpga chip comprises FPGA RAM memory mode and FPGA First Input First Output (First Input First Output, FIFO) pattern, the address wire whether FPGA has used SOC to provide is provided in its difference.Fpga chip inside comprises realizes EMIF control module and distributed block random access memory (DBRAM) module; Distributed block random access memory (DBRAM) module is carried out exchanges data for buffer memory fpga chip and SOC processor.The EMIF control module, for carrying out the sequential coupling of SOC processor and fpga chip distributed block random access memory (DBRAM) module.SOC processor in the present invention and the communication means of FPGA mainly are applicable to Leonardo da Vinci's series processors of TI company and the FPGA of disposable type.
Fig. 2 is FPGA RAM memory mode and SOC interface function block diagram, is the logic function block diagram of FPGA internal hardware programming.FPGA has hardware programmable capability flexibly, and there is a large amount of BRAM resources its inside, realizes EMIF control module and distributed block random access memory (DBRAM) module (dual-port block RAM) in the present invention in FPGA inside by hardware programmable.DBRAM (dual-port block RAM) carries out data interaction for buffer memory FPGA and SOC.As shown in Fig. 5,6,7, the EMIF read-write sequence of read and write data sequential and the SOC processor of distributed block random access memory (DBRAM) module is also inconsistent, carries out the sequential coupling of DBRAM module in SOC processor and FPGA by the EMIF control module.
The electrical connection diagram that Fig. 3 is FPGA fifo mode and SOC processor, Fig. 4 is FPGA fifo mode and SOC interface function block diagram.Under fifo mode, EMIF control module in FPGA does not need the SOC processor that address signal ADDR is provided, and the internal counter in the EMIF control module is low effectively according to write data signal EM_WE() or reading data signal EM_OE(effectively low) automatically produce address and offer the DBRAM module; The RAM memory mode, the address wire width that the EMIF control module provides the SOC processor matches the address width of DBRAM.
Under built-in Linux, the FPGA device driver is an intermediate software layer between application layer software and FPGA, and the FPGA device drives is the details that application program has shielded hardware.In the present invention, the FPGA device drives supports form with module to embedded Linux system dynamic load and unloading.The insmod module loading realizes the initialization driven, and the unloading of rmmod module realizes the release of resource.Fig. 8 is FPGA driver module initialization flowchart.In the initialization that FPGA drives, will complete the SOC processor the pin multiplexing configuration, the work such as EMIF read-write sequence is set, and to system registry handling function method: read fpga_read (); Write fpga_write(); The FPGA internal memory shines upon fpga_mmap () etc. linearly.
Fig. 9 is that several operational flowcharts are write in the FPGA driving; during the linux process transfer; fpga_read () application mutex amount realizes the protection to resource; fpga_read () is from the FPGA reading out data to kernel spacing and to linux user's space copies data, and then release semaphore completes the reading operation.Fpga_write() process and fpga_write() it is similar that just the data direction of transfer is contrary.Read fpga_read () and write fpga_write() all to relate to the data copies efficiency of linux user's space and kernel spacing lower for method.Figure 10 is that in the present invention, FPGA drives the reading operational flowchart.Figure 11 is that FPGA drives the mmap operational flowchart.Internal memory under Linux shines upon the mmap method linearly can allow consumer process space direct control physical address, and execution efficiency is higher.Fpga_mmap () is by calling remap_page_range() function realizes the mapping of one section linear physical address, calls remap_page_range().
The communication means of the communication system of SOC processor and fpga chip under a kind of embedded Linux platform, method comprises the following steps: under the FPGA fifo mode, the internal counter in the EMIF control module is low effectively according to write data signal EM_WE() or reading data signal EM_OE(effectively low) automatically produce address and offer the DBRAM module; Under FPGA RAM memory mode, the address wire width that the EMIF control module provides the SOC processor matches the address width of DBRAM;
Under FPGA fifo mode or FPGA RAM memory mode, the EMIF control module all needs the SOC processor to provide one almost to expire signal almost_full, one almost empty almost_empty signal be connected to the input pin GPIO[1:0 of SOC processor], when writing number and reading, the SOC processor detects almost_full, the almost_empty signal, could write data to FPGA while only having the almost_full invalidating signal, could read data while only having the almost_empty invalidating signal.The FPGA device drives supports form with module to embedded Linux system dynamic load and unloading.
The above is exemplarily described the present invention by reference to the accompanying drawings; obviously specific implementation of the present invention is not subject to the restrictions described above; as long as the various improvement that adopted method design of the present invention and technical scheme to carry out; or directly apply to other occasion without improvement, all within protection scope of the present invention.
Claims (9)
1. the communication system of SOC (system on a chip) SOC processor and fpga chip under an embedded Linux platform, comprise SOC processor, fpga chip, it is characterized in that: the external memory interface EMIF of described SOC processor and the electrical connection of the input and output pin of fpga chip.
2. the communication system of SOC (system on a chip) SOC processor and fpga chip under a kind of embedded Linux platform according to claim 1 is characterized in that: the pin of the external memory interface EMIF of described SOC processor comprises input pin, chip selection signal pin EM_CS, write data signal pin EM_WE, reading data signal pin EM_OE, read-write enable signal pin EM_R/W, address pin ADDR, data pin EM_D.
3. the communication system of SOC (system on a chip) SOC processor and fpga chip under a kind of embedded Linux platform according to claim 1, it is characterized in that: the external memory interface EMIF of described SOC processor and the input and output pin electric connecting mode of fpga chip comprise FPGA RAM memory mode and FPGA First Input First Output pattern.
4. the communication system of SOC (system on a chip) SOC processor and fpga chip under a kind of embedded Linux platform according to claim 1, it is characterized in that: described fpga chip inside comprises realizes EMIF control module and distributed block ram module.
5. the communication system of SOC (system on a chip) SOC processor and fpga chip under a kind of embedded Linux platform according to claim 1 is characterized in that: described distributed block ram module carries out exchanges data for buffer memory fpga chip and SOC processor.
6. the communication system of SOC (system on a chip) SOC processor and fpga chip under a kind of embedded Linux platform according to claim 1, it is characterized in that: described EMIF control module, for carrying out the sequential coupling of SOC processor and fpga chip distributed block ram module.
7. the communication means according to the communication system of SOC (system on a chip) SOC processor and fpga chip under the described embedded Linux platform of claim 1-3 any one, it is characterized in that: described method comprises the following steps:
Under FPGA First Input First Output pattern, the internal counter in the EMIF control module is low effectively according to write data signal EM_WE() or reading data signal EM_OE(effectively low) automatically produce address and offer the distributed block ram module;
Under FPGA RAM memory mode, the address wire width that the EMIF control module provides the SOC processor matches the address width of distributed block ram module.
8. the communication means of the communication system of SOC (system on a chip) SOC processor and fpga chip under a kind of embedded Linux platform according to claim 7, it is characterized in that: under FPGA First Input First Output pattern or FPGA RAM memory mode, the EMIF control module all needs the SOC processor to provide one almost to expire signal almost_full, one almost empty almost_empty signal be connected to the input pin GPIO[1:0 of SOC processor], when writing number and reading, the SOC processor detects almost_full, the almost_empty signal, could write data to FPGA while only having the almost_full invalidating signal, could read data while only having the almost_empty invalidating signal.
9. the communication means of the communication system of SOC processor and fpga chip under a kind of embedded Linux platform according to claim 7 is characterized in that: the FPGA device drives supports form with module to embedded Linux system dynamic load and unloading;
The insmod module loading realizes the initialization driven, and the unloading of rmmod module realizes the release of resource.
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| CN104267702A (en) * | 2014-10-11 | 2015-01-07 | 哈尔滨工业大学 | Galatea type plasma magnetic confinement device sequential control system based on SOPC technology |
| CN107329892A (en) * | 2017-06-07 | 2017-11-07 | 珠海市杰理科技股份有限公司 | Drive method of testing, device, storage medium and its computer equipment |
| CN107833567A (en) * | 2017-10-27 | 2018-03-23 | 长沙理工大学 | Display based on FPGA and signal switching and parameter configuration method thereof |
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| CN104267702B (en) * | 2014-10-11 | 2017-05-31 | 哈尔滨工业大学 | Galatea type magnetic confinement of plasma device sequential control systems based on SOPC technologies |
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| CN107329892A (en) * | 2017-06-07 | 2017-11-07 | 珠海市杰理科技股份有限公司 | Drive method of testing, device, storage medium and its computer equipment |
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| CN109308268A (en) * | 2017-07-27 | 2019-02-05 | 中车株洲电力机车研究所有限公司 | A kind of data cache device and method |
| CN107833567A (en) * | 2017-10-27 | 2018-03-23 | 长沙理工大学 | Display based on FPGA and signal switching and parameter configuration method thereof |
| CN108628780A (en) * | 2018-04-28 | 2018-10-09 | 上海与德科技有限公司 | A kind of data communications method, system and electric vehicle |
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| CN112925485A (en) * | 2021-05-11 | 2021-06-08 | 湖南博匠信息科技有限公司 | Multi-channel high-speed data transmission and storage method and system of embedded Linux |
| CN112925485B (en) * | 2021-05-11 | 2021-08-03 | 湖南博匠信息科技有限公司 | Multi-channel high-speed data transmission and storage method and system of embedded Linux |
| CN113688592A (en) * | 2021-08-12 | 2021-11-23 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | SoC chip implementation system, method, medium and device based on driving middleware |
| CN114218155A (en) * | 2021-12-16 | 2022-03-22 | 中国人民解放军国防科技大学 | Gateway development method and development platform for space-based Internet of things |
| CN114218155B (en) * | 2021-12-16 | 2023-09-29 | 中国人民解放军国防科技大学 | Gateway development method and development platform for space-based Internet of Things |
| CN115964229A (en) * | 2023-03-16 | 2023-04-14 | 北京华环电子股份有限公司 | Cooperative working method and device of multiprocessor device and storage medium |
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