CN110719373B - Anti-hang-up xDSL system and method - Google Patents
Anti-hang-up xDSL system and method Download PDFInfo
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Abstract
The invention discloses an anti-hang-up xDSL system, which relates to the field of xDSL and comprises a logic control module, wherein the logic control module is used for monitoring a DSP reset signal, responding to the DSP reset signal and sequentially generating a first reset adjusting signal and a second reset adjusting signal, the first reset adjusting signal is sent to a DCXO module, and the second reset adjusting signal is sent to the DSP module. And the DCXO module is used for receiving the first reset adjusting signal, outputting a clock signal with default frequency and sending the clock signal to the DSP module. And the DSP module is used for receiving and responding to the second reset adjustment reset signal and carrying out digital signal processing operation according to the clock signal with default frequency.
Description
Technical Field
The invention relates to the field of xDSL, in particular to an anti-hang xDSL system and an anti-hang xDSL method.
Background
With the continuous development of information-oriented in modern society, especially the continuous development of services such as video and data represented by IPTV (Internet Protocol television), the existing copper wire transmission system cannot meet the increasing demand of interconnection rate, and the transmission capacity of the copper wire transmission system is urgently required to be further increased. In fact, with the proliferation of network transmission capacity requirements, copper wire transmission technology has experienced ADSL, ADSL2+, VDSL2+, etc., even though VDSL technology bandwidth has also expanded from 12MHz to 35 MHz. Theoretically, the copper wire transmission technology can reach the speed of 300Mbit/s at the downlink and 100Mbit/s at the uplink.
In the field of communications, various types of Digital Subscriber Lines (DSL) are collectively referred to as xDSL. In a copper wire transmission system, as the rate of xDSL is increasing, the frequency band range of xDSL is also expanding, which directly results in that the received interference is increased inevitably, including crosstalk between lines, background noise interference, impulse noise interference, service radio interference, and the like.
Due to the inherent defect of copper money, the existing subscriber cable problem almost accounts for more than 50% of the fault cause of the whole xDSL subscriber, and in order to meet the large-scale deployment of real-time services, the requirements on the stability and reliability (such as bit error rate and disconnection rate) of an xDSL network are higher. The maintenance efficiency of the outside line is improved, and the automatic detection and diagnosis of the line problem become key factors for solving the problem. The mainstream scheme at present is a DSM (dynamic spectrum management) technology, that is, a data signal of an adjacent port and a crosstalk transfer function between lines are obtained by actively sending signals, so that crosstalk information of the adjacent port is eliminated according to the information, the anti-interference capability of xDSL is enhanced, and the entire xDSL line system is always in a stable and optimized state.
The vector disk is a control unit module of a vector control algorithm, crosstalk in a channel is evaluated in a mode appointed by a local side and a terminal, and information is pre-coded into a normal channel at a sending end in advance. Therefore, the pre-coded signal and the crosstalk in the channel are offset in two phases in the transmission process, and the local side or the terminal receiving end can receive correct information with approximate no crosstalk;
the logic control module is that the DSPs of each xDSL control unit need to use a synchronous and fixed clock frequency, and in order to achieve synchronization, the logic control unit sends a 64KHz clock signal to each xDSL control unit to the master DSP of the single disk, and the master DSP adjusts DXCO output through the I2C bus based on the 64K clock.
Meanwhile, the DCXO (digital Controlled Oscillator) module includes a digital compensated crystal Oscillator, which is mainly used to provide a clock for normal operation of a system or an IC, maintain frequency stability under a certain operating condition, and output a clock frequency with a large range according to different adjustment sources.
As shown in fig. 1, in the existing xDSL copper wire transmission system, on the premise of extending the frequency band, Vectored DSL technology is mainly used, so that simple crosstalk of different channels is reduced, and interference of external electrical factors on the channels is reduced. When the vector disk is used, each xDSL control unit is synchronized through the vector disk, and the vector disk can synchronize a clock corresponding to a DSP chip of the control unit at the moment, so that the frequency of a DSP processing digital signal and the clock frequency can be corresponding and used. However, in the existing xDSL copper wire transmission system, the clock corresponding to the DSP chip is adjusted by adding a DCXO module. When the DSP chip is abnormally reset, the DSP chip needs to start working from the default clock frequency, and the DCXO module cannot receive the reset signal and adjust the clock frequency to output the clock signal to the DSP chip again, the DSP chip receives the clock signal of the clock frequency adjusted by the DCXO module before the reset, so that the DSP module cannot process the digital signal, and the management module of the related adjustment DCXO module cannot process the numerical signal at the same time of the DSP reset, does not know how to further adjust the DCXO, so that the state is kept all the time, namely the DSP hangs up.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide an anti-hang-up xDSL system, which can ensure that the xDSL is not hung up when the xDSL is reset, and improve the stability and reliability of a line.
To achieve the above object, in a first aspect, an embodiment of the present invention provides an anti-hang xDSL system, which includes a DSP module, a DCXO module, and a logic control module:
the logic control module is used for monitoring a DSP reset signal, responding to the DSP reset signal and sequentially generating a first reset adjusting signal and a second reset adjusting signal, wherein the first reset adjusting signal is sent to the DCXO module, and the second reset adjusting signal is sent to the DSP module;
the DCXO module is used for receiving the first reset adjusting signal, outputting a clock signal with default frequency and sending the clock signal to the DSP module;
and the DSP module is used for receiving and responding to the second reset adjustment reset signal and carrying out digital signal processing operation according to the clock signal with default frequency.
As a preferred embodiment, the DCXO module includes a DCXO switch, the logic control module inputs a first reset adjustment signal to the DCXO switch after receiving the DSP reset signal, and the DCXO switch turns off and turns on the DCXO module after receiving the first reset adjustment signal.
As a preferred embodiment, the first reset adjustment signal is a timing signal.
As a preferred embodiment, the DSP reset signal comprises a software reset signal.
As a preferred embodiment, the xDSL system is disposed on a board.
As a preferred embodiment, the logic control module includes a register, and the logic control module outputs the first reset adjustment signal and the second reset adjustment signal according to a value stored in the register.
In a second aspect, an embodiment of the present invention further provides an anti-deadlock xDSL method, which includes:
the reset signal of the DSP is monitored and,
responding to the DSP reset signal, firstly generating a first reset adjusting signal and sending the first reset adjusting signal to the DCXO module, and then generating a second reset adjusting signal and sending the second reset adjusting signal to the DSP module;
the DCXO module receives the first reset adjusting signal, outputs a clock signal with default frequency and sends the clock signal to the DSP module;
and the DSP module receives and responds to the second reset adjusting signal and carries out digital signal processing operation according to the clock signal with default frequency.
As a preferred embodiment, the DCXO module includes a DCXO switch, the logic control module inputs a first reset adjustment signal to the DCXO switch after receiving the DSP reset signal, and the DCXO switch turns off and turns on the DCXO module after receiving the first reset adjustment signal.
As a preferred embodiment, the first reset adjustment signal is a timing signal.
As a preferred embodiment, the DSP reset signal comprises a software reset signal.
Compared with the prior art, the invention has the advantages that:
when the reset operation is carried out, the default clock frequency input aiming at the DSP module can be automatically and rapidly finished, and the DSP module is ensured not to receive the clock signal before the reset after the reset. Thereby ensuring that the numerical value signal can not be processed in disorder, locking, hanging and the like. The invention can monitor the DSP reset signal and inform the DCXO module by setting logic control, and the DCXO module can output the clock signal of default clock frequency to the DSP when the DSP is reset by receiving the reset adjusting signal sent by the logic control module, thereby ensuring the operation of the whole xDSL system.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings corresponding to the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of an xDSL cable card structure in a system;
FIG. 2 is a schematic structural diagram of an embodiment of an anti-deadlock xDSL system according to the present invention;
FIG. 3 is another schematic diagram of an embodiment of an anti-deadlock xDSL system according to the present invention;
FIG. 4 is a flow chart of an embodiment of an anti-hang xDSL system according to the present invention;
fig. 5 is a flowchart of a method for hanging up xDSL.
Detailed Description
Interpretation of terms:
embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
The embodiment of the invention provides an anti-hang-up xDSL system and a method thereof, which can monitor a reset signal through a logic control module to output a reset adjusting signal for adjusting a DCXO module, and can control the DCXO module to output the signal when the DCXO module is reset.
In order to achieve the technical effects, the general idea of the application is as follows:
the digital signal processor comprises a DSP module, a DCXO module and a logic control module. Wherein,
the logic control module is used for monitoring a DSP reset signal, responding to the DSP reset signal and sequentially generating a first reset adjusting signal and a second reset adjusting signal, wherein the first reset adjusting signal is sent to the DCXO module, and the second reset adjusting signal is sent to the DSP module;
the DCXO module is used for receiving the first reset adjusting signal, outputting a clock signal with default frequency and sending the clock signal to the DSP module;
and the DSP module is used for receiving and responding to the second reset adjustment reset signal and carrying out digital signal processing operation according to the clock signal with default frequency.
In an xDSL copper wire transmission network, under the premise of expanding a frequency band, if a Vectored DSL technology is adopted, crosstalk among different channels and interference of the outside to the channels are reduced. When the xDSL system uses the vector disk, the vector disk is needed to synchronize each xDSL control unit, that is, to synchronize the clock of the DSP chip in the control unit, and the clock of the DSP module is self-regulated by adding the DCXO.
Therefore, the invention provides an anti-hang-up xDSL system, which can recover normal state by sudden abnormal reset in xDSL and input the clock frequency of default frequency to the reset DSP before the DSP module is hung up due to shortage, thereby ensuring that the DSP module can normally perform digital signal processing operation and further improving the safety and stability of the whole xDSL network.
In order to better understand the technical solution, the following detailed description is made with reference to specific embodiments.
Referring to fig. 2, an embodiment of the present invention provides an anti-deadlock xDSL system, which includes:
the logic control module is used for monitoring a DSP reset signal, responding to the DSP reset signal and sequentially generating a first reset adjusting signal and a second reset adjusting signal, wherein the first reset adjusting signal is sent to the DCXO module, and the second reset adjusting signal is sent to the DSP module;
the DCXO module is used for receiving the first reset adjusting signal, outputting a clock signal with default frequency and sending the clock signal to the DSP module;
and the DSP module is used for receiving and responding to the second reset adjustment reset signal and carrying out digital signal processing operation according to the clock signal with default frequency.
The anti-hang xDSL system provided by the embodiment of the invention detects the reset signal, and realizes linkage of the DSP module and the DCXO module through the logic control module. After the reset signal is detected, a first reset adjusting signal and a second reset adjusting signal are sequentially generated, the first reset adjusting signal is output to the DCXO module, the DCXO module outputs a clock signal with default clock frequency to the DSP module after receiving the first adjusting signal and before the DS module P is reset, the DSP module does not have the phenomena of hanging and the like due to the fact that the DSP module works on the clock signal with the default clock frequency after receiving the second reset adjusting signal, and the sequential generation sequence ensures that the DCXO module can complete reset and output the clock signal with the default clock frequency to the DSP module before the DSP module is reset.
Referring to fig. 3, as a preferred real-time scheme, the DCXO module includes a DCXO switch, the logic control module inputs a first reset adjustment signal to the DCXO switch after receiving the DSP reset signal, and the DCXO switch turns off and turns on the DCXO module after receiving the first reset adjustment signal.
When the logic control module controls the DCXO module to output the clock signal with the default frequency, the DCXO module can be turned on and off through the DCXO switch of the DCXO module. The DCXO module is opened according to the first reset adjusting signal of the logic control module and is reset, and then the clock signal of the default clock frequency is output, the DSP module after the reset can be ensured to correspond to the clock signal of the frequency, and the digital signal operation is normally carried out.
As a preferred embodiment, the DSP reset signal comprises a software reset signal.
The software reset signal is that after the detection system/module detects the requirement of resetting the DSP module in xDSL, the detection system/module sends a second reset adjustment signal to the DSP module through the software path, and the DSP module resets after receiving the second reset signal.
As a preferred embodiment, the xDSL system is disposed on a board, and the DSP reset signal is a power-off reset of the board.
When the xDSL system is used for communication on the board card, the xDSL system can communicate with more upstream and downstream devices, error codes or disconnection can be avoided in the communication, and the xDSL system is required to restart the DSP module. At this moment, the board card including the DSP module can be reset through power-off reset of the board card, and the phenomenon that the whole board card loses effect due to dead clamping of the DSP module is prevented.
Further, the logic control module includes a register, and the logic control module outputs a first reset adjustment signal and a second reset adjustment signal according to a value stored in the register.
When the xDSL system is used as a function of the board card, the logic control module can read data stored in a specific location on the register to adjust the first reset adjustment signal and the second reset adjustment signal output by the logic control module. By the mode, the DCXO module can be reset more quickly, so that the clock signal with the default clock frequency can be output before the DSP module is reset, and the phenomenon of hang-up of the DSP module is prevented.
Furthermore, the logic control module outputs a preset control signal to reset the DSP module.
The reset signal of the DSP module is output by the logic control module together, so that when the reset operation of the whole board card is carried out, the DSP module can be mutually coordinated with the DCXO and reset under the logic control module according to the sequence strictly. Therefore, the stability and reliability of the line are ensured, and simultaneously, the time sequence correspondence between the DSP in the xDSL and the DCXO module is rapidly completed, so that the system clock of the whole xDSL line is in a stable and optimized state.
An embodiment of the invention will now be described in its entirety, by way of example, with reference to fig. 4, in which:
step A1: after the service board card is normally powered on and operated, the board card starts to monitor the reset signal of the DSP module, wherein the monitoring is informed to the logic control module. The logic control module can monitor the reset signal, and all DSP reset signals need to realize the reset operation through the logic control terminal, so that the accuracy of the reset signal judgment is ensured.
Step A2: and rewriting the value of the corresponding register in the corresponding logic control module according to the judgment of the logic control module, and then outputting a proper time sequence control signal according to the value of the register to control the DCXO power switch and the DSP to reset.
Step A3: the logic control module outputs a corresponding control signal to close the switch of the DCXO, so as to close the DCXO.
Step A4: the logic control module outputs a corresponding control signal according to the adjusted relevant time sequence to open the DCXO switch, so that the DCXO is opened, and at the moment, the DCXO can output a default clock frequency.
Step A5: the logic control module outputs corresponding control signals to reset the DSP device.
Step A6: the DCXO outputs the default clock frequency before the DSP is powered on, and at the moment, the DSP module can complete starting work according to a normal flow after receiving the clock signal of the default clock frequency.
As shown in fig. 5, the present invention further provides an anti-deadlock xDSL method, which includes:
the reset signal of the DSP is monitored and,
responding to the DSP reset signal, firstly generating a first reset adjusting signal and sending the first reset adjusting signal to the DCXO module, and then generating a second reset adjusting signal and sending the second reset adjusting signal to the DSP module;
the DCXO module receives the first reset adjusting signal, outputs a clock signal with default frequency and sends the clock signal to the DSP module;
and the DSP module receives and responds to the second reset adjusting signal and carries out digital signal processing operation according to the clock signal with default frequency.
Preferably, the DCXO module includes a DCXO switch, the logic control module inputs the first reset adjustment signal to the DCXO switch after receiving the DSP reset signal, and the DCXO switch closes and opens the DCXO module after receiving the first reset adjustment signal.
Further, the first reset adjustment signal is a timing signal.
Optionally, the DSP reset signal includes a software reset signal.
Various modifications and specific examples of the embodiments of the system described above are also applicable to the method of the present embodiment, and the detailed description of the system given above will make clear to those skilled in the art that the method of the present embodiment is not described in detail here for the sake of brevity.
Computer storage media for embodiments of the invention may employ any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer-readable storage medium may be, for example but not limited to: an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Generally, the anti-hang-up xDSL system and method provided by the embodiments of the present invention can ensure that the xDSL is not hung up when resetting, thereby improving the stability and reliability of the line, and simultaneously, quickly completing the timing sequence correspondence between the DSP in the xDSL and the DCXO module, so that the system clock of the entire xDSL line is in a stable and optimized state.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. An anti-hang xDSL system, which comprises a DSP module, a DCXO module and a logic control module, and is characterized in that the system comprises:
the logic control module is used for monitoring a DSP reset signal, responding to the DSP reset signal and sequentially generating a first reset adjusting signal and a second reset adjusting signal, wherein the first reset adjusting signal is sent to the DCXO module, and the second reset adjusting signal is sent to the DSP module;
the DCXO module is used for receiving the first reset adjusting signal, outputting a clock signal with default frequency and sending the clock signal to the DSP module;
and the DSP module is used for receiving and responding to the second reset adjusting signal and carrying out digital signal processing operation according to the clock signal with default frequency.
2. The anti-hang xDSL system as recited in claim 1, wherein: the DCXO module includes the DCXO switch, logic control module receives behind the DSP reset signal, to the first regulation signal that resets of DCXO switch input, after the DCXO switch receives first regulation signal that resets, opens after closing the DCXO module.
3. The anti-hang xDSL system as recited in claim 2, wherein: the first reset adjustment signal is a timing signal.
4. The anti-hang xDSL system as recited in claim 1, wherein: the DSP reset signal comprises a software reset signal.
5. The anti-hang xDSL system as recited in claim 4, wherein: the xDSL system is arranged on the board card.
6. The anti-hang xDSL system as recited in claim 5, wherein: the logic control module comprises a register, and the logic control module outputs a first reset adjusting signal and a second reset adjusting signal according to the numerical value stored in the register.
7. An anti-hang xDSL method, comprising:
the logic control module monitors the DSP reset signal,
responding to the DSP reset signal, firstly generating a first reset adjusting signal and sending the first reset adjusting signal to the DCXO module, and then generating a second reset adjusting signal and sending the second reset adjusting signal to the DSP module;
the DCXO module receives the first reset adjusting signal, outputs a clock signal with default frequency and sends the clock signal to the DSP module;
and the DSP module receives and responds to the second reset adjusting signal and carries out digital signal processing operation according to the clock signal with default frequency.
8. A method as claimed in claim 7, characterized by: the DCXO module includes the DCXO switch, logic control module receives behind the DSP reset signal, to the first regulation signal that resets of DCXO switch input, after the DCXO switch receives first regulation signal that resets, opens after closing the DCXO module.
9. A method as claimed in claim 8, characterized by: the first reset adjustment signal is a timing signal.
10. A method as claimed in claim 7, characterized by: the DSP reset signal comprises a software reset signal.
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| CN101808019B (en) * | 2010-04-02 | 2012-07-25 | 烽火通信科技股份有限公司 | Method for detecting clock out-of-lock of line interface disk of SDH device |
| EP3086478B1 (en) * | 2015-04-23 | 2018-09-19 | Nxp B.V. | Wireless receiver and method |
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