CN107809285B - Limiting amplifier for burst mode receiver - Google Patents
Limiting amplifier for burst mode receiver Download PDFInfo
- Publication number
- CN107809285B CN107809285B CN201711128993.0A CN201711128993A CN107809285B CN 107809285 B CN107809285 B CN 107809285B CN 201711128993 A CN201711128993 A CN 201711128993A CN 107809285 B CN107809285 B CN 107809285B
- Authority
- CN
- China
- Prior art keywords
- signal
- input end
- gate circuit
- port
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/693—Arrangements for optimizing the preamplifier in the receiver
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/695—Arrangements for optimizing the decision element in the receiver, e.g. by using automatic threshold control
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Amplifiers (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention discloses a limiting amplifier for a burst mode receiver and a signal identification method thereof.A signal period identification circuit is added in the burst mode receiver BM-LA, and noise and effective signals can be effectively distinguished by comparing the period of input signals. Meanwhile, because the signal identification is carried out in the lead code period, the signal detection only needs 2TB duration, and the time overhead is little, the method can be widely applied to a high-speed OLT burst mode receiver.
Description
Technical Field
The invention belongs to the technical field of passive optical networks, and particularly relates to a limiting amplifier for a burst mode receiver and a design of a signal identification method thereof.
Background
A typical uplink transmission of a Passive Optical Network (PON) adopts a Time Division Multiple Access (TDMA) manner, as shown in fig. 1, optical signals sent by a plurality of Optical Network Terminals (ONTs) enter an Optical Line Terminal (OLT) through a combined signal after passing through an Optical Distribution Network (ODN), so that a receiver at the OLT end operates in a burst mode.
As shown in fig. 2, in a circuit architecture of a typical OLT receiver, a photodiode converts a received burst data optical signal into a photocurrent, and sends the photocurrent to a burst mode trans-impedance amplifier (BM-TIA), an output of the photodiode is sent to an input end of a burst mode limiting amplifier (BM-LA), and the BM-LA performs limiting amplification on the signal and detects whether the signal is valid; finally, the data and detection signals (SD signals) are output to a clock and data recovery Circuit (CDR).
The principle of the traditional BM-LA signal detection algorithm of the OLT receiver is to detect the amplitude of a received signal, compare the amplitude with a preset threshold voltage, and output a logic level of a detected effective signal when the detected signal amplitude is greater than the threshold; if the signal is less than the threshold value, returning to receive a new signal, and outputting logic for keeping the effective signal not detected.
In a conventional BM-LA Signal detection circuit architecture, as shown in fig. 3, a received Signal is first amplified by an Amplifier (AMP) module, and then output to a Signal Level Detect module, which detects an amplitude of the amplified Signal and compares the amplitude with a preset threshold (Signal Level setting), and a comparison result (Level Detect) is output to a Signal detection logic Generator (Signal Detect Generator) module, and an SD Signal is output to an external interface; usually the SD will be connected to the JAM pin of BM-LA to enable the output driver (BUF) module.
However, due to thermal noise of the photodiode, device noise and external interference, the instantaneous pulse voltage received at the input terminal of the BM-LA under the condition of no signal input is likely to exceed the threshold voltage, so that the BM-LA is erroneously determined to detect an effective signal under the condition of no signal input, and such erroneous logic is output to the receiver system, which is likely to cause an abnormality of the OLT during the operation of the TDMA. At present, most of applications can only adjust the threshold voltage set by the BM-LA to be high in order to reduce the probability of error occurrence, but this reduces the sensitivity of the whole receiver and sacrifices the transmission distance of the optical network.
Disclosure of Invention
The invention aims to provide a limiting amplifier for a burst mode receiver and a signal identification method thereof, aiming at the problem that the signal detection is easy to generate errors under the influence of noise and interference of the traditional BM-LA detection signal algorithm and circuit architecture, and the probability of the generation of effective signal detection errors can be greatly reduced.
The technical scheme of the invention is as follows: a limiting amplifier for a burst mode receiver comprises an amplifier module, a signal amplitude detector module, a signal period identification module, a signal detection logic generator module and an output driving module; the input end of the amplifier module is the input end of the whole limiting amplifier, and the output end of the amplifier module is respectively connected with the input end of the signal amplitude detector module and the input end of the output driving module; the signal amplitude detector module, the signal period identification module and the signal detection logic generator module are sequentially connected; the output end of the signal detection logic generator module is connected with a JAM pin of the output driving module; the output end of the output driving module is the output end of the whole limiting amplifier.
The signal period identification module comprises a frequency divider, a delay TDL device, a delay TUL-TDL device, a delay TS device, a first inverter, a second inverter, a third inverter, a first AND gate circuit, a second AND gate circuit, a third AND gate circuit, a fourth AND gate circuit, a fifth AND gate circuit, a first D trigger, a second D trigger, a third D trigger and an OR gate circuit.
The CLK port of the frequency divider is the input end of the signal period discrimination module, and the Q port of the frequency divider is respectively connected with the input end of the first inverter, the input end of the delay TDL device, the second input end of the third AND gate circuit, the second input end of the fourth AND gate circuit and the CLK port of the third D trigger; the output end of the first inverter is respectively connected with the second input end of the first AND gate circuit and the second input end of the second AND gate circuit; the output end of the delay TDL device is respectively connected with the input end of the second inverter, the input end of the delay TUL-TDL device and the first input end of the fourth AND circuit; the output end of the second inverter is connected with the first input end of the second AND circuit; the output end of the delay TUL-TDL device is respectively connected with the first input end of the third AND circuit and the input end of the third inverter; the output end of the third inverter is connected with the first input end of the first AND circuit.
The output end of the first AND-gate circuit is connected with the RST port of the first D flip-flop, and the output end of the second AND-gate circuit is connected with the CLK port of the first D flip-flop; the output end of the third AND-gate circuit is connected with the RST port of the second D flip-flop, and the output end of the fourth AND-gate circuit is connected with the CLK port of the second D flip-flop; the Q port of the first D trigger is connected with the first input end of the fifth AND circuit, and the Q port of the second D trigger is connected with the second input end of the fifth AND circuit; the output end of the fifth AND circuit is connected with the input end of the delay TS device, the output end of the delay TS device is connected with the second input end of the OR gate circuit, and the output end of the OR gate circuit is connected with the D port of the third D trigger; the Q port of the third D flip-flop is the output end of the signal period discrimination module, and the Q port of the third D flip-flop is also connected with the first input end of the OR gate circuit.
The D port of the first D trigger and the D port of the second D trigger are both connected with a VH digital logic high level; and the RST port of the frequency divider and the RST port of the third D flip-flop are both connected with a RESET signal.
The invention has the beneficial effects that: compared with a signal period discrimination circuit realized by adopting an analog module, the signal period discrimination module is simpler in circuit architecture and circuit realization and does not need a specially customized analog function module; and digital modules are less susceptible to processing and external environments than analog modules. Therefore, the signal period identification module can be widely applied to OLT burst mode receivers realized by various processes and provides reliable period identification function.
The invention also provides a limiting amplifier signal identification method for a burst mode receiver, which comprises the following steps:
and S1, receiving the burst signal by using BM-LA.
And S2, amplifying the received burst signal through the amplifier module, and respectively outputting the amplified burst signal to the signal amplitude detector module and the output driving module.
And S3, detecting the amplitude of the amplified burst signal through the signal amplitude detector module, judging whether the amplitude is greater than a set threshold voltage, if so, entering a step S4, and if not, returning to the step S1.
S4, detecting the cycle of the amplified burst signal through the signal cycle discrimination module, and judging whether the cycle is in a preset time range, if so, entering the step S5, otherwise, returning to the step S1.
And S5, outputting an effective signal to the signal detection logic generator module through the signal period identification module.
And S6, outputting the SD signal to a JAM pin of the output driving module through the signal detection logic generator module, and enabling the output driving module to output the detected effective burst signal.
The invention has the beneficial effects that: according to the invention, the signal period identification circuit is added in the BM-LA of the burst mode receiver, effective signals are identified by comparing the difference between noise and lead codes, the probability of error detection of the effective signals can be greatly reduced, and compared with the traditional method that the threshold voltage of the LA is increased, the sensitivity index of the receiver can not be reduced. Meanwhile, the signal identification of the invention is carried out in the lead code period and only needs 2TB duration, so the invention can be widely applied to a high-speed OLT burst mode receiver.
Drawings
Fig. 1 is a schematic diagram illustrating a typical upstream transmission mode of a passive optical network.
Fig. 2 is a schematic diagram of an OLT burst mode receiver architecture.
Fig. 3 is a schematic diagram of a conventional BM-LA signal detection circuit.
Fig. 4 is a schematic diagram of a limiting amplifier for a burst mode receiver according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a circuit structure of a single-ended signal period discriminating module according to an embodiment of the invention.
Fig. 6 is a schematic diagram of a circuit architecture of a differential type signal period discriminating module according to an embodiment of the present invention.
Fig. 7 is a timing diagram of the signal period discriminating module according to an embodiment of the present invention when the input signal period TB is TDL < TB < TUL input.
Fig. 8 is a timing diagram of the signal period discriminating module according to an embodiment of the present invention when the input signal period TB is TDL < TUL < TB input.
Fig. 9 is a timing diagram of the signal period discriminating module according to an embodiment of the present invention when the input signal period TB is TB < TDL < TUL input.
Fig. 10 is a flowchart of a limiting amplifier signal discrimination method for a burst mode receiver according to a second embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It is to be understood that the embodiments shown and described in the drawings are merely exemplary and are intended to illustrate the principles and spirit of the invention, not to limit the scope of the invention.
The first embodiment is as follows:
an embodiment of the present invention provides a limiting amplifier for a burst mode receiver, as shown in fig. 4, including an amplifier module, a signal amplitude detector module, a signal period discrimination module, a signal detection logic generator module, and an output driver module; the input end of the amplifier module is the input end of the whole limiting amplifier, and the output end of the amplifier module is respectively connected with the input end of the signal amplitude detector module and the input end of the output driving module; the signal amplitude detector module, the signal period identification module and the signal detection logic generator module are sequentially connected; the output end of the signal detection logic generator module is connected with a JAM pin of the output driving module; the output end of the output driving module is the output end of the whole limiting amplifier.
As shown in fig. 5, the signal period discriminating module includes a frequency divider, a delay TDL device, a delay TUL-TDL device, a delay TS device, a first inverter, a second inverter, a third inverter, a first and circuit, a second and circuit, a third and circuit, a fourth and circuit, a fifth and circuit, a first D flip-flop, a second D flip-flop, a third D flip-flop, and an or gate circuit.
The CLK port of the frequency divider is the input end of the signal period discrimination module, and the Q port of the frequency divider is respectively connected with the input end of the first inverter, the input end of the delay TDL device, the second input end of the third AND gate circuit, the second input end of the fourth AND gate circuit and the CLK port of the third D trigger; the output end of the first inverter is respectively connected with the second input end of the first AND gate circuit and the second input end of the second AND gate circuit; the output end of the delay TDL device is respectively connected with the input end of the second inverter, the input end of the delay TUL-TDL device and the first input end of the fourth AND circuit; the output end of the second inverter is connected with the first input end of the second AND circuit; the output end of the delay TUL-TDL device is respectively connected with the first input end of the third AND circuit and the input end of the third inverter; the output end of the third inverter is connected with the first input end of the first AND circuit.
The output end of the first AND-gate circuit is connected with the RST port of the first D flip-flop, and the output end of the second AND-gate circuit is connected with the CLK port of the first D flip-flop; the output end of the third AND-gate circuit is connected with the RST port of the second D flip-flop, and the output end of the fourth AND-gate circuit is connected with the CLK port of the second D flip-flop; the Q port of the first D trigger is connected with the first input end of the fifth AND circuit, and the Q port of the second D trigger is connected with the second input end of the fifth AND circuit; the output end of the fifth AND circuit is connected with the input end of the delay TS device, the output end of the delay TS device is connected with the second input end of the OR gate circuit, and the output end of the OR gate circuit is connected with the D port of the third D trigger; the Q port of the third D flip-flop is the output end of the signal period discrimination module, and the Q port of the third D flip-flop is also connected with the first input end of the OR gate circuit.
The D port of the first D trigger and the D port of the second D trigger are both connected with a VH digital logic high level; and the RST port of the frequency divider and the RST port of the third D flip-flop are both connected with a RESET signal.
The frequency divider is used for dividing the frequency of the input signal by 2, namely the period of the output signal is 2 times of that of the input signal; the RST port is a reset end, and as long as the RST port receives a logic high level signal, the Q port is reset, so that the output of the Q port is a logic low level signal. The first inverter, the second inverter and the third inverter are used to phase-shift the phase of the signal by 180 degrees. The delay TDL device, the delay TUL-TDL device, and the delay TS device are used to delay the input signal by a preset time output. The first AND gate circuit, the second AND gate circuit, the third AND gate circuit, the fourth AND gate circuit and the fifth AND gate circuit are used for performing logical AND operation on two input signals. The or gate circuit is used for performing logical or operation on two input signals. The first D trigger, the second D trigger and the third D trigger are triggered by adopting a clock CLK rising edge, sample an input signal of a D port, then output to a Q port and keep the next clock rising edge; the RST port is a reset port, and as long as the port receives a logic high level signal, the Q port is reset, so that the output of the Q port is a logic low level signal.
In the embodiment of the present invention, the signal period discriminating module not only adopts the single-ended input single-ended output circuit architecture as shown in fig. 5, but also can be extended to a differential input differential output circuit architecture as shown in fig. 6, and the functions and connection relations thereof are completely consistent with the single-ended structure, except that the input end and the output end of each circuit element adopt a differential form, and the differential structure is mostly applied to the high-speed data input situation.
Timing diagrams of the signal period discriminating module provided by the embodiment of the invention corresponding to different inputs are respectively shown in fig. 7 to fig. 9. The meaning of each English letter in the timing diagram is as follows: TDL represents a lower limit value of a preset time; TUL represents an upper limit value of the preset time; TUL is generally set to be less than or equal to 2 TDL; TB denotes the period of the PON preamble, TB — 2 × TB; q1 to Q10, Q1N to Q3N, R1, R2, and SD correspond to the node names in fig. 5 one by one, and the time sequence relationship of each node is as follows:
din is an input PON preamble signal, which is a signal of a period TB, where TB is 2 × TB;
q1 is Din and passes through a frequency divider, the period generated after frequency division by two is 2TB signal, the positive duty cycle is TB, wherein the RESET RST port input of the frequency divider by two is a RESET signal;
q2 is the output signal of Q1 delayed by TDL duration through a delay TDL device, namely Q1;
q3 is the output signal of Q1 delayed by TUL duration through delay TDL device and delay TUL-TDL device, namely Q1;
Q1N, Q2N and Q3N are output signals of Q1, Q2 and Q3 passing through the first inverter, the second inverter and the third inverter respectively;
the Q4 is an output signal of the Q1 and Q2 signals after logical AND operation of the fourth AND circuit;
r1 is the output signal of Q1 and Q3 after the third AND gate logical AND operation;
q5 is the output signal of Q1N and Q2N signal after the second AND gate logical AND operation;
r2 is the output signal of Q1N and Q3N after the logical AND operation of the first AND gate circuit;
q6 is the output of the second D flip-flop, the CLK port input of the second D flip-flop is Q4, reset RST port input is R1, the D port is fixed to VH digital logic high level;
q7 is the output of the first D flip-flop, the CLK port input of the first D flip-flop is Q5, reset RST port input is R2, the D port is fixed to VH digital logic high level;
the Q8 is an output signal of the Q7 and Q6 signals after logical AND operation of a fifth AND circuit;
q9 is the output signal of Q8 through delaying TS ware, namely Q8 delay TS duration;
q10 is the output signal of Q9 and SD signal after OR gate logical OR operation;
SD is the output of the third D flip-flop, the CLK port input of the third D flip-flop is Q1, the RESET RST port input is the RESET signal, and the D port input is Q10.
Fig. 7 is a timing diagram of TB satisfying TDL < TB < TUL, i.e. the period TB of Din is between the preset times TDL and TUL. As can be seen in fig. 7, since the positive pulses of TDL < TB, Q1 and Q2 overlap, Q4 is the two-phase and the resulting positive pulse is within the positive pulse width of Q1; also, since the positive pulse of TB < TUL, Q3 and the positive pulse of the next cycle of Q1 overlap, R1 is the two-phase and the resulting positive pulse signal is within the next positive pulse width of Q1; q6 is a D flip-flop output with the rising edge of the positive pulse of Q4 as the clock sampling signal and the positive pulse of R1 as the reset signal, the positive pulse generated starting with the rising edge of Q4 and ending with the rising edge of R1. Similarly, Q5 and R2 can be obtained from the phases of Q1N, Q2N and Q3N; q7 is a D flip-flop output with the rising edge of the positive pulse of Q5 as the clock sampling signal and the positive pulse of R2 as the reset signal, the positive pulse generated starting with the rising edge of Q5 and ending with the rising edge of R2. Observing the timing relationship for both Q6 and Q7 is that Q7 differs from Q6 by one TB; q8 is the Q6 and Q7 phases, and since the positive pulse widths of Q6 and Q7 are greater than TB, with overlap, the Q8 positive pulse begins with the rising edge of Q7 and ends with the falling edge of the positive pulse of Q6. Q9 delays Q8 by a small time TS to ensure the establishment and maintenance time of the D trigger at the later stage; q10 is Q9 and SD signal phase or; SD is a D flip-flop output with Q10 as the data input and the positive pulse rising edge of Q1 as the clock sample signal; the initial state SD is 0 and therefore Q10 corresponds to Q9, the second cycle rising edge of Q1 is clocked, the sampling instant is within the positive pulse of Q9 and therefore the SD output is high, and once the SD output is high, the SD output is latched unless the RESET signal arrives. SD high indicates a valid signal is detected.
FIG. 8 shows that when TB satisfies TDL < TUL < TB, the period TB of Din is longer than the predetermined TDL and TUL. As can be seen, since the positive pulses of TDL < TUL < TB, Q1 and Q2 overlap, Q4 is the two-phase and the resulting positive pulse is within the positive pulse width of Q1; the positive pulses of Q1 and Q3 are overlapped, R1 is the phase of the two, and the generated positive pulse is also within the same positive pulse width of Q1; q6 begins with the rising edge of Q4 to the end of the rising edge of R1, generating a positive pulse within the positive pulse width of Q1. Similarly, Q5, R2 and Q7 can be obtained from the phases Q1N, Q2N and Q3N. The timing relationship for both Q6 and Q7 was observed to be that Q7 differs from Q6 by one TB, but since the positive pulse widths of Q6 and Q7 are less than TB, there is no overlap, and Q8 is the phase of Q6 and Q7, so no positive pulse is generated by Q8. Since Q8 remains low, Q9, Q10 are also low, and the SD output remains low, indicating that no valid signal is detected.
FIG. 9 shows that when TB satisfies TB < TDL < TUL, the period TB of Din is shorter than the predetermined TDL and TUL. As can be seen, since the second positive pulses of TB < TDL < TUL, Q2 and Q1 overlap, Q4 is the two-phase, resulting in a positive pulse within the second positive pulse width of Q1; the second positive pulses of Q3 and Q1 overlap, R1 is the two-phase and the resulting positive pulse is also within the second positive pulse width of Q1; the Q6 begins with the rising edge of Q4 to the end of the rising edge of R1, producing a positive pulse within the second positive pulse width of Q1. Similarly, Q5, R2 and Q7 can be obtained from the phases Q1N, Q2N and Q3N. The timing relationship for both Q6 and Q7 was observed to be that Q7 differs from Q6 by one TB, but since the positive pulse widths of Q6 and Q7 are less than TB, there is no overlap, and Q8 is the phase of Q6 and Q7, so no positive pulse is generated by Q8. Since Q8 remains low, Q9, Q10 are also low, and the SD output remains low, indicating that no valid signal is detected.
Example two:
an embodiment of the present invention provides a limiting amplifier signal discrimination method for a burst mode receiver, as shown in fig. 10, including the following steps:
and S1, receiving the burst signal by using BM-LA.
And S2, amplifying the received burst signal through the amplifier module, and respectively outputting the amplified burst signal to the signal amplitude detector module and the output driving module.
S3, detecting the amplitude of the amplified burst signal by the signal amplitude detector module, and judging whether the amplitude is larger than the set threshold voltage, if so, entering the step S4, otherwise, returning to the step S1, and receiving a new burst signal.
S4, detecting the cycle of the amplified burst signal through the signal cycle discrimination module, and judging whether the cycle is in a preset time range, if so, entering the step S5, otherwise, returning to the step S1, and receiving a new burst signal.
And S5, outputting an effective signal to the signal detection logic generator module through the signal period identification module.
And S6, outputting the SD signal to a JAM pin of the output driving module through the signal detection logic generator module, and enabling the output driving module to output the detected effective burst signal.
In the embodiment of the invention, only when the signal amplitude and the signal period meet the set conditions, the signal detection logic generator module outputs the detected SD signal, so that the output driving module is enabled to output the detected effective burst signal, and the finally output effective burst signal is the burst signal amplified by the amplifier module.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (3)
1. A limiting amplifier for a burst mode receiver is characterized by comprising an amplifier module, a signal amplitude detector module, a signal period identification module, a signal detection logic generator module and an output driving module; the input end of the amplifier module is the input end of the whole limiting amplifier, and the output end of the amplifier module is respectively connected with the input end of the signal amplitude detector module and the input end of the output driving module; the signal amplitude detector module, the signal period identification module and the signal detection logic generator module are sequentially connected; the output end of the signal detection logic generator module is connected with a JAM pin of the output driving module; the output end of the output driving module is the output end of the whole limiting amplifier;
the signal period identification module comprises a frequency divider, a delay TDL device, a delay TUL-TDL device, a delay TS device, a first inverter, a second inverter, a third inverter, a first AND gate circuit, a second AND gate circuit, a third AND gate circuit, a fourth AND gate circuit, a fifth AND gate circuit, a first D trigger, a second D trigger, a third D trigger and an OR gate circuit;
the CLK port of the frequency halver is the input end of the signal period discrimination module, and the Q port of the frequency halver is respectively connected with the input end of the first inverter, the input end of the delay TDL device, the second input end of the third AND gate circuit, the second input end of the fourth AND gate circuit and the CLK port of the third D trigger; the output end of the first inverter is respectively connected with the second input end of the first AND gate circuit and the second input end of the second AND gate circuit; the output end of the delay TDL device is respectively connected with the input end of the second inverter, the input end of the delay TUL-TDL device and the first input end of the fourth AND circuit; the output end of the second inverter is connected with the first input end of the second AND circuit; the output end of the delay TUL-TDL device is respectively connected with the first input end of the third AND gate circuit and the input end of the third inverter; the output end of the third inverter is connected with the first input end of the first AND circuit;
the output end of the first AND gate circuit is connected with an RST port of the first D flip-flop, and the output end of the second AND gate circuit is connected with a CLK port of the first D flip-flop; the output end of the third AND-gate circuit is connected with an RST port of the second D flip-flop, and the output end of the fourth AND-gate circuit is connected with a CLK port of the second D flip-flop; the Q port of the first D trigger is connected with the first input end of the fifth AND circuit, and the Q port of the second D trigger is connected with the second input end of the fifth AND circuit; the output end of the fifth AND gate circuit is connected with the input end of the delay TS device, the output end of the delay TS device is connected with the second input end of the OR gate circuit, and the output end of the OR gate circuit is connected with the D port of the third D trigger; and the Q port of the third D trigger is the output end of the signal period identification module, and is also connected with the first input end of the OR gate circuit.
2. The limiting amplifier of claim 1, wherein the D port of the first D flip-flop and the D port of the second D flip-flop are both connected to a VH digital logic high level.
3. The limiting amplifier according to claim 1, wherein the RST port of the frequency divider and the RST port of the third D flip-flop are both connected to a RESET signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711128993.0A CN107809285B (en) | 2017-11-15 | 2017-11-15 | Limiting amplifier for burst mode receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711128993.0A CN107809285B (en) | 2017-11-15 | 2017-11-15 | Limiting amplifier for burst mode receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107809285A CN107809285A (en) | 2018-03-16 |
| CN107809285B true CN107809285B (en) | 2019-12-20 |
Family
ID=61580143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711128993.0A Active CN107809285B (en) | 2017-11-15 | 2017-11-15 | Limiting amplifier for burst mode receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107809285B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109286389B (en) * | 2018-11-30 | 2023-10-27 | 成都嘉纳海威科技有限责任公司 | Signal discrimination device and method for burst mode limiting amplifier |
| CN113364446B (en) * | 2021-08-06 | 2021-12-17 | 深圳市迅特通信技术股份有限公司 | Burst coupling circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106209034A (en) * | 2016-07-22 | 2016-12-07 | 天津大学 | A kind of high frequency clock frequency detecting structure for attack resistance chip |
| CN106656323A (en) * | 2016-11-14 | 2017-05-10 | 成都嘉纳海威科技有限责任公司 | Signal detection circuit structure and method of passive optical network burst mode receiver |
| CN207475568U (en) * | 2017-11-15 | 2018-06-08 | 成都嘉纳海威科技有限责任公司 | A kind of limiting amplifier for burst-mode receiver |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100518023C (en) * | 2006-07-28 | 2009-07-22 | 武汉光迅科技股份有限公司 | Burst light-emitting signal power testing method and apparatus in PON system |
| CN101232360B (en) * | 2007-01-23 | 2011-08-10 | 华为技术有限公司 | Data receiving apparatus and method |
| CN102577182B (en) * | 2011-12-28 | 2014-11-05 | 华为技术有限公司 | Optical line terminal and method for processing amplified spontaneous emission by same |
-
2017
- 2017-11-15 CN CN201711128993.0A patent/CN107809285B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106209034A (en) * | 2016-07-22 | 2016-12-07 | 天津大学 | A kind of high frequency clock frequency detecting structure for attack resistance chip |
| CN106656323A (en) * | 2016-11-14 | 2017-05-10 | 成都嘉纳海威科技有限责任公司 | Signal detection circuit structure and method of passive optical network burst mode receiver |
| CN207475568U (en) * | 2017-11-15 | 2018-06-08 | 成都嘉纳海威科技有限责任公司 | A kind of limiting amplifier for burst-mode receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107809285A (en) | 2018-03-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7560683B2 (en) | Photo detecting circuit and noise elimination method utilized to produce a photo reception signal | |
| CN102257749B (en) | Transimpedance amplifier and PON system | |
| US8861584B2 (en) | Noise discriminator for passive optical network burst mode receiver | |
| US8483579B2 (en) | Phase detector circuit for clock and data recovery circuit and optical communication device having the same | |
| US5589683A (en) | Optical receiver apparatus for quickly detecting loss of a composite optical signal input employing a loss-of-clock detector | |
| CN107809285B (en) | Limiting amplifier for burst mode receiver | |
| US6323692B1 (en) | Transconductance compensation circuit having a phase detector circuit with cycle slipping recovery operation and method | |
| CN117579173B (en) | Signal loss detection circuit and chip | |
| EP2696519B1 (en) | Optical receiver | |
| CN207475568U (en) | A kind of limiting amplifier for burst-mode receiver | |
| KR102213933B1 (en) | Time to digital converter and distance measuring device comprising the same | |
| US8513994B2 (en) | State machine for deskew delay locked loop | |
| JP2962218B2 (en) | Digital optical receiving circuit | |
| JP4838279B2 (en) | Amplifier circuit | |
| CN101783706A (en) | Burst mode receiver | |
| US7864907B2 (en) | Data receiver with clock recovery circuit | |
| EP2161833B1 (en) | Gain switching circuit for preamplifier | |
| JP2007049475A (en) | Photo-receiver | |
| CN106656323A (en) | Signal detection circuit structure and method of passive optical network burst mode receiver | |
| KR100513275B1 (en) | A data recovery algorithm using data position detecting and a serial data receiver adopting the algorithm | |
| US6960960B2 (en) | Frequency detector detecting variation in frequency difference between data signal and clock signal | |
| US20090289664A1 (en) | Signal detecting apparatus, signal receiving apparatus, and signal detecting method | |
| EP2299615B1 (en) | Circuit for end-of-burst detection | |
| JP4691128B2 (en) | Amplifier circuit | |
| JP5215056B2 (en) | Bit rate judging device, bit rate judging method, signal discriminator and optical signal receiving discriminator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |