CN107809285A - A kind of limiting amplifier and its signal discrimination method for burst-mode receiver - Google Patents
A kind of limiting amplifier and its signal discrimination method for burst-mode receiver Download PDFInfo
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- CN107809285A CN107809285A CN201711128993.0A CN201711128993A CN107809285A CN 107809285 A CN107809285 A CN 107809285A CN 201711128993 A CN201711128993 A CN 201711128993A CN 107809285 A CN107809285 A CN 107809285A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/693—Arrangements for optimizing the preamplifier in the receiver
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/695—Arrangements for optimizing the decision element in the receiver, e.g. by using automatic threshold control
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Abstract
The invention discloses a kind of limiting amplifier and its signal discrimination method for burst-mode receiver, signal period discriminator circuit is added in burst-mode receiver BM LA, pass through the cycle of comparator input signal, noise and useful signal can be efficiently differentiated out, compared with tradition only detection signal amplitude method, the probability that useful signal detection makes a mistake can be greatly reduced.Simultaneously because the signal of the present invention, which differentiates, to be carried out in the lead code period, signal detection only needs 2TB durations, and time overhead is seldom, therefore can be widely used in high speed OLT burst-mode receivers.
Description
Technical field
The invention belongs to passive optical network technique field, and in particular to a kind of limited range enlargement for burst-mode receiver
The design of device and its signal discrimination method.
Background technology
The typical uplink of EPON (PON) uses time division multiple acess (TDMA) mode, as shown in figure 1, multiple light
Combining signal of the optical signal that the network terminal (ONT) is sent after Optical Distribution Network (ODN) enters optical line terminal (OLT), by
This visible OLT ends receiver is operated in burst mode.
The circuit framework of typical OLT receivers, as shown in Fig. 2 photodiode is the bursty data optical signal received
It is transformed into photoelectric current, is sent into burst mode trans-impedance amplifier (BM-TIA), burst mode limiting amplifier is sent into its output
(BM-LA) input, BM-LA carries out limited range enlargement to signal, while whether detection signal is effective；Finally, output data and
Detection signal (SD signals) arrives clock and data restoring circuit (CDR).
The algorithm of traditional OLT receiver BM-LA signal detections, its principle are the amplitudes that detection receives signal, then
By it compared with threshold voltage set in advance, when the signal amplitude detected is more than threshold value, then output detects effectively
The logic level of signal；If being less than threshold value, return and receive new signal, output holding is not detected by useful signal logic.
The circuit framework of traditional BM-LA signal detections, puts as shown in figure 3, BM-LA first passes around the signal received
Big device (AMP) module is amplified, and is then output to signal magnitude detector (Signal Level Detect) module, is detected
The amplitude of amplified signal, and by it compared with threshold value set in advance (Siganl Level Seting), comparative result
(Level Detect) is output to signal detection logic generator (Signal Detect Generator) module, output SD letters
Number give external interface；Usual SD can be connected to BM-LA JAM pins, to enable output driving (BUF) module.
However, due to the thermal noise of photodiode, device noise and the interference in the external world, can to input in no signal
In the case of, receive transient pulse voltage in BM-LA input, it is likely that more than threshold voltage, can thus cause BM-LA
Under no signal input condition, the false judgment of useful signal is detected, such error-logic, which exports, gives receiver system
System, it is likely that cause OLT to occur when TDMA works abnormal.Most applications, can only in order to reduce the probability of happening of mistake at present
The BM-LA threshold voltages set are heightened, but can so reduce the sensitivity of whole receiver, sacrifice the transmission distance of optical-fiber network
From.
The content of the invention
The purpose of the present invention is in noise and the influence of interference for traditional BM-LA detection signals algorithm and circuit framework
Under, a kind of the problem of signal detection easily makes a mistake, it is proposed that limiting amplifier and its letter for burst-mode receiver
Number discrimination method, the probability that useful signal detection mistake occurs can be greatly reduced.
The technical scheme is that：A kind of limiting amplifier for burst-mode receiver, including amplifier module,
Signal magnitude detector module, signal period identification module, signal detection logic generator block and output driving module；Put
The input of big device module is the input of whole limiting amplifier, and its output end is defeated with signal magnitude detector module respectively
Enter the input connection of end and output driving module；Signal magnitude detector module, signal period identification module and signal
Detection logic generator block is sequentially connected with；The output end of signal detection logic generator block and the JAM of output driving module
Pin connects；The output end of output driving module is the output end of whole limiting amplifier.
Wherein, signal period identification module includes two-divider, delay TDL devices, delay TUL-TDL devices, delay TS devices, the
One phase inverter, the second phase inverter, the 3rd phase inverter, first with gate circuit, second with gate circuit, the 3rd with gate circuit, the 4th with
Gate circuit, the 5th and gate circuit, the first d type flip flop, the second d type flip flop, 3d flip-flop and OR circuit.
The CLK ports of two-divider be signal period identification module input, its Q port respectively with the first phase inverter
Input, the input for postponing TDL devices, the 3rd with the second input of gate circuit, the 4th with the second input of gate circuit with
And the CLK ports connection of 3d flip-flop；The output end of first phase inverter respectively with first with the second input of gate circuit with
And second be connected with the second input of gate circuit；Postpone the output end input with the second phase inverter, the delay respectively of TDL devices
The input of TUL-TDL devices and the 4th it is connected with the first input end of gate circuit；The output end of second phase inverter with second with
The first input end connection of gate circuit；Postpone the output ends of TUL-TDL devices respectively with the 3rd with the first input end of gate circuit with
And the 3rd phase inverter input connection；The output end of 3rd phase inverter is connected with first with the first input end of gate circuit.
First is connected with the output end of gate circuit with the RST ports of the first d type flip flop, second with the output end of gate circuit with
The CLK ports connection of first d type flip flop；3rd is connected with the output end of gate circuit with the RST ports of the second d type flip flop, and the 4th
It is connected with the output end of gate circuit with the CLK ports of the second d type flip flop；The Q ports of first d type flip flop and the 5th and gate circuit
First input end is connected, and the Q ports of the second d type flip flop are connected with the 5th with the second input of gate circuit；5th and gate circuit
Output end with postpone TS devices input be connected, postpone TS devices output end and OR circuit the second input connection, or
The output end of gate circuit is connected with the D ports of 3d flip-flop；The Q ports of 3d flip-flop are signal period identification module
Output end, and the Q ports of 3d flip-flop are also connected with the first input end of OR circuit.
The D ports of first d type flip flop and the D ports of the second d type flip flop are connected with VH digital logic high levels；Two divided-frequency
The RST ports of device and the RST ports of 3d flip-flop are connected with RESET signal.
The beneficial effects of the invention are as follows：The burst mode limiting amplifier of the present invention, signal period identification module therein
All it is made up of basic digital logic module, compared with the signal period discriminator circuit realized using analog module, circuit frame
Structure and circuit realiration are simpler, it is not necessary to the analog functional module of custom-made；And digital module is compared to analog module more
Add the influence for being not susceptible to technique and external environment condition.Therefore the signal period identification module of the present invention can be widely used in various works
In the OLT burst-mode receivers that skill is realized, and provide reliable cycle identification function.
Present invention also offers a kind of limiting amplifier signal discrimination method for burst-mode receiver, including it is following
Step：
S1, use BM-LA reception bursts.
S2, by amplifier module the burst received is amplified, and the burst after amplification is distinguished
Export to signal magnitude detector module and output driving module.
S3, the amplitude by the burst after the detection amplification of signal magnitude detector module, and judge whether it is more than
The threshold voltage of setting, if then entering step S4, otherwise return to step S1.
S4, the cycle by the burst after the detection amplification of signal period identification module, and judge it whether default
Time range in, if then entering step S5, otherwise return to step S1.
S5, pass through signal period identification module output useful signal to signal detection logic generator block.
S6, the JAM pins by signal detection logic generator block output SD signals to output driving module, are enabled defeated
Go out effective burst that drive module output detects.
The beneficial effects of the invention are as follows：The present invention adds signal period discriminating electricity in burst-mode receiver BM-LA
Road, by comparing the difference of noise and lead code, useful signal is identified, useful signal detection can be greatly reduced mistake occurs
Probability, compared with conventional method is by heightening LA threshold voltages, will not reduce receiver sensitivity index by mistake.Simultaneously because this
The signal of invention, which differentiates, to be carried out in the lead code period, it is only necessary to 2TB durations, therefore high speed OLT burst moulds can be widely used in
Formula receiver.
Brief description of the drawings
Fig. 1 show the typical uplink transmission mode schematic diagram of EPON.
Fig. 2 show OLT burst-mode receiver configuration diagrams.
Fig. 3 show traditional BM-LA signal deteching circuits configuration diagram.
A kind of limiting amplifier for burst-mode receiver that Fig. 4 show the offer of the embodiment of the present invention one is illustrated
Figure.
Fig. 5 show the single-ended format signal period identification module circuit framework schematic diagram of the offer of the embodiment of the present invention one.
Fig. 6 show the difference form signal period identification module circuit framework schematic diagram of the offer of the embodiment of the present invention one.
The signal period identification module that Fig. 7 show the offer of the embodiment of the present invention one in input signal cycle TB is TDL<TB
<Timing diagram under TUL input conditions.
The signal period identification module that Fig. 8 show the offer of the embodiment of the present invention one in input signal cycle TB is TDL<
TUL<Timing diagram under TB input conditions.
The signal period identification module that Fig. 9 show the offer of the embodiment of the present invention one in input signal cycle TB is TB<TDL
<Timing diagram under TUL input conditions.
Figure 10 show a kind of limiting amplifier signal for burst-mode receiver of the offer of the embodiment of the present invention two
Discrimination method flow chart.
Embodiment
The illustrative embodiments of the present invention are described in detail referring now to accompanying drawing.It should be appreciated that shown in accompanying drawing and
What the embodiment of description was merely exemplary, it is intended that explain the principle and spirit of the present invention, and not limit the model of the present invention
Enclose.
Embodiment one：
The embodiments of the invention provide a kind of limiting amplifier for burst-mode receiver, as shown in figure 4, including putting
Big device module, signal magnitude detector module, signal period identification module, signal detection logic generator block and output are driven
Dynamic model block；The input of amplifier module be whole limiting amplifier input, its output end respectively with signal amplitude detection
The input of device module and the input connection of output driving module；Signal magnitude detector module, signal period differentiate mould
Block and signal detection logic generator block are sequentially connected with；The output end and output driving of signal detection logic generator block
The JAM pins connection of module；The output end of output driving module is the output end of whole limiting amplifier.
Wherein, as shown in figure 5, signal period identification module include two-divider, delay TDL devices, delay TUL-TDL devices,
Delay TS devices, the first phase inverter, the second phase inverter, the 3rd phase inverter, first and gate circuit, second and gate circuit, the 3rd and door
Circuit, the 4th and gate circuit, the 5th and gate circuit, the first d type flip flop, the second d type flip flop, 3d flip-flop and OR gate electricity
Road.
The CLK ports of two-divider be signal period identification module input, its Q port respectively with the first phase inverter
Input, the input for postponing TDL devices, the 3rd with the second input of gate circuit, the 4th with the second input of gate circuit with
And the CLK ports connection of 3d flip-flop；The output end of first phase inverter respectively with first with the second input of gate circuit with
And second be connected with the second input of gate circuit；Postpone the output end input with the second phase inverter, the delay respectively of TDL devices
The input of TUL-TDL devices and the 4th it is connected with the first input end of gate circuit；The output end of second phase inverter with second with
The first input end connection of gate circuit；Postpone the output ends of TUL-TDL devices respectively with the 3rd with the first input end of gate circuit with
And the 3rd phase inverter input connection；The output end of 3rd phase inverter is connected with first with the first input end of gate circuit.
First is connected with the output end of gate circuit with the RST ports of the first d type flip flop, second with the output end of gate circuit with
The CLK ports connection of first d type flip flop；3rd is connected with the output end of gate circuit with the RST ports of the second d type flip flop, and the 4th
It is connected with the output end of gate circuit with the CLK ports of the second d type flip flop；The Q ports of first d type flip flop and the 5th and gate circuit
First input end is connected, and the Q ports of the second d type flip flop are connected with the 5th with the second input of gate circuit；5th and gate circuit
Output end with postpone TS devices input be connected, postpone TS devices output end and OR circuit the second input connection, or
The output end of gate circuit is connected with the D ports of 3d flip-flop；The Q ports of 3d flip-flop are signal period identification module
Output end, and the Q ports of 3d flip-flop are also connected with the first input end of OR circuit.
The D ports of first d type flip flop and the D ports of the second d type flip flop are connected with VH digital logic high levels；Two divided-frequency
The RST ports of device and the RST ports of 3d flip-flop are connected with RESET signal.
Two-divider is used to the frequency of input signal is carried out to remove 2, i.e. the cycle of output signal is 2 times of input signal；
Its RST port is reset terminal, as long as the port receives logic-high signal, then Q ports is resetted, and makes its output be
Logic-low signal.First phase inverter, the second phase inverter and the 3rd phase inverter are used for the phase that the phase of signal is carried out to 180 degree
Move.Postpone TDL devices, delay TUL-TDL devices and delay TS devices to be used to export the input signal delay default time.First and door
Circuit, second are used for two signals to input with gate circuit, the 3rd with gate circuit, the 4th with gate circuit and the 5th with gate circuit
Make logic and operation.OR circuit is used to make logic or computing to two signals of input.First d type flip flop, the second d type flip flop
Triggered with 3d flip-flop using clock CLK rising edges, the input signal of D ports is sampled, is then output to Q ports, and
Remain to rising edge clock arrival next time；Its RST port is reseting port, as long as the port receives logic high letter
Number, then Q ports are resetted, it is logic-low signal to make its output.
In the embodiment of the present invention, signal period identification module is except using single ended input Single-end output electricity as shown in Figure 5
Road framework, differential-input differential output circuit framework is also extended to, as shown in fig. 6, its function and annexation and single-ended knot
Structure is completely the same, and simply the input of each circuit element and output end use difference form, and differential configuration majority is to apply
Under high-speed data input situation.
Signal period identification module provided in an embodiment of the present invention corresponds to the timing diagram of different inputs respectively such as Fig. 7~Fig. 9
It is shown.The implication of each English alphabet is as follows in timing diagram：TDL represents the lower limit of preset time；TUL represents the upper of preset time
Limit value；TUL≤2*TDL is generally set；TB represents the cycle of PON lead codes, TB=2*Tb；Q1~Q10, Q1N~Q3N
And the node name in R1, R2, SD and Fig. 5 corresponds, the sequential relationship of each node is as follows：
Din be input PON preamble signals, its be cycle T B signal, TB=2*Tb；
Q1 is that Din passes through two-divider, and the cycle generated after two divided-frequency is 2*TB signals, and its positive dutycycle is TB, wherein
The reset RST ports input of two-divider is RESET signal；
Q2 is that Q1 postpones the output signal of TDL durations by delay TDL devices, i.e. Q1；
Q3 is that Q1 postpones the output signal of TUL durations by delay TDL devices and delay TUL-TDL devices, i.e. Q1；
Q1N, Q2N, Q3N correspond to respectively Q1, Q2, Q3 by the first phase inverter, the second phase inverter, the 3rd phase inverter it is defeated
Go out signal；
Q4 is output signals of the Q1 with Q2 signals after the 4th and gate circuit logic and operation；
R1 is output signals of the Q1 with Q3 signals after the 3rd and gate circuit logic and operation；
Q5 is output signals of the Q1N with Q2N signals after second and gate circuit logic and operation；
R2 is output signals of the Q1N with Q3N signals after first and gate circuit logic and operation；
Q6 is the output of the second d type flip flop, and the CLK ports input of the second d type flip flop is Q4, resets the input of RST ports and is
R1, D port are fixed as VH digital logic high levels；
Q7 is the output of the first d type flip flop, and the CLK ports input of the first d type flip flop is Q5, resets the input of RST ports and is
R2, D port are fixed as VH digital logic high levels；
Q8 is output signals of the Q7 with Q6 signals after the 5th and gate circuit logic and operation；
Q9 is that Q8 postpones the output signal of TS durations by delay TS devices, i.e. Q8；
Q10 is Q9 and output signal of the SD signals after OR circuit logic or computing；
SD is the output of 3d flip-flop, and the CLK ports input of 3d flip-flop is Q1, resets the input of RST ports and is
RESET signal, the input of D ports is Q10.
Fig. 7 is that TB meets TDL<TB<TUL timing diagram, namely Din cycle T B presetting time TDL and TUL it
Between.As can be seen from Figure 7, due to TDL<TB, Q1 and Q2 positive pulse have it is overlapping, Q4 for both mutually with caused positive pulse exists
In Q1 positive pulse width；Also due to TB<TUL, Q3 positive pulse and the positive pulse of Q1 next cycle just have overlapping, R1
For both mutually with caused positive pulse signal is in Q1 next positive pulse width；Q6 is the positive pulse rising edge work with Q4
For clock sampling signal, R1 positive pulse do reset signal d type flip flop output, caused positive pulse with Q4 rising edges start to
R1 rising edges terminate.Similarly, by Q1N, Q2N and Q3N phase and Q5 and R2 can be obtained；Q7 be using Q5 positive pulse rising edge as when
Clock sampled signal, R2 positive pulse do the d type flip flop output of reset signal, and caused positive pulse is started to R2 with Q5 rising edges
Edge is risen to terminate.The sequential relationship for observing both Q6 and Q7 is that Q7 differs a TB with Q6；Q8 be Q6 and Q7 phases with, due to Q6 and
Q7 positive pulse width is more than TB, and both have overlapping, therefore Q8 positive pulses are started to Q6 positive pulse trailing edge with Q7 rising edges
Terminate.Q9 is that Q8 postpones a less duration TS, and the retention time is established for guarantee rear class d type flip flop；Q10 is that Q9 and SD believes
Number phase or；SD is using Q10 as data input, and Q1 positive pulse rising edge exports as the d type flip flop of clock sampling signal；Just
Primary state SD is 0, therefore Q10 is correspondingly equal to Q9, and Q1 second round rising edge is as clock, positive pulse of the sampling instant in Q9
It is interior, therefore SD outputs are height, once SD outputs are height, then SD outputs are latched, unless RESET reset signals arrive.SD is high table
Show and detect useful signal.
Fig. 8 meets TDL as TB<TUL<TB, namely Din cycle T B are longer than presetting TDL and TUL.Can from figure
Find out, due to TDL<TUL<TB, Q1 and Q2 positive pulse have overlapping, both Q4 is phase and positive arteries and veins of the caused positive pulse in Q1
Rush in width；Q1 and Q3 positive pulse have it is overlapping, R1 for both mutually with caused positive pulse is also wide in Q1 same positive pulse
In degree；Q6 starts to R1 rising edges to terminate with Q4 rising edges, and caused positive pulse is in Q1 positive pulse width.Similarly, can be by
Q1N, Q2N and Q3N phase are with obtaining Q5, R2 and Q7.The sequential relationship for observing both Q6 and Q7 is that Q7 differs a TB with Q6, but
Because Q6 and Q7 positive pulse width is less than TB, both are not overlapping, and Q8 is Q6 and Q7 phases and therefore Q8 produces without positive pulse
It is raw.Because Q8 remains low, Q9, Q10 are also to be low, and SD outputs remain low, and expression is not detected by useful signal.
Fig. 9 meets TB as TB<TDL<TUL, namely Din cycle T B are shorter than presetting TDL and TUL.Can from figure
Find out, due to TB<TDL<TUL, Q2 and Q1 second positive pulse have it is overlapping, Q4 for both mutually with caused positive pulse is in Q1
Second positive pulse width in；Q3 and Q1 second positive pulse have it is overlapping, R1 for both mutually with caused positive pulse also exists
In Q1 second positive pulse width；Q6 starts to R1 rising edges to terminate with Q4 rising edges, caused positive pulse in Q1 second
In individual positive pulse width.Similarly, by Q1N, Q2N and Q3N phase and Q5, R2 and Q7 can be obtained.The sequential for observing both Q6 and Q7 is closed
System is that Q7 differs a TB with Q6, but because Q6 and Q7 positive pulse width is less than TB, and both are not overlapping, and Q8 be Q6 and
Q7 phases with, therefore Q8 without positive pulse produce.Because Q8 remains low, Q9, Q10 are also to be low, and SD outputs remain low, and expression is not examined
Measure useful signal.
Embodiment two：
The embodiments of the invention provide a kind of limiting amplifier signal discrimination method for burst-mode receiver, such as schemes
Shown in 10, comprise the following steps：
S1, use BM-LA reception bursts.
S2, by amplifier module the burst received is amplified, and the burst after amplification is distinguished
Export to signal magnitude detector module and output driving module.
S3, the amplitude by the burst after the detection amplification of signal magnitude detector module, and judge whether it is more than
The threshold voltage of setting, if then entering step S4, otherwise return to step S1, receives new burst.
S4, the cycle by the burst after the detection amplification of signal period identification module, and judge it whether default
Time range in, if then entering step S5, otherwise return to step S1, receives new burst.
S5, pass through signal period identification module output useful signal to signal detection logic generator block.
S6, the JAM pins by signal detection logic generator block output SD signals to output driving module, are enabled defeated
Go out effective burst that drive module output detects.
In the embodiment of the present invention, only when all meeting set condition in signal amplitude and cycle, signal detection logic produces
Device module, which can just export, detects SD signals, and then effective burst that enabled output driving module output detects, finally
Effective burst of output is the burst after the amplification of amplifier module.
One of ordinary skill in the art will be appreciated that embodiment described here is to aid in reader and understands this hair
Bright principle, it should be understood that protection scope of the present invention is not limited to such especially statement and embodiment.This area
Those of ordinary skill can make according to these technical inspirations disclosed by the invention various does not depart from the other each of essence of the invention
The specific deformation of kind and combination, these deform and combined still within the scope of the present invention.
Claims (4)
1. a kind of limiting amplifier for burst-mode receiver, it is characterised in that examined including amplifier module, signal amplitude
Survey device module, signal period identification module, signal detection logic generator block and output driving module；The amplifier mould
The input of block is the input of the whole limiting amplifier, the input with signal magnitude detector module respectively of its output end
The connection of the input of end and output driving module；The signal magnitude detector module, signal period identification module and letter
Number detection logic generator block be sequentially connected with；The output end of the signal detection logic generator block and output driving module
JAM pins connection；The output end of the output driving module is the output end of the whole limiting amplifier；
The signal period identification module includes two-divider, delay TDL devices, delay TUL-TDL devices, delay TS devices, first anti-
Phase device, the second phase inverter, the 3rd phase inverter, first and gate circuit, second and gate circuit, the 3rd and gate circuit, the 4th and door electricity
Road, the 5th and gate circuit, the first d type flip flop, the second d type flip flop, 3d flip-flop and OR circuit；
The CLK ports of the two-divider are the input of the signal period identification module, and its Q port is anti-phase with first respectively
The input of device, the input for postponing TDL devices, the 3rd with the second input of gate circuit, the 4th with the second input of gate circuit
End and the connection of the CLK ports of 3d flip-flop；The output end of first phase inverter is respectively with first and the second of gate circuit
Input and second it is connected with the second input of gate circuit；The output end of the delay TDL devices respectively with the second phase inverter
Input, postpone the input of TUL-TDL devices and the 4th be connected with the first input end of gate circuit；Second phase inverter
Output end be connected with second with the first input end of gate circuit；The output end of the delay TUL-TDL devices respectively with the 3rd with
The input of the first input end of gate circuit and the 3rd phase inverter connects；The output end of 3rd phase inverter and first and door
The first input end connection of circuit；
Described first is connected with the output end of gate circuit with the RST ports of the first d type flip flop, described second with the output of gate circuit
End is connected with the CLK ports of the first d type flip flop；Described 3rd connects with the output end of gate circuit and the RST ports of the second d type flip flop
Connect, the described 4th is connected with the output end of gate circuit with the CLK ports of the second d type flip flop；The Q ports of first d type flip flop
It is connected with the 5th with the first input end of gate circuit, the Q ports of second d type flip flop input with the 5th and the second of gate circuit
End connection；Described 5th be connected with the output end of gate circuit with postponing the input of TS devices, the output end of the delay TS devices and
The second input connection of OR circuit, the output end of the OR circuit are connected with the D ports of 3d flip-flop；Described
The Q ports of 3d flip-flop be the signal period identification module output end, and the Q ports of the 3d flip-flop also with or
The first input end connection of gate circuit.
2. limiting amplifier according to claim 1, it is characterised in that the D ports of first d type flip flop and the 2nd D
The D ports of trigger are connected with VH digital logic high levels.
3. limiting amplifier according to claim 1, it is characterised in that the RST ports of the two-divider and the 3rd D are touched
The RST ports of hair device are connected with RESET signal.
4. a kind of limiting amplifier signal discrimination method for burst-mode receiver, it is characterised in that comprise the following steps：
S1, use BM-LA reception bursts；
S2, by amplifier module the burst received is amplified, and the burst after amplification is exported respectively
To signal magnitude detector module and output driving module；
S3, the amplitude by the burst after the detection amplification of signal magnitude detector module, and judge whether it is more than setting
Threshold voltage, if then entering step S4, otherwise return to step S1；
S4, the cycle by the burst after the detection amplification of signal period identification module, and judge it whether when default
Between in the range of, if then entering step S5, otherwise return to step S1；
S5, pass through signal period identification module output useful signal to signal detection logic generator block；
S6, the JAM pins by signal detection logic generator block output SD signals to output driving module, enable output and drive
Effective burst that the output of dynamic model block detects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711128993.0A CN107809285B (en) | 2017-11-15 | 2017-11-15 | Limiting amplifier for burst mode receiver |
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|---|---|---|---|
| CN201711128993.0A CN107809285B (en) | 2017-11-15 | 2017-11-15 | Limiting amplifier for burst mode receiver |
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| CN107809285A true CN107809285A (en) | 2018-03-16 |
| CN107809285B CN107809285B (en) | 2019-12-20 |
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