CN107807479A - 阵列基板和显示面板 - Google Patents

阵列基板和显示面板 Download PDF

Info

Publication number
CN107807479A
CN107807479A CN201711131501.3A CN201711131501A CN107807479A CN 107807479 A CN107807479 A CN 107807479A CN 201711131501 A CN201711131501 A CN 201711131501A CN 107807479 A CN107807479 A CN 107807479A
Authority
CN
China
Prior art keywords
base palte
array base
binding
bindings
bindings bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201711131501.3A
Other languages
English (en)
Other versions
CN107807479B (zh
Inventor
宋月胜
许鹤
高东来
王文博
关锋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qingdao Boe Optoelectronic Technology Co ltd
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
BOE Hebei Mobile Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, BOE Hebei Mobile Display Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201711131501.3A priority Critical patent/CN107807479B/zh
Publication of CN107807479A publication Critical patent/CN107807479A/zh
Priority to US16/150,497 priority patent/US10707241B2/en
Application granted granted Critical
Publication of CN107807479B publication Critical patent/CN107807479B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本发明公开了一种阵列基板和显示面板，涉及显示技术领域，主要目的是用于使工作人员能够快速的查找到阵列基板中绑定区域内的预设序号的绑定位。本发明的主要技术方案为：一种阵列基板，包括：基板本体，所述基板本体的一侧具有绑定区域，所述绑定区域内具有多个依次排序设置的绑定位，多个排序设置的所述绑定位中的预设排序位置处设有区空位，所述区空位用于将所述绑定区域分隔成多个绑定子区域，使每个所述绑定子区域内具有预设数量的所述绑定位。本发明主要用于设置信号线。

Description

阵列基板和显示面板
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板和显示面板。
背景技术
近年来随着人们对显示器显示效果的要求提高，液晶显示器内每英寸所拥有的像素数目不断提高，这就使显示面板内单位面积上排布更多的像素，对应的就具有更多的布线。
现有技术中，液晶显示器的阵列基板中显示区域外围的绑定区域即PAD区域上依次布设有多个绑定位，每个绑定位上均绑定有数据线或信号线，用于连接集成电路模块，以控制液晶显示器的显示，但是，当液晶显示器出现暗线等显示不良的现象时，工作人员在确认绑定区域中的问题绑定位的序号后，由于绑定位上没有标号，这样工作人员就需要对绑定区域上依次设置的多个绑定位进行计数排序，直至排序到对应序号，才可以查找到该问题绑定位，而这种查找方式的查找效率较低，工作人员的工作量较大。
发明内容
有鉴于此，本发明实施例提供一种阵列基板和显示面板，主要目的是用于使工作人员能够快速的查找到阵列基板中绑定区域内的预设序号的绑定位。
为达到上述目的，本发明主要提供如下技术方案：
一方面，本发明实施例提供了一种阵列基板，其特征在于，包括：
基板本体，所述基板本体的一侧具有绑定区域，所述绑定区域内具有多个依次排序设置的绑定位，多个排序设置的所述绑定位中的预设排序位置处设有区空位，所述区空位用于将所述绑定区域分隔成多个绑定子区域，使每个所述绑定子区域内具有预设数量的所述绑定位。
进一步的，所述区空位为多个，多个所述区空位分别设置于多个所述绑定位中的多个预设排序位置处。
进一步的，每个所述绑定子区域内的所述绑定位的数量相同。
进一步的，每个所述区空位上均设有标号。
进一步的，所述标号记录所述区空位对应的所述绑定子区域内所述绑定位的数量。
进一步的，所述标号记录所述区空位所对应的所述绑定位的排序序号。
进一步的，每个所述绑定子区域内的绑定位数量为40-50个。
进一步的，多个所述绑定位依次排成多个相互平行的横排，每个所述横排上的所述区空位与其它所述横排上对应的所述区空位在同一竖列上。
另一方面，本发明实施例还提供了一种显示面板，包括：所述的阵列基板。
本发明实施例提供了一种阵列基板，用于使工作人员能够快速的查找到阵列基板中绑定区域内的预设序号的绑定位，现有技术中，工作人员需要排查阵列基板中绑定区域内预设序号的绑定位时，通常需要从第一个绑定位开始一一查数，查数过程非常的费力，而且还经常容易出现查数错位的问题，进而导致排查效率低的问题，与现有技术相比，本申请文件提供的阵列基板包括：基板本体，基板本体的一侧具有绑定区域，绑定区域内具有多个依次排序设置的绑定位，多个排序设置的绑定位中的预设排序位置处设有区空位，区空位用于将绑定区域分隔成多个绑定子区域，使每个绑定子区域内具有预设数量的绑定位，当工作人员需要排查预设序号的绑定位时，可以首先判断预设序号的绑定位所在的绑定子区域，然后再在绑定子区域内进行查数，这样就减少的查数的数量，进而可以减少工作人员查找阵列基板中绑定区域内的预设序号的绑定位的时间，提高了查找效率。
附图说明
图1为本发明实施例提供的阵列基板的结构示意图；
图2为本发明实施例提供的阵列基板的局部结构放大图。
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例，对依据本发明提出的阵列基板其具体实施方式、结构、特征及其功效，详细说明如后。
如图1、图2所示，本发明实施例提供了一种阵列基板，包括：
基板本体，基板本体的一侧具有绑定区域1，绑定区域1内具有多个依次排序设置的绑定位2，多个排序设置的绑定位2中的预设排序位置处设有区空位3，区空位3用于将绑定区域1分隔成多个绑定子区域4，使每个绑定子区域4内具有预设数量的绑定位2。
其中，阵列基板上一般包括阵列区域和绑定区域1，其中，阵列区域是阵列基板的工作区域，具有栅线、数据线及公共电极线等信号线、像素电极、公共电极及薄膜晶体管(TFT)等组件，通过这些组件形成驱动液晶的电场；而绑定区域1又称为PAD区域，绑定区域1位于阵列基板的四个边中的其中一个或相邻的两个边上，绑定区域1内一般只设有信号线或数据线，阵列基板能够通过绑定区域1内的信号线或数据线与外部的驱动电路板的引线相互连接。
其中，上述的绑定区域1内可以具有多个绑定位2，每个绑定位2用于绑定绑定一条信号线，每条信号线的一端用于连接阵列基板上对应像素的集成电路模块，即(单层区信号传输金手指，dummy bump)，另一端用于连接外部的驱动电路板，其中，绑定区域1内的多个绑定位2可以是依次排序设置的，例如：多个绑定位2可以沿一条直线依次排序设置；或者多个绑定位2可以沿多条相互平行的直线依次排序设置，其具体的排列方式可以有多种，在此不作限定；绑定区域1内的绑定位2一般可以有300至400个，由于多个绑定位2都是排序设置的，工作人员在排查显示面板的故障时，可以首先查找绑定区域1的问题绑定位2，再对应查找相应的问题集成电路模块，但是，由于绑定区域1的绑定位2没有排序号的标识，这样工作人员在查找对应序号位置的绑定位2就非常的麻烦，例如：当工作人员需要排查序号为150的绑定位2时，就需要从序号为1的绑定位2开始进行查数，直至查数到序号为150的绑定位为止，才可以进行排除问题，非常的费力，另外，绑定区域1内绑定位2的规格又非常的微小，工作人员往往需要通过显微镜才可以进行查数，这样就容易出现查数错位的问题，严重影响排除的准确性，降低排除效率。
其中，上述多个排序设置的绑定位2中的预设排序位置处设有区空位3，其中，区空位3的数量可以为一个也可以为多个，在此不作限定，通过区空位3 可以将绑定区域1分隔成多个绑定子区域4，使每个绑定子区域4内具有预设数量的绑定位2，这样就可以提高排除的效率，例如：共320个绑定位2，其中，每40个绑定位2处设有一个区空位3，当工作人员需要排查第150个绑定位2 时，首先，工作人员通过显微镜可以首先判断问题绑定位2在第4个绑定子区域4内，其中，第4个绑定子区域4内的绑定位序号为130至160，然后，再在第4个绑定子区域4内进行查数，这样就可以提高绑定位2的查数效率，保证了查数的准确性。其中，区空位3可以有多种形式，例如：可以为预留的间隔空间，也可以为没有绑定信号线的绑定位，还可以为特殊标识，在此不作限定。
本发明实施例提供了一种阵列基板，用于使工作人员能够快速的查找到阵列基板中绑定区域内的预设序号的绑定位，现有技术中，工作人员需要排查阵列基板中绑定区域内预设序号的绑定位时，通常需要从第一个绑定位开始一一查数，查数过程非常的费力，而且还经常容易出现查数错位的问题，进而导致排查效率低的问题，与现有技术相比，本申请文件提供的阵列基板包括：基板本体，基板本体的一侧具有绑定区域，绑定区域内具有多个依次排序设置的绑定位，多个排序设置的绑定位中的预设排序位置处设有区空位，区空位用于将绑定区域分隔成多个绑定子区域，使每个绑定子区域内具有预设数量的绑定位，当工作人员需要排查预设序号的绑定位时，可以首先判断预设序号的绑定位所在的绑定子区域，然后再在绑定子区域内进行查数，这样就减少的查数的数量，进而可以减少工作人员查找阵列基板中绑定区域内的预设序号的绑定位的时间，提高了查找效率。
另外，由于阵列基板上的IC bump与cummy bump之间都是通过异向导电胶(ACF)连接，而IC bump与cummy bump连接导通是否良好需要观察异向导电胶中导电粒子的压开状态，而本实施例中，通过上述区空位可以直接观察到导电粒子的压开状态以及多个位置的压痕是否稳定，进而可以加快调试人员的工作效率。
进一步的，区空位3为多个，多个区空位3分别设置于多个绑定位2中的多个预设排序位置处。本实施例中，由于阵列基板的绑定区域1中的绑定位2 较多，一般可以为300至400个，为了提高对预设序号的绑定位2进行排查，可以设有多个区空位3，这样每个区空位3所分隔成的绑定子区域4内的绑定位 2就较少，进而可以减少绑定位2查数的数量，提高了排查效率。
进一步的，每个绑定子区域4内的绑定位2的数量相同。本实施例中，工作人员在排查预设序号的绑定位2时，由于每个绑定子区域4内的绑定位2的数量相同，这样工作人员可以更加快速的判断出预设序号的绑定位2所处的绑定子区域4，进而可以提高排除速度，节约排除时间。
进一步的，每个区空位3上均设有标号5。本实施例中，工作人员在排查预设序号的绑定位2时，工作人员可以通过区空位3上的标号5快速的判断出该区空位3所对应绑定位2的排序位置，这样就可以进一步的提高工作人员的排查速度。
上述标号5的记录内容可以有多种，可选地，标号5记录区空位3对应的绑定子区域4内绑定位2的数量。本实施例中，工作人员通过标号5可以快速的了解其对应的绑定子区域4内的绑定位2数量，例如：每40个绑定位2上设有一个区空位3，这样每个区空位3上的标号5可以为40，这样工作人员通过排序号可以快速的了解每个绑定子区域4内的绑定位2数量，进而可以提高工作人员的排查效率。
上述标号5还可以记录其他的内容，可选地，标号5记录区空位3所对应的绑定位2的排序序号，例如：每40个绑定位2上设有一个区空位3，这样第一个区空位的标号5可以为40，第二个区空位的标号5可以为80，第三个区空位的标号5可以为120，以此类推，通过区空位3上的标号5可以快速的辨别该区空位3所对应的绑定位2的排序序号，进一步提高工作人员的排查效率。
进一步的，每个绑定子区域4内的绑定位2数量为40-50个。本实施例中，由于阵列基板的绑定区域1中的绑定位2一般可以为300至400个，而每40-50 个绑定位2分隔为一个绑定子区域4，不仅可以减少工作人员的查数时间，还可以减小区空位3对显示效果的影响，提高了阵列基板的实用性。
进一步的，多个绑定位2依次排成多个相互平行的横排，每个横排上的区空位与其它横排上对应的区空位在同一竖列上。本实施例中，由于每个横排上的区空位与其它横排上对应的区空位在同一竖列上，进而可以减小区空位对显示面板显示效果的影响。
另一方面，本发明实施例还提供了一种显示面板，包括：上述的阵列基板。
本发明实施例提供了一种显示面板，用于使工作人员能够快速的查找到阵列基板中绑定区域内的预设序号的绑定位，现有技术中，工作人员需要排查阵列基板中绑定区域内预设序号的绑定位时，通常需要从第一个绑定位开始一一查数，查数过程非常的费力，而且还经常容易出现查数错位的问题，进而导致排查效率低的问题，与现有技术相比，本申请文件提供的显示面板包括阵列基板，该阵列基板包括：基板本体，基板本体的一侧具有绑定区域，绑定区域内具有多个依次排序设置的绑定位，多个排序设置的绑定位中的预设排序位置处设有区空位，区空位用于将绑定区域分隔成多个绑定子区域，使每个绑定子区域内具有预设数量的绑定位，当工作人员需要排查预设序号的绑定位时，可以首先判断预设序号的绑定位所在的绑定子区域，然后再在绑定子区域内进行查数，这样就减少的查数的数量，进而可以减少工作人员查找阵列基板中绑定区域内的预设序号的绑定位的时间，提高了查找效率。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (9)

1.一种阵列基板，其特征在于，包括：
基板本体，所述基板本体的一侧具有绑定区域，所述绑定区域内具有多个依次排序设置的绑定位，多个排序设置的所述绑定位中的预设排序位置处设有区空位，所述区空位用于将所述绑定区域分隔成多个绑定子区域，使每个所述绑定子区域内具有预设数量的所述绑定位。
2.根据权利要求1所述的阵列基板，其特征在于，
所述区空位为多个，多个所述区空位分别设置于多个所述绑定位中的多个预设排序位置处。
3.根据权利要求2所述的阵列基板，其特征在于，
每个所述绑定子区域内的所述绑定位的数量相同。
4.根据权利要求3所述的阵列基板，其特征在于，
每个所述区空位上均设有标号。
5.根据权利要求4所述的阵列基板，其特征在于，
所述标号记录所述区空位对应的所述绑定子区域内所述绑定位的数量。
6.根据权利要求4所述的阵列基板，其特征在于，
所述标号记录所述区空位所对应的所述绑定位的排序序号。
7.根据权利要求2所述的阵列基板，其特征在于，
每个所述绑定子区域内的绑定位数量为40-50个。
8.根据权利要求2所述的阵列基板，其特征在于，
多个所述绑定位依次排成多个相互平行的横排，每个所述横排上的所述区空位与其它所述横排上对应的所述区空位在同一竖列上。
9.一种显示面板，其特征在于，包括：
如权利要求1至8中任一项所述的阵列基板。
CN201711131501.3A 2017-11-15 2017-11-15 阵列基板和显示面板 Active CN107807479B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201711131501.3A CN107807479B (zh) 2017-11-15 2017-11-15 阵列基板和显示面板
US16/150,497 US10707241B2 (en) 2017-11-15 2018-10-03 Array substrate and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201711131501.3A CN107807479B (zh) 2017-11-15 2017-11-15 阵列基板和显示面板

Publications (2)

Publication Number Publication Date
CN107807479A true CN107807479A (zh) 2018-03-16
CN107807479B CN107807479B (zh) 2021-01-22

Family

ID=61580244

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711131501.3A Active CN107807479B (zh) 2017-11-15 2017-11-15 阵列基板和显示面板

Country Status (2)

Country Link
US (1) US10707241B2 (zh)
CN (1) CN107807479B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN209882200U (zh) * 2018-11-09 2019-12-31 重庆先进光电显示技术研究院 印刷电路板及其显示器连接结构

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070048376A (ko) * 2005-11-04 2007-05-09 엘지.필립스 엘시디 주식회사 액정표시장치
CN1967836A (zh) * 2005-11-18 2007-05-23 鸿富锦精密工业（深圳）有限公司 一种芯片
CN101000413A (zh) * 2006-01-13 2007-07-18 三星电子株式会社 液晶显示器及其形成方法和薄膜晶体管基板
CN101521984A (zh) * 2008-02-29 2009-09-02 中兴通讯股份有限公司 降低金手指配合推力的方法和印刷电路板
KR20110005573A (ko) * 2009-07-10 2011-01-18 엘지디스플레이 주식회사 액정 표시장치
CN203151861U (zh) * 2013-01-07 2013-08-21 天之域电子工业(厦门)有限公司 一种柔性电路板结构
CN204335152U (zh) * 2014-11-27 2015-05-13 武汉天马微电子有限公司 一种柔性印刷电路板及显示装置
CN104661430A (zh) * 2015-03-17 2015-05-27 京东方科技集团股份有限公司 一种对位标识、电路板和显示装置
US20160086911A1 (en) * 2007-11-09 2016-03-24 Renesas Electronics Corporation Semiconductor device and a method of manufacturing the same
US9575386B2 (en) * 2013-01-25 2017-02-21 Samsung Display Co., Ltd. Thin film transistor substrate, method of manufacturing the same and display device having the same
CN206353887U (zh) * 2016-12-16 2017-07-25 昆山意力电路世界有限公司 一种柔性高密度隔段式高对准金手指线路板
CN107015407A (zh) * 2015-12-03 2017-08-04 三星显示有限公司 具有虚设端子的显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI300543B (en) * 2004-06-01 2008-09-01 Au Optronics Corp Liquid crystal display panel having a cell test structure and method for making the same
TWI302290B (en) * 2005-08-17 2008-10-21 Au Optronics Corp Structure for circuit assembly
TWI442360B (zh) * 2010-10-28 2014-06-21 Au Optronics Corp 顯示器及其接合阻抗的檢測系統以及檢測方法
US9750140B2 (en) * 2014-03-14 2017-08-29 Innolux Corporation Display device
US9570365B2 (en) * 2014-03-14 2017-02-14 Innolux Corporation Display device and test pad thereof

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070048376A (ko) * 2005-11-04 2007-05-09 엘지.필립스 엘시디 주식회사 액정표시장치
CN1967836A (zh) * 2005-11-18 2007-05-23 鸿富锦精密工业（深圳）有限公司 一种芯片
CN101000413A (zh) * 2006-01-13 2007-07-18 三星电子株式会社 液晶显示器及其形成方法和薄膜晶体管基板
US20160086911A1 (en) * 2007-11-09 2016-03-24 Renesas Electronics Corporation Semiconductor device and a method of manufacturing the same
CN101521984A (zh) * 2008-02-29 2009-09-02 中兴通讯股份有限公司 降低金手指配合推力的方法和印刷电路板
KR20110005573A (ko) * 2009-07-10 2011-01-18 엘지디스플레이 주식회사 액정 표시장치
CN203151861U (zh) * 2013-01-07 2013-08-21 天之域电子工业(厦门)有限公司 一种柔性电路板结构
US9575386B2 (en) * 2013-01-25 2017-02-21 Samsung Display Co., Ltd. Thin film transistor substrate, method of manufacturing the same and display device having the same
CN204335152U (zh) * 2014-11-27 2015-05-13 武汉天马微电子有限公司 一种柔性印刷电路板及显示装置
CN104661430A (zh) * 2015-03-17 2015-05-27 京东方科技集团股份有限公司 一种对位标识、电路板和显示装置
CN107015407A (zh) * 2015-12-03 2017-08-04 三星显示有限公司 具有虚设端子的显示装置
CN206353887U (zh) * 2016-12-16 2017-07-25 昆山意力电路世界有限公司 一种柔性高密度隔段式高对准金手指线路板

Also Published As

Publication number Publication date
US10707241B2 (en) 2020-07-07
CN107807479B (zh) 2021-01-22
US20190148408A1 (en) 2019-05-16

Similar Documents

Publication Publication Date Title
US10229650B2 (en) Array substrate and display device
JP4260250B2 (ja) 静電気保護回路を有する液晶表示装置及びこの回路を利用した表示検査方法
CN104330935B (zh) 一种阵列基板、显示面板和显示装置
CN104376821B (zh) 液晶显示驱动器ic
CN100543523C (zh) 液晶显示器及其驱动方法
CN105023548B (zh) 半导体装置和显示装置
CN205264701U (zh) 一种阵列基板、显示面板和显示装置
CN105159513B (zh) 阵列基板、自容式触控显示面板及电子装置
DE102014220430A1 (de) Datenverarbeitungsvorrichtung
CN108389516A (zh) 异形显示屏及显示装置
CN108109592A (zh) 显示装置及其工作方法
CN100364043C (zh) 半导体装置、其电检查方法、以及具备它的电子设备
EP1280130A3 (en) Display device and electronic instrument
CN105427798A (zh) 一种像素电路、显示面板及显示装置
TWM611578U (zh) 用於驅動包括指紋感測像素、顯示像素和觸控感測器的面板的單晶片元件、電子模組以及包括該單晶片元件的電子裝置
DE102014114128A1 (de) Elektromagnetisches induktives touchpanel, elektromagnetisches induktives touchdisplay-panel und elektromagnetisches induktives touchdisplay-gerät
CN105405385A (zh) Goa电路、goa电路扫描方法、显示面板和显示装置
CN108073911A (zh) 感光装置、感光模组、显示模组及电子设备
CN102037401A (zh) 液晶温度传感器、液晶温度传感器的温度检测方法、液晶装置以及液晶装置的驱动方法
CN105575354A (zh) 用于显示面板的驱动电路
CN104078014B (zh) 用于显示装置的源驱动器
CN108399869A (zh) 电光面板、电光装置和电子设备
CN105931591A (zh) 一种显示面板的调试方法
CN107807479A (zh) 阵列基板和显示面板
CN109192169A (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20230117

Address after: Room 518, No. 29, Taizhong Road, Wangtai Street Office, Huangdao District, Qingdao, Shandong 266425

Patentee after: Qingdao BOE Optoelectronic Technology Co.,Ltd.

Patentee after: BOE TECHNOLOGY GROUP Co.,Ltd.

Address before: 065500 north side of No.3 Road, west side of No.6 Road, development zone, Gu'an County, Langfang City, Hebei Province

Patentee before: BOE (HEBEI) MOBILE DISPLAY TECHNOLOGY Co.,Ltd.

Patentee before: BOE TECHNOLOGY GROUP Co.,Ltd.

TR01 Transfer of patent right