CN107799461A - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
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- CN107799461A CN107799461A CN201610802982.5A CN201610802982A CN107799461A CN 107799461 A CN107799461 A CN 107799461A CN 201610802982 A CN201610802982 A CN 201610802982A CN 107799461 A CN107799461 A CN 107799461A
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- interlayer dielectric
- dielectric layer
- layer
- polish stop
- stop layer
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- 238000000034 method Methods 0.000 title claims abstract description 66
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
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- 239000011229 interlayer Substances 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 40
- 238000000227 grinding Methods 0.000 claims description 17
- 239000007788 liquid Substances 0.000 claims description 10
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
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- 238000005229 chemical vapour deposition Methods 0.000 description 11
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 150000002739 metals Chemical group 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
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- 229910004541 SiN Inorganic materials 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- 238000001514 detection method Methods 0.000 description 1
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- 125000001301 ethoxy group Chemical group [H]C([H])([H])C([H])([H])O* 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000009415 formwork Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical group O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Abstract
The present invention provides a kind of manufacture method of semiconductor devices, and methods described includes:Semiconductor substrate is provided, on the semiconductor substrate formed with some dummy grids；Polish stop layer and interlayer dielectric layer are sequentially depositing, to cover the Semiconductor substrate and some dummy grids, wherein the top surface of the interlayer dielectric layer is higher than the top surface of the dummy grid；First cmp is carried out to the interlayer dielectric layer, stopped in the polish stop layer；Second cmp is carried out to the interlayer dielectric layer and polish stop layer, until the polish stop layer reaches target thickness；The polish stop layer is etched, stopped on the top surface of the dummy grid；Etching removes the dummy grid, to form gate trench；Deposited metal layer is to form metal gates in the gate trench.According to the present invention it is possible to the saucerization formed during effectively reducing CMP in interlayer dielectric layer top surface, so as to reduce the metal residue in the saucerization, improves the yield and performance of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture method of semiconductor devices.
Background technology
With the continuous development of semiconductor technology, the size of semiconductor devices constantly reduces.Below 32nm high-k/metal gate
Pole is increasingly becoming the main flow direction of current semiconductor technology development.Cmp (the chemical- of metal gates
Mechanical planarization, abbreviation CMP) processing procedure is to form one of most important processing procedure of metal gates, chemical machine
Tool grinding technique grinds two kinds of effects with mechanical polishing and chemical formula, and whole wafer surface can be made to reach planarization,
So as to accurately control metal gates step (step).
CMP technique is widely used in the making of metal gate electrode in the high-k/metal gate in 28nm technology nodes.For
In substituting metal grid processing procedure, generally require to be applied to dummy grid polysilicon opening chemical mechanical planarization process and metal gates chemistry
Mechanical grinding process makes high-k/metal gate device and products.
For rear metal gate process, during CMP, because the removal speed ratio of interlayer dielectric layer is higher, its top surface
The saucerization of formation is larger, causes during metal gates are formed, part metals residue in the dish-like depression, by
It can cause short circuit in these metal residues or reduce the reliability of chip, reduce the performance and yield of product..
Therefore, it is necessary to a kind of manufacture method of new semiconductor devices is proposed, to solve above-mentioned technical problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, and methods described includes：
Semiconductor substrate is provided, on the semiconductor substrate formed with some dummy grids；
Polish stop layer and interlayer dielectric layer are sequentially depositing, to cover the Semiconductor substrate and some pseudo- grid
Pole, wherein the top surface of the interlayer dielectric layer is higher than the top surface of the dummy grid；
First cmp is carried out to the interlayer dielectric layer, stopped in the polish stop layer；
Second cmp is carried out to the interlayer dielectric layer and polish stop layer, until the polish stop layer reaches
To target thickness；
The polish stop layer is etched, stopped on the top surface of the dummy grid；
Etching removes the dummy grid, to form gate trench；
Deposited metal layer is to form metal gates in the gate trench.
Further, using with grinding of the interlayer dielectric layer material to the high selectivity of the polish stop layer material
Liquid performs first cmp.
Further, using with same or like selection of the interlayer dielectric layer material to the polish stop layer material
The lapping liquid of ratio performs second cmp.
Further, the target thickness of the polish stop layer is 50 angstroms~150 angstroms.
Further, in the polish stop layer etching process, the thickness of interlayer dielectric layer loss is less than 50 angstroms.
Further, the material of the dummy grid includes polysilicon.
Further, the polish stop layer includes SiN.
Further, the interlayer dielectric layer includes high-aspect-ratio (HARP) oxide and tetraethyl orthosilicate sequentially formed
(TEOS) oxide.
Further, the bottom being additionally included in before metal gates are formed in the gate trench and side wall form work function
The step of metal level.
In summary, using the manufacture method of the present invention, can effectively reduce during CMP in interlayer dielectric layer top surface shape
Into saucerization, so as to reduce the metal residue in the saucerization, improve the yield and performance of device.
Brief description of the drawings
The embodiment of the present invention is described in more detail in conjunction with the accompanying drawings, above-mentioned and other purpose of the invention,
Feature and advantage will be apparent.Accompanying drawing is used for providing further understanding the embodiment of the present invention, and forms explanation
A part for book, it is used to explain the present invention together with the embodiment of the present invention, is not construed as limiting the invention.In the accompanying drawings,
Identical reference number typically represents same parts or step.
In accompanying drawing：
Figure 1A-Fig. 1 G are the devices that the step of according to an exemplary embodiment of the present one method is implemented successively obtains respectively
The schematic cross sectional view of part；
Fig. 2 is a kind of schematic flow of the manufacture method of one semiconductor devices according to an exemplary embodiment of the present
Figure.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although it can make
Various elements, part, area, floor and/or part are described with term first, second, third, etc., these elements, part, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, part, area, floor or part with it is another
One element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include making
With the different orientation with the device in operation.For example, if the device upset in accompanying drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions
Outside, the present invention can also have other embodiment.
In the conventional CMP processing procedures of metal gates, because the removal speed ratio of interlayer dielectric layer is higher, what its top surface was formed
Saucerization is larger, causes during metal gates are formed, and part metals are residued in the dish-like depression, due to these gold
Category residue can cause short circuit or reduce the reliability of chip, so as to reduce the performance of product and yield.
In view of the shortcomings of the prior art, the invention provides a kind of manufacture method of semiconductor devices, methods described to include：
Semiconductor substrate is provided, on the semiconductor substrate formed with some dummy grids；
Polish stop layer and interlayer dielectric layer are sequentially depositing, to cover the Semiconductor substrate and some pseudo- grid
Pole, wherein the top surface of the interlayer dielectric layer is higher than the top surface of the dummy grid；
First cmp is carried out to the interlayer dielectric layer, stopped in the polish stop layer；
Second cmp is carried out to the interlayer dielectric layer and polish stop layer, until the polish stop layer reaches
To target thickness；
The polish stop layer is etched, stopped on the top surface of the dummy grid；
Etching removes the dummy grid, to form gate trench；
Deposited metal layer is to form metal gates in the gate trench.
The material of wherein described dummy grid is polysilicon, and the polish stop layer is the SiN of deposition, the interlayer dielectric layer
Including the HARP oxides being sequentially depositing and TEOS oxide.The grinding is stopped using with the interlayer dielectric layer material
The lapping liquid of the high selectivity of layer material performs first cmp；Using with the interlayer dielectric layer material pair
The lapping liquid of the same or like selection ratio of the polish stop layer material performs second cmp.The grinding
The target thickness of stop-layer is 50 angstroms~150 angstroms, to the thickness that in the polish stop layer etching process, interlayer dielectric layer loses
Less than 50 angstroms.
According to the present invention, using the method control interlayer dielectric layer of etching and grinding after the second cmp step
The removal thickness of stop-layer, the saucerization of interlayer dielectric layer is reduced, it is residual so as to reduce the metal in the saucerization
Thing is stayed, improves the performance and yield of product.
[embodiment one]
Reference picture 1A- Fig. 1 G, the step of according to an exemplary embodiment of the present one method of illustrated therein is is implemented successively
The schematic cross sectional view of the device obtained respectively.
As shown in Figure 1A, there is provided Semiconductor substrate 100, on the semiconductor substrate formed with some dummy grids 101.
Wherein, the constituent material of Semiconductor substrate 100 can use undoped with monocrystalline silicon, the monocrystalline doped with impurity
Silicon, silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI) is laminated on insulator, on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc..In the present embodiment, the material selection monocrystalline of Semiconductor substrate 100
Silicon.
Formed with isolation structure (not shown) in Semiconductor substrate 100, isolation structure can be that shallow trench isolates (STI)
Structure or selective oxidation silicon (LOCOS) isolation structure, in the present embodiment, isolation structure is preferably shallow trench isolation junction
Structure.Exemplarily, isolation structure can divide Semiconductor substrate 100 for nmos area and PMOS areas.Shape is gone back in Semiconductor substrate 100
Into there is various traps (well) structure, to put it more simply, being omitted in diagram.
The material of dummy grid 101 includes polysilicon or amorphous carbon.In the present embodiment, the dummy grid material layer is more
Crystal silicon layer, any deposition process well known to those skilled in the art can be used to form polysilicon layer, such as chemical vapour deposition technique
(CVD), such as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition
(LTCVD), plasma activated chemical vapour deposition (PECVD), it is possible to use general such as sputter and physical vapour deposition (PVD) (PVD)
Similarity method.Exemplary, forming the method for dummy grid 101 is：Deposition forms high k dielectric layer (not on a semiconductor substrate successively
Show) and dummy grid material layer, the photoresist layer of patterning, the photoresist layer definition are formed in the dummy grid material layer
The shape of the dummy grid 101 and the size of critical size, using the photoresist layer as hard mask etch dummy grid material
Layer and high k dielectric layer, form dummy gate structure.Then the photoresist layer is removed.The forming method of above-mentioned dummy grid 101 is only
It is that exemplarily, other any methods for forming dummy grid 101 may be applicable to the present invention.
The k values (dielectric constant) of high k dielectric layer are usually more than 3.9, its constituent material include hafnium oxide, hafnium silicon oxide,
Nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium,
Aluminum oxide etc., preferably hafnium oxide, zirconium oxide or aluminum oxide.The technique that CVD, ALD or PVD etc. can be used suitable is formed
High k dielectric layer.The thickness range of high k dielectric layer is 10 angstroms to 30 angstroms.
Formed with clearance wall in the side wall of each dummy grid in some dummy grids.The material example of the clearance wall
The insulating materials such as silicon nitride in this way, silica or silicon oxynitride.In the present embodiment, clearance wall is oxide and nitride
Lamination.The technique for forming clearance wall can be any technique well known to those skilled in the art, such as chemical vapor deposition.
Gap wall inevitably can also form clearance wall during depositing in the top of dummy gate structure, but it can be in processing procedure afterwards
It is middle to be removed by cmp or etching.
Then, with continued reference to polish stop layer 102 and interlayer dielectric layer 103 shown in Figure 1A, is sequentially depositing, with described in covering
Semiconductor substrate 100 and some dummy grids 101, wherein the top surface of the interlayer dielectric layer 103 is higher than the dummy grid
101 top surface.
Polish stop layer 102 can be formed with materials such as SiCN, SiN, SiC, SiOF, SiON.In the present embodiment, grinding stops
Only the material of layer 102 is silicon nitride.Any suitable deposition process such as CVD or PVD can be used to be formed.
Form the various suitable techniques that interlayer dielectric layer 103 can use those skilled in the art to be familiar with.Interlayer is situated between
Electric layer 103 can be silicon oxide layer, using thermal chemical vapor deposition (thermal CVD) manufacturing process or high density etc. from
The material layer for having doped or undoped silica that daughter (HDP) manufacturing process is formed, such as undoped silica glass
(USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer can also be doping boron or doping phosphorus
Spin cloth of coating-type glass (spin-on-glass, SOG), the tetraethoxysilane (PTEOS) for adulterating phosphorus or four ethoxies for adulterating boron
Base silane (BTEOS).In the present embodiment, the interlayer dielectric layer 103 includes high-aspect-ratio (HARP) oxidation being sequentially depositing
Thing and tetraethyl orthosilicate (TEOS) oxide.
Then, with reference to shown in figure 1B, the first cmp is carried out to the interlayer dielectric layer 103, stopped at described
In polish stop layer 102.Exemplarily, the first cmp is carried out, removes most of interlayer dielectric layer 103, this process
Grinding rate is a kind of rough lapping mode than very fast.Using with the material of interlayer dielectric layer 103 to the polish stop layer
The lapping liquid of the high selectivity of 102 materials performs first cmp, for example, selection is than being more than or equal to 50:1.
Under lapping liquid effect, the grinding rate to polish stop layer 102 is much larger than to the grinding rate of interlayer dielectric layer 103.
In general CMP tool is equipped with end point determination device (EPD), to be detected as needed to the terminal of grinding.
When material is ground to default target thickness or target material (target location), end point determination device sends stopping
The signal of grinding.In an example, using optical end point detection or current of electric end point determination to first chemical machinery
The grinding endpoint of grinding is detected.
Then, with reference to figure 1C, the second cmp is carried out to the interlayer dielectric layer 103 and polish stop layer 102,
Until the polish stop layer 102 reaches target thickness, in the present embodiment, the target thickness is 50A~150A.
Second cmp is fine lapping, and the polishing velocity of the second cmp is ground less than the first chemical machinery
The polishing velocity of mill.In the step, the second cmp stop at polish stop layer 102 reach target thickness 50A~
During 150A.In the present embodiment, using same or like to the material of polish stop layer 102 with the material of interlayer dielectric layer 103
The lapping liquid of ratio is selected to perform the second cmp, while the lapping liquid can also have the low selection to dummy grid material
Than.
Then, with reference to figure 1D, the polish stop layer 102 is etched, is stopped on the top surface of the dummy grid 101.The step
In rapid, the polish stop layer that thickness above dummy grid is 50A~150A, in the process, interlayer are removed by etching selectivity
The removal thickness of dielectric layer 103 is less than 50A.Exemplarily, dry etching can be used to perform etch process, dry method etch technology
Including but not limited to：Reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.In the present embodiment
In, using plasma etch process, the etching gas used is based on oxygen (O2- based) gas, the stream of etching gas
It can be 50 cc/mins (sccm)~150 cc/min (sccm) to measure scope, and reaction room pressure can be 5 millitorrs
(mTorr)~20 millitorr (mTorr).Wherein, the etching gas of dry etching can also be bromination hydrogen, carbon tetrafluoride gas
Or gas of nitrogen trifluoride.
Then, deposition forms hard mask layer.The material of hard mask layer can be arbitrarily suitable hard mask material, this implementation
In example, the material of the hard mask layer is TiN.It can be formed using any deposition process well known to those skilled in the art, such as
The methods of chemical vapor deposition, physical vapour deposition (PVD).Then, the corresponding PMOS parts hard mask layer is removed, with described in exposure
Dummy grid 101.In the present embodiment, photoresist layer is formed on hard mask layer, the photoresist is patterned using photoetching process
Layer,, will be exposed hard afterwards using the method for dry etching or wet etching with the corresponding PMOS parts hard mask layer of exposure
Mask layer removes, with the exposure dummy grid 101.The above method is only that exemplarily, other suitable methods are equally applicable to
The present invention.Remaining hard mask layer there is protection to make the polish stop layer 102 and interlayer dielectric layer 103 of NMOS area below
With.Merely just as an example, being not intended to limit the invention, the step of above-mentioned deposition forms hard mask is not must
The step of must performing, above-mentioned remaining hard mask can also cover to PMOS area, to remove NMOS in subsequent technique
The dummy grid in region.
Then, as referring to figure 1E, etching removes dummy grid 101 described in PMOS area, to form gate trench 104.
In the present embodiment, by implementing dry etching, the dummy grid 101 is removed.The technique ginseng of the dry etching
Number includes：Etching gas HBr flow is 20-500sccm, pressure 2-40mTorr, power 100-2000W, wherein
MTorr represents milli millimetres of mercury, and sccm represents cc/min.After the dry etching is implemented, using wet etching
Technique removes etch residues and impurity caused by the dry etching.The above method is only exemplarily other suitable sides
Method, such as wet etching etc. are equally applicable to the present invention.
In the gate trench 104 before deposited metal layer, in addition to successively on the bottom and side wall of gate trench
Deposition forms the step of the first workfunction layers.Further, covering is also included before the first workfunction layers are formed
The step of layer.
For PMOS device, its first workfunction layers is p-type workfunction layers, p-type workfunction layers (PWF)
Material can select to be but be not limited to TixN1-x, TaC, MoN, TaN or other suitable film layers.Can use CVD,
Technique suitable ALD or PVD etc. forms p-type workfunction layers.The thickness range of p-type workfunction layers be 10 angstroms extremely
580 angstroms.
For nmos device, its first workfunction layers is N-type workfunction layers (NWF), N-type workfunction layers
Material can select to be but be not limited to TaC, Ti, Al, TixAl1-x or other suitable film layers.Can use CVD,
Technique suitable ALD or PVD etc. forms N-type workfunction layers.The thickness range of N-type workfunction layers is 10 angstroms to 80
Angstrom.
Then, as shown in fig. 1F, deposited metal layer in the gate trench 104 and on the interlayer dielectric layer 103
105, the metal level top surface is higher than the top surface of the interlayer dielectric layer.The material of the metal level can select to be but be not limited to
Al, W or other suitable film layers.The suitable technique such as CVD, ALD or PVD can be used to form the first metal layer.
In the present embodiment, using metal level described in PVD deposition, the material of the metal level is Al.
Then, as shown in Figure 1 G, the 3rd cmp is performed to the metal level, stops at the interlayer dielectric layer
On 103 surface, to form metal gates 105.
Reference picture 2, it is a kind of indicative flowchart of the manufacture method of semiconductor devices of one embodiment of the present of invention,
For schematically illustrating the flow of whole manufacturing process.
In step s 201, there is provided Semiconductor substrate, on the semiconductor substrate formed with some dummy grids；
In step S202, be sequentially depositing polish stop layer and interlayer dielectric layer, with cover the Semiconductor substrate and
Some dummy grids, wherein the top surface of the interlayer dielectric layer is higher than the top surface of the dummy grid；
In step S203, the first cmp is carried out to the interlayer dielectric layer, the grinding is stopped at and stops
On layer；
In step S204, the second cmp is carried out to the interlayer dielectric layer and polish stop layer, until institute
State polish stop layer and reach target thickness；
In step S205, the polish stop layer is etched, stopped on the top surface of the dummy grid；
In step S206, etching removes the dummy grid, to form gate trench；
In step S207, deposited metal layer is to form metal gates in the gate trench.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (9)
1. a kind of manufacture method of semiconductor devices, it is characterised in that methods described includes：
Semiconductor substrate is provided, on the semiconductor substrate formed with some dummy grids；
Polish stop layer and interlayer dielectric layer are sequentially depositing, to cover the Semiconductor substrate and some dummy grids, its
Described in interlayer dielectric layer top surface be higher than the dummy grid top surface；
First cmp is carried out to the interlayer dielectric layer, stopped in the polish stop layer；
Second cmp is carried out to the interlayer dielectric layer and polish stop layer, until the polish stop layer reaches mesh
Mark thickness；
The polish stop layer is etched, stopped on the top surface of the dummy grid；
Etching removes the dummy grid, to form gate trench；
Deposited metal layer is to form metal gates in the gate trench.
2. the method as described in claim 1, it is characterised in that stopped using having the interlayer dielectric layer material to the grinding
Only the lapping liquid of the high selectivity of layer material performs first cmp.
3. the method as described in claim 1, it is characterised in that stopped using having the interlayer dielectric layer material to the grinding
Only the lapping liquid of the same or like selection ratio of layer material performs second cmp.
4. the method as described in claim 1, it is characterised in that the target thickness of the polish stop layer is 50 angstroms~150 angstroms.
5. the method as described in claim 1, it is characterised in that in the polish stop layer etching process, interlayer dielectric layer
The thickness of loss is less than 50 angstroms.
6. the method as described in claim 1, it is characterised in that the material of the dummy grid includes polysilicon.
7. the method as described in claim 1, it is characterised in that the polish stop layer includes SiN.
8. the method as described in claim 1, it is characterised in that the interlayer dielectric layer includes the HARP oxides sequentially formed
And TEOS oxide.
9. the method as described in claim 1, it is characterised in that be additionally included in the gate trench before metal gates are formed
In bottom and side wall on formed workfunction layers the step of.
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| CN111816562A (en) * | 2019-04-10 | 2020-10-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111863712A (en) * | 2019-04-24 | 2020-10-30 | 台湾积体电路制造股份有限公司 | Semiconductor structure and method of forming a semiconductor structure |
| WO2020259220A1 (en) * | 2019-06-25 | 2020-12-30 | 浙江驰拓科技有限公司 | Method of preparing mram bottom electrode |
| CN113823690A (en) * | 2020-06-19 | 2021-12-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN117855254A (en) * | 2024-03-08 | 2024-04-09 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
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