CN107785399B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN107785399B CN107785399B CN201711014282.0A CN201711014282A CN107785399B CN 107785399 B CN107785399 B CN 107785399B CN 201711014282 A CN201711014282 A CN 201711014282A CN 107785399 B CN107785399 B CN 107785399B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract
The application discloses display panel and display device, in the equal area in the direction that occupies perpendicular to array substrate, increased compensation capacity of compensation electric capacity, guarantee that the time that the signal of drive circuit output reachs every row pixel is the same, and/or, guarantee that the time that the signal of drive circuit output reachs every row pixel is the same to signal transmission's homogeneity has been improved. The application provides a display panel, including the array substrate, the array substrate includes a plurality of pixels that the array was arranged and for a plurality of pixels provide the first signal line of signal, second signal line of signal, its characterized in that includes: the number of pixels corresponding to the first signal line is smaller than that of pixels corresponding to the second signal line; a compensation capacitor is arranged on the first signal line and at least comprises three polar plates, and orthographic projections of one polar plate and the other two polar plates on the array substrate are overlapped.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
The array substrate of the display panel is provided with criss-cross scanning signal lines and data lines, the scanning signal lines and the data lines enclose pixel units, and each pixel unit is internally provided with a Thin Film Transistor (TFT) and a pixel electrode. Fig. 1 is a schematic structural diagram of an array substrate in the prior art. In the display process of the display panel, the scanning signal lines 101 scan line by line, and one scanning signal line 101 controls the thin film transistor of the line through a Gate On Array (GOA) 104 of the line, thereby controlling one line of pixel electrodes. When a scanning signal line 101 is scanned, the thin film transistor 102 controlled by the scanning signal line 101 is turned on, so that the data driving circuit 105 drives the data line 103 to transmit a corresponding data voltage on the data line 103 to a pixel electrode corresponding to the thin film transistor 102, charges the pixel electrode, and after the scanning is finished, the thin film transistor 102 is turned off.
In the process of designing the display panel, due to the existence of the special-shaped area (for example, the groove for arranging the camera, the headphone, and other devices on the mobile phone panel), as shown in fig. 2, when the scanning signal lines 101 are distributed to the special-shaped area by the GOA 104 or the data lines 103 are distributed to the special-shaped area by the data driving circuit 105, the number of the corresponding pixels on each row of the scanning signal lines 101 or each column of the data lines 103 is different, which may cause the capacitance on the TFT 102 corresponding to the pixels on each row of the scanning signal lines 101 or each column of the data lines 103 to be different, so that the delay of signal transmission on each signal line is different, which may cause the transmission signal to be non-uniform, and further affect the uniformity of the picture display; in the prior art, the capacitance difference between different signal lines can be reduced by arranging a plurality of compensation capacitors 106 of double-layer plates on the signal line with a small number of corresponding pixels, but a large wiring space is required.
Disclosure of Invention
The embodiment of the application provides a display panel and a display device, which are used for increasing the compensation capacity of a compensation capacitor in the same area in the direction perpendicular to an array substrate, ensuring that the time for a signal output by a driving circuit to reach each row of pixels is the same, and/or ensuring that the time for a signal output by the driving circuit to reach each column of pixels is the same, thereby improving the uniformity of signal transmission.
The embodiment of the application provides a display panel, including the array substrate, the array substrate includes a plurality of pixels that the array was arranged and for a plurality of pixels provide the first signal line of signal, second signal line of signal, include: the number of pixels corresponding to the first signal line is smaller than that of pixels corresponding to the second signal line; the first signal line is provided with a compensation capacitor, the compensation capacitor at least comprises three polar plates, and orthographic projections of one polar plate and the other two polar plates in the direction perpendicular to the array substrate are overlapped.
According to the display panel provided by the embodiment of the application, the compensation capacitor at least comprising three polar plates is arranged on the signal line with the smaller number of the corresponding pixels in the plurality of signal lines, the compensation capacity of the compensation capacitor is increased in the same area in the direction perpendicular to the array substrate, the same time for the signals output by the driving circuit to reach each row of pixels is ensured, and/or the same time for the signals output by the driving circuit to reach each column of pixels is ensured, so that the uniformity of signal transmission is improved.
Optionally, in the display panel provided in this embodiment of the present application, the display panel is an organic electroluminescence panel;
the array substrate comprises a plurality of thin film transistors and a plurality of storage capacitors; wherein the content of the first and second substances,
the thin film transistor includes: a grid metal layer and a source drain metal layer;
the storage capacitor comprises a first metal polar plate and a second metal polar plate, wherein the first metal polar plate and the grid metal layer are arranged on the same layer, and the second metal polar plate and the grid metal layer and the source drain metal layer are arranged on different layers.
Optionally, in the display panel provided in the embodiment of the present application, the compensation capacitor includes a first electrode plate, a second electrode plate, and a third electrode plate; the first polar plate and the third polar plate are positioned on two sides of the second polar plate, the orthographic projection of the second polar plate is overlapped with the orthographic projection of the first polar plate and the orthographic projection of the third polar plate in the direction vertical to the array substrate, and the first polar plate is electrically connected with the third polar plate; wherein the content of the first and second substances,
the first polar plate and the grid metal layer are arranged on the same layer;
the second polar plate and the second metal polar plate are arranged on the same layer;
the third polar plate and the source drain metal layer are arranged on the same layer.
According to the display panel provided by the embodiment of the application, the capacitors comprising the three pole plates are formed by utilizing the metal pole plates which are respectively arranged on the same layer with the grid metal layer, the second metal pole plate and the source drain metal layer in the organic electroluminescence panel, and the compensation capacity of the compensation capacitors is increased by two times in the same area in the direction perpendicular to the array substrate.
Optionally, in the display panel provided in the embodiment of the present application, the thin film transistor further includes: an active layer;
the compensation capacitor further comprises a fourth polar plate; the second polar plate and the fourth polar plate are positioned on two sides of the first polar plate, the orthographic projection of the first polar plate is overlapped with the orthographic projection of the second polar plate and the orthographic projection of the fourth polar plate in the direction vertical to the array substrate, and the second polar plate is electrically connected with the fourth polar plate; wherein the content of the first and second substances,
the fourth polar plate and the active layer are arranged on the same layer.
According to the display panel provided by the embodiment of the application, the organic electroluminescence panel and the grid metal layer, the second metal plate, the source drain metal layer and the metal plate arranged on the same layer as the active layer in the array substrate are utilized to form the capacitor comprising the three plates, and the compensation capacity of the compensation capacitor is increased by three times in the same area in the direction perpendicular to the array substrate.
Optionally, in the display panel provided in the embodiment of the present application, the array substrate further includes: a pixel electrode layer;
the compensation capacitor further comprises a fifth polar plate; the second polar plate and the fifth polar plate are positioned on two sides of the third polar plate, the orthographic projection of the third polar plate is overlapped with the orthographic projection of the second polar plate and the orthographic projection of the fifth polar plate in the direction vertical to the array substrate, and the second polar plate, the fourth polar plate and the fifth polar plate are electrically connected; wherein the content of the first and second substances,
the fifth electrode plate and the pixel electrode layer are arranged on the same layer.
According to the display panel provided by the embodiment of the application, the organic electroluminescence panel and the metal electrode plates arranged on the same layer of the grid metal layer, the second metal electrode plate, the source drain metal layer, the active layer and the pixel electrode layer in the array substrate respectively form the capacitor comprising the three electrode plates, and the compensation capacity of the compensation capacitor is increased by four times in the same area in the direction perpendicular to the array substrate.
Optionally, in the display panel provided in the embodiment of the present application, the display panel is a liquid crystal panel;
the array substrate comprises a plurality of thin film transistors; wherein the content of the first and second substances,
the thin film transistor includes: the active layer, the grid metal layer and the source and drain metal layer.
Optionally, in the display panel provided in the embodiment of the present application, the compensation capacitor includes a sixth polar plate, a seventh polar plate, and an eighth polar plate; the sixth polar plate and the eighth polar plate are positioned on two sides of the seventh polar plate, an orthographic projection of the seventh polar plate is overlapped with an orthographic projection of the sixth polar plate and the eighth polar plate in a direction perpendicular to the array substrate, and the sixth polar plate is electrically connected with the eighth polar plate; wherein the content of the first and second substances,
the sixth polar plate and the active layer are arranged on the same layer;
the seventh polar plate and the grid metal layer are arranged on the same layer;
the eighth polar plate and the source drain metal layer are arranged on the same layer.
According to the display panel provided by the embodiment of the application, the capacitors comprising the three electrode plates are formed by utilizing the metal electrode plates which are respectively arranged in the liquid crystal panel and in the same layer with the active layer, the grid electrode metal layer and the source drain electrode metal layer in the array substrate, and the compensation capacity of the compensation capacitors is increased by two times in the same area in the direction perpendicular to the array substrate.
Optionally, in the display panel provided in the embodiment of the present application, the array substrate further includes: the light shielding metal layer is positioned on one side of the active layer, which is far away from the gate metal layer, and is overlapped with the channel part of the active layer in the direction vertical to the array substrate;
the compensation capacitor further comprises a ninth polar plate; the seventh polar plate and the ninth polar plate are positioned on two sides of the sixth polar plate, the orthographic projection of the sixth polar plate is overlapped with the orthographic projection of the seventh polar plate and the orthographic projection of the ninth polar plate in the direction perpendicular to the array substrate, and the seventh polar plate is electrically connected with the ninth polar plate; wherein the content of the first and second substances,
the ninth polar plate and the shading metal layer are arranged on the same layer.
According to the display panel provided by the embodiment of the application, the capacitors comprising the three electrode plates are formed by utilizing the metal electrode plates which are respectively arranged on the same layer with the active layer, the grid metal layer, the source drain metal layer and the shading layer in the liquid crystal panel, and the compensation capacity of the compensation capacitors is increased by three times in the same area in the direction perpendicular to the array substrate.
Optionally, in the display panel provided in the embodiment of the present application, the array substrate further includes: a pixel electrode layer;
the compensation capacitor further comprises a tenth polar plate; the seventh polar plate and the tenth polar plate are positioned on two sides of the eighth polar plate, the orthographic projection of the eighth polar plate is overlapped with the orthographic projection of the seventh polar plate and the orthographic projection of the tenth polar plate in the direction perpendicular to the array substrate, and the seventh polar plate, the ninth polar plate and the tenth polar plate are electrically connected; wherein the content of the first and second substances,
the tenth polar plate and the pixel electrode layer are arranged on the same layer.
According to the display panel provided by the embodiment of the application, the capacitors comprising the three electrode plates are formed by utilizing the metal electrode plates which are respectively arranged on the same layer with the active layer, the grid metal layer, the source drain metal layer, the shading layer and the pixel electrode layer in the liquid crystal panel, and the compensation capacity of the compensation capacitor is increased by four times in the same area in the direction perpendicular to the array substrate.
Optionally, in the display panel provided in the embodiment of the present application, the array substrate further includes: a common electrode layer;
the compensation capacitor further comprises an eleventh polar plate; the eighth polar plate and the eleventh polar plate are positioned on two sides of the tenth polar plate, the orthographic projection of the tenth polar plate is overlapped with the orthographic projection of the eighth polar plate and the orthographic projection of the eleventh polar plate in the direction perpendicular to the array substrate, and the sixth polar plate, the eighth polar plate and the eleventh polar plate are electrically connected; wherein the content of the first and second substances,
the eleventh polar plate and the common electrode layer are arranged on the same layer.
According to the display panel provided by the embodiment of the application, the capacitors comprising the three electrode plates are formed by utilizing the metal electrode plates which are respectively arranged on the same layer with the active layer, the grid metal layer, the source drain metal layer, the shading layer, the pixel electrode layer and the common electrode layer in the liquid crystal panel, and the compensation capacity of the compensation capacitors is increased by five times in the same area in the direction perpendicular to the array substrate.
Optionally, in the display panel provided in this embodiment of the present application, one plate of the compensation capacitor is connected to one of the first signal lines, and the other plate of the compensation capacitor is connected to a fixed potential line.
According to the display panel provided by the embodiment of the application, one polar plate in the compensation capacitor is connected with one first signal line, and the other polar plate is connected with the fixed potential line, so that the fixed potential of the capacitor is introduced into the compensation capacitor, and the normal work of the compensation capacitor is maintained.
Optionally, in the display panel provided in this embodiment of the present application, one of the at least three plates is a fixed potential line itself.
According to the display panel provided by the embodiment of the application, the capacitor is formed by utilizing the fixed potential lines and other layer structures, the capacitor is prevented from being formed by additionally arranging a metal layer, and the thickness of the display panel is favorably reduced.
Optionally, in the display panel provided in this embodiment of the present application, the compensation capacitor is at least located at one end of the first signal line.
The above-mentioned display panel that this application embodiment provided, through inciting somebody to action compensation capacitance set up in the one end of first signal line avoids addding the one deck metal level and is used for constituting the electric capacity, is favorable to reducing the thickness of display panel.
Optionally, in the display panel provided in the embodiment of the present application, the first signal line is a scanning signal line.
According to the display panel provided by the embodiment of the application, the compensation capacitor at least comprising the three polar plates is arranged on the scanning signal line with the smaller number of the corresponding pixels, so that signals on the scanning signal line can simultaneously reach the corresponding pixels on the same row or the same column, and the uniformity of signal transmission is ensured.
Optionally, in the display panel provided in this embodiment of the present application, the compensation capacitor is located between the gate driving circuit and the pixel region.
According to the display panel provided by the embodiment of the application, the compensation capacitor is arranged between the gate drive circuit and the pixel area, so that signals output by the gate drive circuit can simultaneously reach the same row of corresponding pixels, and/or signals output by the gate drive circuit can simultaneously reach the same column of corresponding pixels, and the uniformity of signal transmission is ensured.
Optionally, in the display panel provided in the embodiment of the present application, the first signal line is a data line.
The above-mentioned display panel that this application embodiment provided sets up the compensation capacitance that includes three polar plate at least on the less data line of the quantity of pixel that corresponds for signal on the data line can reach the same line pixel that corresponds simultaneously, and/or, makes signal on the data line can reach the same row pixel that corresponds simultaneously, has guaranteed signal transmission's homogeneity.
Optionally, in the display panel provided in this embodiment of the present application, the compensation capacitor is located between the data driving circuit and the pixel region.
According to the display panel provided by the embodiment of the application, the compensation capacitor is arranged between the data driving circuit and the pixel area, so that the time for the signals output by the driving circuit to reach each row of pixels is the same, and/or the time for the signals output by the driving circuit to reach each column of pixels is the same, and the uniformity of signal transmission is ensured.
Accordingly, an embodiment of the present application provides a display device including the display panel according to any one of the above descriptions.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate of a display panel in the prior art;
fig. 2 is a schematic diagram illustrating a compensation capacitor disposed in an array substrate of a display panel according to the prior art;
fig. 3 is a schematic diagram illustrating a principle of a compensation capacitor disposed in an array substrate of a display panel according to an embodiment of the present disclosure;
fig. 4 is a simplified structural diagram of a compensation capacitor disposed in an array substrate of a display panel according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a three-layer plate compensation capacitor when a display panel provided by an embodiment of the present application is an organic electroluminescence panel;
fig. 6 is a schematic structural diagram of a four-layer plate compensation capacitor when a display panel provided by an embodiment of the present application is an organic electroluminescent panel;
fig. 7 is a schematic structural diagram of a five-layer plate compensation capacitor when a display panel provided in this embodiment of the present application is an organic electroluminescent panel;
fig. 8 is a schematic structural diagram of a three-layer plate compensation capacitor when a display panel provided in the embodiment of the present application is a liquid crystal panel;
fig. 9 is a schematic structural diagram of a four-layer plate compensation capacitor when a display panel provided in the embodiment of the present application is a liquid crystal panel;
fig. 10 is a schematic structural diagram of a five-layer plate compensation capacitor when the display panel provided in the embodiment of the present application is a liquid crystal panel;
fig. 11 is a schematic structural diagram of a six-layer plate compensation capacitor when a display panel provided in this embodiment of the present application is a liquid crystal panel;
fig. 12 is a schematic view of an implementation area of a display panel according to an embodiment of the present disclosure;
fig. 13 is a second schematic view of an implementation area of a display panel according to an embodiment of the present disclosure;
fig. 14 is a third schematic view of an implementation area of a display panel according to an embodiment of the present disclosure;
fig. 15 is a fourth schematic view of an implementation area of a display panel according to an embodiment of the present disclosure.
Detailed Description
In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be described in further detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The shapes and sizes of the various elements in the drawings are not to be considered as true proportions, but rather are merely intended to illustrate the context of the application.
The embodiment of the present application provides a display panel, which includes an array substrate, as shown in fig. 3, the array substrate includes a plurality of pixels 303 arranged in an array, and a first signal line 301 and a second signal line 302 for providing signals to the plurality of pixels 303, where the number of pixels 303 corresponding to the first signal line 301 is smaller than the number of pixels 303 corresponding to the second signal line 302; a compensation capacitor 304 is disposed on the first signal line, and as shown in fig. 4, the compensation capacitor includes at least three plates (plate 401/402/403), and one of the plates (e.g., plate 402) overlaps with two other plates (e.g., plate 401/403) in an orthogonal projection of the array substrate.
Further, in practical implementation, in the display panel provided in the embodiment of the present application, the first signal line may be, for example, a first scanning signal line 301(a) in a horizontal direction led by a gate driving circuit, the second signal line may be, for example, a second scanning signal line 302(a) in a horizontal direction led by a gate driving circuit, the number of pixels 303 corresponding to the first scanning signal line 301(a) is smaller than the number of pixels 303 corresponding to the second scanning signal line 302(a), the extending directions of the first scanning signal line 301(a) and the second scanning signal line 302(a) are the same, and a compensation capacitor at least including three layers of plates is disposed on the first scanning signal line 301(a) to ensure that the time for a signal output by the gate driving circuit to reach each column of pixels is the same;
or, the first signal line may be, for example, a first longitudinal data line 301(b) led out by a data driving circuit, the second signal line may be, for example, a second longitudinal data line 302(b) led out by the data driving circuit, the number of pixels 303 corresponding to the first data line 301(b) is smaller than the number of pixels 303 corresponding to the second data line 302(b), the extending directions of the first data line 301(b) and the second data line 302(b) are the same, and a compensation capacitor at least comprising three layers of plates is arranged on the first data line 301(b) to ensure that the time for the signal output by the data driving circuit to reach each row of pixels is the same;
alternatively, the compensation capacitors at least comprising three layers of plates are arranged on the transverse first scanning signal line 301(a) and the longitudinal first data line 301(b) to ensure that the time for the signals output by the data driving circuit to reach each row of pixels is the same as the time for the signals output by the gate driving circuit to reach each column of pixels, thereby improving the uniformity of signal transmission.
Of course, the present invention is not limited to these two signal lines, and the specific implementation may be designed as required, and is not limited herein. Further, in the display panel provided in the embodiment of the present application, as shown in fig. 5, when the display panel is an Organic Light-Emitting Diode (OLED);
the array substrate in the OLED comprises a plurality of thin film transistors and a plurality of storage capacitors;
wherein the thin film transistor includes: a substrate 501, a Buffer layer Buffer 502 located on the substrate 501, a gate insulating layer GI 503 located on the Buffer layer 502, a metal insulating layer IMD 504 located on the GI layer 503, an interlayer insulating layer ILD 505 located on the IMD layer 504, a passivation layer PLN 506 located on the ILD layer 505, a pixel electrode layer 507 located on the PLN layer 506, a pixel definition layer PDL 508 located on the pixel electrode layer 507, a common electrode layer 509 located on the PDL layer 508, an active layer 004 located on the Buffer layer 502, a gate metal layer 001 located on the GI layer 503, and a source drain metal layer 003 located on the ILD layer 505; the source-drain metal layer 003 is connected with the active layer 004 through via holes arranged on the ILD layer 505, the IMD layer 504 and the GI layer 503; the common electrode layer 509 is connected with the source-drain metal layer 003 through a via hole provided on the PDL layer 508;
the storage capacitor comprises a first metal electrode plate 111 and a second metal electrode plate 002, wherein the first metal electrode plate 111 and the gate metal layer 001 are arranged on the same layer and can be made of the same material in the same process, and the second metal electrode plate 002 is arranged in a different layer with the gate metal layer 001 and the source drain metal layer 003. The second metal plate 002 is connected to the first metal plate 111 through a via hole provided on the IMD layer 504.
This application utilizes the metal level that is arranged in different layers in the array substrate, forms the multilayer compensation electric capacity that includes three polar plates at least, knows according to electric capacity formula C ═ ε S/4 pi kd, sets up the compensation electric capacity that includes three-layer polar plate at least on the plane of array substrate, can make the just increase of area S between the polar plate to in occupying the equal area in the direction perpendicular to array substrate, increased compensation electric capacity' S compensation ability.
Specifically, in the display panel provided in the embodiment of the present application, which layers of the array substrate of the OLED form the compensation capacitor including at least three electrode plates may be designed according to needs, and is not limited herein.
The following examples are given.
The first embodiment,
As shown in fig. 5, the compensation capacitor includes a first plate 011, a second plate 012, and a third plate 013.
The first electrode plate 011 and the gate metal layer 001 are arranged on the same layer and can be made of the same material in the same process;
the second electrode plate 012 and the second metal electrode plate 002 are disposed on the same layer, and can be manufactured by using the same material in the same process;
the third plate 013 and the source/drain metal layer 003 are disposed on the same layer, and may be made of the same material in the same process.
The first electrode plate 011 and the third electrode plate 013 are located on two sides of the second electrode plate 012, and the first electrode plate 011 and the third electrode plate 013 are electrically connected through the via holes arranged in the IMD layer 504 and the ILD layer 505, and the orthographic projections of the second electrode plate 012 in the direction perpendicular to the array substrate are respectively overlapped with the orthographic projections of the first electrode plate 011 and the third electrode plate 013, so that the area opposite to the compensation capacitor plates is increased under the same area in the direction perpendicular to the array substrate, and the compensation capacity of the compensation capacitor is increased.
Example II,
As shown in fig. 6, the compensation capacitor includes a first plate 011, a second plate 012, a third plate 013 and a fourth plate 014; wherein the content of the first and second substances,
the first electrode plate 011 and the gate metal layer 001 are arranged on the same layer and can be made of the same material in the same process;
the second electrode plate 012 and the second metal electrode plate 002 are disposed on the same layer, and can be manufactured by using the same material in the same process;
the third electrode plate 013 and the source/drain metal layer 003 are arranged on the same layer, and can be made of the same material in the same process;
the fourth electrode plate 014 and the active layer 004 are disposed in the same layer, and can be manufactured by using the same material in the same process.
Wherein the first and third electrode plates 011 and 013 are located on two sides of the second electrode 012, and the first and third electrode plates 011 and 013 are electrically connected through vias disposed in the IMD layer 504 and ILD layer 505; the second and fourth electrode plates 012 and 014 are located on two sides of the first electrode plate 011, and the second and fourth electrode plates 014 and 014 are electrically connected through vias disposed in the GI layer 503 and the IMD layer 504; the orthographic projections of the second electrode plate 012 in the direction perpendicular to the array substrate are respectively overlapped with the orthographic projections of the first electrode plate 011 and the third electrode plate 013; the orthographic projection of the fourth electrode plate 014 is overlapped with the orthographic projection of the first electrode plate 011 in the direction perpendicular to the array substrate, so that the area opposite to the electrode plates of the compensation capacitor is increased under the condition of occupying the same area in the direction perpendicular to the array substrate, and the compensation capacity of the compensation capacitor is increased. The other reference numerals in the drawings denote the same structures as those in fig. 5.
Example III,
As shown in fig. 7, the compensation capacitor includes a first plate 011, a second plate 012, a third plate 013, a fourth plate 014 and a fifth plate 015; wherein the content of the first and second substances,
the first electrode plate 011 and the gate metal layer 001 are arranged on the same layer and can be made of the same material in the same process;
the second electrode plate 012 and the second metal electrode plate 002 are disposed on the same layer, and can be manufactured by using the same material in the same process;
the third electrode plate 013 and the source/drain metal layer 003 are arranged on the same layer, and can be made of the same material in the same process;
the fourth electrode plate 014 and the active layer 004 are arranged in the same layer and can be manufactured by adopting the same material in the same process;
the fifth electrode plate 015 and the pixel electrode layer 507 are disposed on the same layer, and may be made of the same material in the same process.
Wherein the first and third electrode plates 011 and 013 are located on two sides of the second electrode 012, and the first and third electrode plates 011 and 013 are electrically connected through vias disposed in the IMD layer 504 and ILD layer 505; the second and fourth electrode plates 012 and 014 are located on two sides of the first electrode plate 011; the second and fifth electrode plates 012, 015 are located at two sides of the third electrode plate 013, and the second and fourth electrode plates 012, 014, 015 are electrically connected through vias disposed in the GI layer 503, IMD layer 504, ILD layer 505, PLN layer 506, and an orthographic projection of the second electrode plate 012 overlaps with an orthographic projection of the first and third electrode plates 011, 013 in a direction perpendicular to the array substrate; the orthographic projection of the fourth polar plate 014 is overlapped with the orthographic projection of the first polar plate 011 in the direction perpendicular to the array substrate; the orthographic projection of the fifth pole plate 015 is overlapped with the orthographic projection of the third pole plate 013 in the direction perpendicular to the array substrate, so that the right facing area between the pole plates of the compensation capacitor is increased under the condition that the same area is occupied in the direction perpendicular to the array substrate, and the compensation capacity of the compensation capacitor is increased. The other reference numerals in the drawings denote the same structures as those in fig. 5.
Further, in the Display panel provided in the embodiment of the present application, as shown in fig. 8, when the Display panel is a Liquid Crystal Display (LCD);
the array substrate in the LCD comprises a plurality of thin film transistors;
wherein the thin film transistor includes: a substrate 801, a Buffer layer Buffer 802 located on the substrate 801, a gate insulating layer GI 803 located on the Buffer layer 802, an interlayer insulating layer ILD 804 located on the GI layer 803, a passivation layer PLN 805 located on the ILD layer 804, a pixel electrode layer 904 located on the PLN layer 805, a pixel definition layer PDL 806 located on the pixel electrode layer 904, a common electrode layer 905 located on the PDL layer 806, a light-shielding metal layer 903 located on the substrate 801, an active layer 900 located on the light-shielding metal layer 903, a gate metal layer 901 located on the active layer 900, and a source-drain metal layer 902 located on the gate metal layer 901; the source and drain metal layers 902 are connected with the active layer 900 through via holes arranged on the ILD layer 804 and the GI layer 803; the common electrode layer 905 is connected with the source drain metal layer 902 through a via hole arranged on the PDL layer 806; the light-shielding metal layer 903 is located on one side of the active layer 900 far from the gate metal layer 903, and overlaps with a channel portion of the active layer 900 in a direction perpendicular to the array substrate, and the light-shielding layer 903 is used for shielding a channel formed by the active layer 900, so as to prevent light from irradiating the thin film transistor on the active layer 900 and causing adverse effects on the thin film transistor.
Similar to the above, the present application utilizes metal layers located in different layers of the array substrate to form a multi-layer compensation capacitor at least including three electrode plates, and according to a capacitance formula C ═ S/4 π kd, a compensation capacitor at least including three electrode plates is disposed on a plane of the array substrate, so that the compensation capacity of the compensation capacitor can be increased in an equal area occupying a direction perpendicular to the array substrate. Specifically, in the display panel provided in the embodiment of the present application, the compensation capacitor including at least three electrode plates is formed by which layers in the array substrate of the LCD, which can be designed according to needs, and is not limited herein.
The following examples are given.
Example four,
As shown in fig. 8, the compensation capacitor includes a sixth plate 910, a seventh plate 911 and an eighth plate 912;
the sixth electrode plate 910 and the active layer 900 are disposed on the same layer, and may be made of the same material in the same process;
the seventh polar plate 911 and the gate metal layer 901 are arranged on the same layer, and can be made of the same material in the same process;
the eighth plate 912 and the source/drain metal layer 902 are disposed on the same layer, and may be made of the same material in the same process.
The sixth plate 910 and the eighth plate 912 are located at two sides of the seventh plate 911, and the sixth plate 910 and the eighth plate 912 are electrically connected to the via hole of the ILD layer 804 through the GI layer 803; the orthographic projection of the seventh polar plate 911 is overlapped with the orthographic projections of the sixth polar plate 910 and the eighth polar plate 912 respectively in the direction perpendicular to the array substrate, so that the dead area between the polar plates of the compensation capacitor is increased under the condition of occupying the same area in the direction perpendicular to the array substrate, and the compensation capacity of the compensation capacitor is increased.
Example V,
As shown in fig. 9, the compensation capacitor includes a sixth plate 910, a seventh plate 911, an eighth plate 912 and a ninth plate 913;
the sixth electrode plate 910 and the active layer 900 are disposed on the same layer, and may be made of the same material in the same process;
the seventh polar plate 911 and the gate metal layer 901 are arranged on the same layer, and can be made of the same material in the same process;
the eighth plate 912 and the source/drain metal layer 902 are disposed on the same layer, and may be made of the same material in the same process;
the ninth electrode plate 913 and the light-shielding metal layer 903 are disposed on the same layer, and may be made of the same material in the same process.
The sixth polar plate 910 and the eighth polar plate 912 are located at two sides of the seventh polar plate 911, and the sixth polar plate 910 and the eighth polar plate 912 are electrically connected through vias disposed in the GI layer 803 and the ILD layer 804; the seventh polar plate 911 and the ninth polar plate 913 are located at two sides of the sixth polar plate 910, and the seventh polar plate 911 and the ninth polar plate 913 are electrically connected through via holes disposed in the Buffer layer 802 and the GI layer 803; the orthographic projection of the seventh polar plate 911 is overlapped with the orthographic projections of the sixth polar plate 910 and the eighth polar plate 912 respectively in the direction perpendicular to the array substrate; the orthographic projection of the ninth polar plate 913 and the orthographic projection of the sixth polar plate 910 are overlapped in the direction perpendicular to the array substrate, so that the area facing the polar plates of the compensation capacitor is increased under the condition that the equivalent area is occupied in the direction perpendicular to the array substrate, and the compensation capacity of the compensation capacitor is increased. The other reference numerals in the drawing denote the same structures as those in fig. 8.
Example six,
As shown in fig. 10, the compensation capacitor includes a sixth plate 910, a seventh plate 911, an eighth plate 912, a ninth plate 913, and a tenth plate 914;
the sixth electrode plate 910 and the active layer 900 are disposed on the same layer, and may be made of the same material in the same process;
the seventh polar plate 911 and the gate metal layer 901 are arranged on the same layer, and can be made of the same material in the same process;
the eighth plate 912 and the source/drain metal layer 902 are disposed on the same layer, and may be made of the same material in the same process;
the ninth electrode plate 913 and the light-shielding metal layer 903 are disposed on the same layer, and may be made of the same material in the same process;
the tenth electrode plate 914 is disposed in the same layer as the pixel electrode layer 904, and may be made of the same material in the same process.
The sixth polar plate 910 and the eighth polar plate 912 are located at two sides of the seventh polar plate 911, and the sixth polar plate 910 and the eighth polar plate 912 are electrically connected through vias disposed in the GI layer 803 and the ILD layer 804; the seventh polar plate 911 and the ninth polar plate 913 are located at two sides of the sixth polar plate 910; the seventh polar plate 911 and the tenth polar plate 914 are located at two sides of the eighth polar plate 912, and the seventh polar plate 911, the ninth polar plate 913 and the tenth polar plate 914 are electrically connected through via holes arranged in the Buffer layer 802, the GI layer 803, the ILD layer 804 and the PLN layer 805; the orthographic projection of the seventh polar plate 911 is overlapped with the orthographic projections of the sixth polar plate 910 and the eighth polar plate 912 respectively in the direction perpendicular to the array substrate; an orthographic projection of the ninth polar plate 913 and an orthographic projection of the sixth polar plate 910 are overlapped in a direction perpendicular to the array substrate; the orthographic projection of the tenth polar plate 914 and the orthographic projection of the eighth polar plate 912 are overlapped in the direction perpendicular to the array substrate, so that the direct facing area between the polar plates of the compensation capacitor is increased under the condition of occupying the same area in the direction perpendicular to the array substrate, and the compensation capacity of the compensation capacitor is increased. The other reference numerals in the drawing denote the same structures as those in fig. 8.
Example seven,
As shown in fig. 11, the compensation capacitor includes a sixth plate 910, a seventh plate 911, an eighth plate 912, a ninth plate 913, a tenth plate 914 and an eleventh plate 915;
the sixth electrode plate 910 and the active layer 900 are disposed on the same layer, and may be made of the same material in the same process;
the seventh polar plate 911 and the gate metal layer 901 are arranged on the same layer, and can be made of the same material in the same process;
the eighth plate 912 and the source/drain metal layer 902 are disposed on the same layer, and may be made of the same material in the same process;
the ninth electrode plate 913 and the light-shielding metal layer 903 are disposed on the same layer, and may be made of the same material in the same process;
the tenth electrode plate 914 and the pixel electrode layer 904 are disposed in the same layer, and can be made of the same material in the same process;
the eleventh electrode plate 915 and the common electrode layer 905 are disposed on the same layer, and may be made of the same material in the same process.
The sixth polar plate 910 and the eighth polar plate 912 are located at two sides of the seventh polar plate 911; the seventh polar plate 911 and the ninth polar plate 913 are located at two sides of the sixth polar plate 910; the seventh polar plate 911 and the tenth polar plate 914 are located at two sides of the eighth polar plate 912, and the seventh polar plate 911, the ninth polar plate 913 and the tenth polar plate 914 are electrically connected through via holes arranged in the Buffer layer 802, the GI layer 803, the ILD layer 804 and the PLN layer 805; the eighth plate 912 and the eleventh plate 915 are located at two sides of the tenth plate 914, and the sixth plate 910, the eighth plate 912 and the eleventh plate 915 are electrically connected through vias disposed in the GI layer 803, the ILD layer 804, the PLN layer 805 and the PDL layer 806; the orthographic projection of the seventh polar plate 911 is overlapped with the orthographic projections of the sixth polar plate 910 and the eighth polar plate 912 respectively in the direction perpendicular to the array substrate; an orthographic projection of the ninth polar plate 913 and an orthographic projection of the sixth polar plate 910 are overlapped in a direction perpendicular to the array substrate; the orthographic projection of the tenth polar plate 914 in the direction perpendicular to the array substrate is overlapped with the orthographic projections of the eighth polar plate 912 and the eleventh polar plate 915 respectively, so that the direct facing area between the polar plates of the compensation capacitor is increased under the condition of occupying the same area in the direction perpendicular to the array substrate, and the compensation capacity of the compensation capacitor is increased. The other reference numerals in the drawing denote the same structures as those in fig. 8.
Further, in practical implementation, in the display panel provided in this embodiment of the present application, one plate of the compensation capacitor is connected to one first signal line, and the other plate of the compensation capacitor is connected to a fixed potential line.
Specifically, in the display panel provided in this embodiment of the present invention, in the first to seventh embodiments, one side of the compensation capacitor is formed by a plurality of electrode plates electrically connected through a via, and the other side of the compensation capacitor is formed by a plurality of electrode plates electrically connected through another via, at least one electrode plate at one end of the compensation capacitor may be connected to a first signal line led out from the driving Circuit, so as to provide the compensation capacitor for the first signal line, so that at least one electrode plate at the other end of the compensation capacitor may be connected to a fixed potential line led out from an Integrated Circuit (IC) or a Flexible Printed Circuit (FPC) to introduce a potential signal into the compensation capacitor, and of course, the manner of supplying power to the compensation capacitor and introducing the potential signal is not limited to the manner described above, and are not intended to be limiting as long as they are consistent with the principles of the present application.
It should be noted that, in the first and fourth embodiments, that is, when the compensation capacitor includes three plates, one end of the compensation capacitor may be a middle plate of the three plates, and the other end may be two uppermost and lowermost plates electrically connected through a via.
Further, in practical implementation, in the display panel provided in this embodiment of the present application, at least one of the plates at one end of the compensation capacitor may be, for example, a fixed potential line itself, that is, the fixed potential line serves as one plate of the compensation capacitor, and forms the compensation capacitor with the other plate.
Further, in a specific implementation, in the display panel provided in this embodiment of the present application, the fixed potential line may be, for example, a Power Voltage (PVDD) bus or a reference voltage (Vref) bus.
Further, in a specific implementation, in the display panel provided in this embodiment of the present application, the compensation capacitor is at least located at one end of the first signal line, that is, the compensation capacitor may be set at any end of the first signal line, or may be set at both ends of the first signal line, and a specific setting manner may be designed as needed, which is not limited herein.
Further, in specific implementation, in the display panel provided in this embodiment of the present invention, the first signal line may be, for example, a scanning signal line led out from a gate driving circuit, or may be a data line led out from a data driving circuit.
Further, in practical implementation, in the display panel provided in this embodiment of the present application, the compensation capacitor may be disposed between the gate driving circuit and the pixel corresponding to the scan signal line, or may be disposed between the data driving circuit and the pixel corresponding to the data line, for example.
Further, in the display panel provided in this embodiment of the present invention, in a specific implementation, the implementation area of the scheme of the present invention may be an irregular area, that is, an irregular shape of the display panel designed according to some requirements in an electronic product, in the irregular area, when the scanning signal lines are distributed to the irregular area by the gate driving circuit or the data lines are distributed to the irregular area by the data driving circuit, the number of the corresponding pixels on each scanning signal line or each data line in each row is different, which may cause the capacitance on the TFT corresponding to the pixels on each scanning signal line or each data line in each row to be different, so that the delay of signal transmission on each signal line is different, and therefore, a compensation capacitor needs to be provided.
Specifically, in the display panel provided in the embodiment of the present application, the special-shaped area may be, for example, a groove for placing an electronic device such as a camera, an earphone, and the like in an electronic product, as shown in fig. 12, if the groove 151 in the display panel 152 is a transparent area, the implementation area 153 of the compensation capacitor described in the present application may be disposed in the groove 151; as shown in fig. 13, if the groove 151 in the display panel 152 is a cut-off region, an implementation region 253 of the compensation capacitor described in the present application may be disposed between an edge of the groove 151 and a display region of the display panel 152; when the display panel 152 is a right-angled rectangle, referring to fig. 14, the compensation capacitor described herein may be disposed at the right-angled region 353 of the display panel 152, for example; when the display panel 152 has a rounded rectangle shape, referring to fig. 15, the compensation capacitor described herein may be disposed at a rounded region 453 of the display panel 152, for example. Of course, the implementation area of the present application is not limited to the above area, and in the implementation, the design may be performed according to the need, and the implementation is only an example and is not limited.
Based on the same inventive concept, the embodiment of the present application further provides a display device, which includes the display panel provided by the embodiment of the present application. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the present application. The implementation of the display device can refer to the above embodiment of the package structure, and repeated descriptions are omitted.
To sum up, the embodiment of the present application provides a display panel and a display device, by setting a compensation capacitor composed of a plurality of plates on a signal line with a small number of corresponding pixels in a plurality of signal lines, in the same area, the compensation capacity of the compensation capacitor is increased, the area occupied by the compensation capacitor is reduced, the time for the signal output by the driving circuit to reach each row of pixels is ensured to be the same, and/or the time for the signal output by the driving circuit to reach each column of pixels is ensured to be the same, so that the uniformity of signal transmission is improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (12)
1. A display panel comprises an array substrate, wherein the array substrate comprises a plurality of pixels arranged in an array, and a first signal line and a second signal line which provide signals for the pixels and have the same extending direction, and the display panel is characterized by comprising: the number of pixels corresponding to the first signal line is smaller than that of pixels corresponding to the second signal line; a compensation capacitor is arranged on the first signal line and at least comprises three polar plates, and orthographic projections of one polar plate and the other two polar plates in the direction vertical to the array substrate are overlapped;
the display panel is an organic electroluminescent panel;
the array substrate comprises a plurality of thin film transistors and a plurality of storage capacitors; wherein the content of the first and second substances,
the thin film transistor includes: a grid metal layer and a source drain metal layer;
the storage capacitor comprises a first metal polar plate and a second metal polar plate, wherein the first metal polar plate and the grid metal layer are arranged on the same layer, and the second metal polar plate and the grid metal layer and the source drain metal layer are arranged on different layers.
2. The display panel of claim 1, wherein the compensation capacitor comprises a first plate, a second plate, and a third plate; the first polar plate and the third polar plate are positioned on two sides of the second polar plate, the orthographic projection of the second polar plate is overlapped with the orthographic projection of the first polar plate and the orthographic projection of the third polar plate in the direction vertical to the array substrate, and the first polar plate is electrically connected with the third polar plate; wherein the content of the first and second substances,
the first polar plate and the grid metal layer are arranged on the same layer;
the second polar plate and the second metal polar plate are arranged on the same layer;
the third polar plate and the source drain metal layer are arranged on the same layer.
3. The display panel according to claim 2, wherein the thin film transistor further comprises: an active layer;
the compensation capacitor further comprises a fourth polar plate; the second polar plate and the fourth polar plate are positioned on two sides of the first polar plate, the orthographic projection of the first polar plate is overlapped with the orthographic projection of the second polar plate and the orthographic projection of the fourth polar plate in the direction vertical to the array substrate, and the second polar plate is electrically connected with the fourth polar plate; wherein the content of the first and second substances,
the fourth polar plate and the active layer are arranged on the same layer.
4. The display panel of claim 3, wherein the array substrate further comprises: a pixel electrode layer;
the compensation capacitor further comprises a fifth polar plate; the second polar plate and the fifth polar plate are positioned on two sides of the third polar plate, the orthographic projection of the third polar plate is overlapped with the orthographic projection of the second polar plate and the orthographic projection of the fifth polar plate in the direction vertical to the array substrate, and the second polar plate, the fourth polar plate and the fifth polar plate are electrically connected; wherein the content of the first and second substances,
the fifth electrode plate and the pixel electrode layer are arranged on the same layer.
5. The display panel according to claim 1, wherein one plate of the compensation capacitor is connected to one of the first signal lines, and the other plate is connected to a fixed potential line.
6. A display panel as claimed in claim 1 wherein one of said at least three of said plates is the fixed potential line itself.
7. The display panel according to claim 1, wherein the compensation capacitor is located at least at one end of the first signal line.
8. The display panel according to claim 7, wherein the first signal line is a scanning signal line.
9. The display panel of claim 8, wherein the compensation capacitor is located between the gate driving circuit and the pixel region.
10. The display panel according to claim 7, wherein the first signal line is a data line.
11. The display panel of claim 10, wherein the compensation capacitor is located between the data driving circuit and the pixel region.
12. A display device characterized by comprising the display panel according to any one of claims 1 to 11.
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| CN107221536A (en) * | 2017-05-25 | 2017-09-29 | 上海天马微电子有限公司 | Array base palte, special-shaped display and display device |
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