CN107769793A - A kind of VPX frameworks wide band radio-frequency acquisition system - Google Patents
A kind of VPX frameworks wide band radio-frequency acquisition system Download PDFInfo
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- CN107769793A CN107769793A CN201711331669.9A CN201711331669A CN107769793A CN 107769793 A CN107769793 A CN 107769793A CN 201711331669 A CN201711331669 A CN 201711331669A CN 107769793 A CN107769793 A CN 107769793A
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- 238000012545 processing Methods 0.000 claims abstract description 36
- 238000006243 chemical reaction Methods 0.000 claims abstract description 22
- 238000004891 communication Methods 0.000 claims abstract description 8
- 230000003993 interaction Effects 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 claims description 4
- 241001274660 Modulus Species 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 6
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
- H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
- H04L49/352—Gigabit ethernet switching [GBPS]
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Abstract
The invention discloses a kind of VPX frameworks wide band radio-frequency acquisition system.System includes analog input card, processing board, storage board, main frame board, backboard, power subsystem, analog input card, processing board, storage board and main frame board are interconnected by backboard respectively, and wherein motherboard card realizes the communication of control signal by gigabit network interface connection analog input card, processing board；Motherboard card connects analog input card, processing board by PCIe interface, stores board to realize the interaction of data；Additionally interconnected between analog input card and processing board by SRIO interfaces, to increase data interaction bandwidth.The system is based on digital receiver technology, realize the input of binary channels intermediate frequency, after digital frequency conversion, demodulation, decoding, Multichannel Information shows and stored, give full play to high-speed PCI e bus advantages, extension storage plate and sound card video card are used for the storage and display of information, and extremely wide data bandwidth can ensure to transmit original sampling point data without falling a little.
Description
Technical field
The present invention relates to wireless communication field, more particularly to a kind of VPX（Reinforced bussing technique standard）Framework broadband is penetrated
Frequency acquisition system, and in particular to satellite communication, wide band radio-frequency collection, Digital Signal Processing, digital receiver.
Background technology
With radio communication, Software Radio Theory and application tend to be ripe and perfect in recent years, and software and radio technique is
Through being applied to by more and more extensive in military, civilian wireless communication system, one of core technology as software radio,
Digital receiver technology industry becomes more and more important.Conventional digital receiver scheme is to pass through the data after Digital Signal Processing
Outside low speed bus passes to PC, and its data bandwidth is little, when requiring that bandwidth just becomes not when original sampling point data are directly stored
It is enough.
The content of the invention
In view of the problem of technology is present now, the present invention provides a kind of VPX frameworks wide band radio-frequency acquisition system.
The technical solution adopted by the present invention is：A kind of VPX frameworks wide band radio-frequency acquisition system, it is characterised in that including 1
Analog input card, 1 processing board, 1 storage board, 1 main frame board, 1 backboard, 1 power subsystem, analog input card, place
Reason board, storage board and main frame board are interconnected by backboard respectively, and wherein motherboard card passes through gigabit network interface connection collection plate
Card, board is handled to realize the communication of control signal；Motherboard card connects analog input card, processing board by PCIe interface, deposited
Board is stored up to realize the interaction of data；Additionally interconnected by SRIO interfaces between analog input card and processing board, handed over to increase data
Mutual bandwidth；Analog input card, processing board are sent instructions to by main frame board, sample frequency and the gain of analog signal is controlled, controls
The demodulation of Digital Down Convert passage processed and rear end, the parameter of decoding, selectable progress signal is shown and storage；Power subsystem with
Backboard connects.
Described motherboard is arranged with three PCIE interfaces, and a PCIEX4 interface connects analog input card, a PCIEX4
Interface connection manages board, a PCIEX8 interfaces connection storage board, handles board and analog input card passes through SRIOX4 interfaces
Interconnection；Motherboard is arranged with three GE interfaces, connects analog input card, processing board, storage board respectively；Two-way analog channel is led to
Analog input card access system is crossed, analog input card is provided with two 10GE access road, and process plate is arranged with a 10GE and externally led to
Road.
Described analog input card includes fpga chip EP4SGX230KF40, temperature compensating crystal oscillator TCXO, digital dock generator
DDS9954, four difference amplifier ADL5201, two wave filter FILTER, digital dock generator DDS9954, the filter of sound surface
Ripple device CDCE62005, two analog-digital converter AD9467,10,000,000,000 fidonetFido conversion chip BCM8727, the first difference amplifier
After ADL5201 and the 3rd difference amplifier ADL5201 connects analog signal respectively, two wave filter FILTER are connected respectively, two
Wave filter FILTER connects the second difference amplifier ADL5201, the 4th difference amplifier ADL5201, the second differential amplification respectively
Device ADL5201 and the 4th difference amplifier ADL5201 connects two analog-digital converter AD9467, temperature compensating crystal oscillator TCXO connections respectively
Digital dock generator DDS9954, digital dock generator DDS9954 connection SAW filter CDCE62005, the filter of sound surface
Ripple device CDCE62005 connections two analog-digital converters AD9467, two analog-digital converter AD9467 connect described FPGA respectively
Chip EP4SGX230KF40, fpga chip EP4SGX230KF40 respectively by the interface of the interface of PCIe × 4 and SRIO × 4 export to
Backboard；Fpga chip EP4SGX230KF40 changes core by two XAUI × 10,000,000,000 described fidonetFidos of 4 interface connections simultaneously
XAUI signals are changed into SFI signal outputs by piece BCM8727,10,000,000,000 fidonetFido conversion chip BCM8727.
Described processing board includes four fpga chip EP4SGX230KF40 and 10,000,000,000 fidonetFido conversion chips
BCM8727, the signal of backboard are connected on the first fpga chip EP4SGX230KF40 by PCIE interfaces and SRIO interfaces, and first
Fpga chip EP4SGX230KF40 passes through SRIO interfaces, LVDS interface and the second fpga chip EP4SGX230KF40, respectively
Three fpga chip EP4SGX230KF40, the 4th fpga chip EP4SGX230KF40 connections, the second fpga chip
EP4SGX230KF40 passes through SRIO interfaces, LVDS interface and the first fpga chip EP4SGX230KF40, the 3rd FPGA cores respectively
Piece EP4SGX230KF40, the 4th fpga chip EP4SGX230KF40 connections, the 3rd fpga chip EP4SGX230KF40 lead to respectively
Cross SRIO interfaces, LVDS interface and the first fpga chip EP4SGX230KF40, the second fpga chip EP4SGX230KF40, the 4th
Fpga chip EP4SGX230KF40 connections, the 4th fpga chip EP4SGX230KF40 pass through SRIO interfaces, LVDS interface respectively
With the first fpga chip EP4SGX230KF40, the second fpga chip EP4SGX230KF40, the 3rd fpga chip
EP4SGX230KF40 connections, the first fpga chip EP4SGX230KF40 are assisted by XUAI × 10,000,000,000 described nets of 4 interface connections
Signal is changed into the output of optical signal form by view conversion chip BCM8727,10,000,000,000 fidonetFido conversion chip BCM8727.
The beneficial effects of the invention are as follows：The system is based on digital receiver technology, the input of binary channels intermediate frequency is realized, through number
After word frequency conversion, demodulation, decoding, Multichannel Information shows and stored, and gives full play to high-speed PCI e bus advantages, extension storage plate and
Sound card video card is used for the storage and display of information, and extremely wide data bandwidth can ensure to transmit original sampling point data without falling
Point.
Brief description of the drawings
Fig. 1 is VPX framework wide band radio-frequency acquisition system theory diagrams；
Fig. 2 is analog input card theory diagram in Fig. 1；
Fig. 3 is that board theory diagram is handled in Fig. 1.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described.
Reference picture 1, the system include 1 analog input card, 1 processing board, 1 storage board, 1 main frame board, 1
Backboard, 1 power subsystem, analog input card, processing board, storage board and main frame board are interconnected by backboard respectively, wherein main
Machine board realizes the communication of control signal by gigabit network interface connection analog input card, processing board；Motherboard card passes through PCIe
Interface connection analog input card, processing board, board is stored to realize the interaction of data；Additionally lead between analog input card and processing board
The interconnection of SRIO interfaces is crossed, to increase data interaction bandwidth；Analog input card, processing board, control are sent instructions to by main frame board
The sample frequency of analog signal and gain, demodulation, the parameter of decoding of Digital Down Convert passage and rear end are controlled, is selectively entered
Row signal shows and stored；Power subsystem is connected with backboard.
The motherboard of the system is arranged with three PCIE interfaces, and a PCIEX4 interface connects analog input card, one
PCIEX4 interface connections manage board, a PCIEX8 interfaces connection storage board, handle board and analog input card passes through
SRIOX4 interfaces interconnect；Motherboard is arranged with three GE interfaces, connects analog input card, processing board, storage board respectively；Two-way
Analog channel is provided with two 10GE access road by analog input card access system, analog input card, and process plate is arranged with one
10GE access roads.
Reference picture 2, the analog input card of the system include fpga chip EP4SGX230KF40, temperature compensating crystal oscillator TCXO, it is digital when
Clock generator DDS9954, four difference amplifier ADL5201, two wave filter FILTER, digital dock generator DDS9954,
SAW filter CDCE62005, two analog-digital converter AD9467,10,000,000,000 fidonetFido conversion chip BCM8727, the first difference
After amplifier ADL5201 and the second difference amplifier ADL5201 connects analog signal respectively, two wave filters are connected respectively
FILTER, two wave filter FILTER connect the 3rd difference amplifier ADL5201, the 4th difference amplifier ADL5201 respectively, the
Three difference amplifier ADL5201 and the 4th difference amplifier ADL5201 connect two analog-digital converter AD9467 respectively, and temperature compensation is brilliant
Shake TCXO connection digital dock generator DDS9954, digital dock generator DDS9954 connection SAW filters
CDCE62005, SAW filter CDCE62005 connection two analog-digital converters AD9467, two analog-digital converter AD9467
Fpga chip EP4SGX230KF40 is connected respectively, and fpga chip EP4SGX230KF40 passes through the interface of PCIe × 4 and SRIO respectively
× 4 interfaces are exported to backboard；Fpga chip EP4SGX230KF40 connects 10,000,000,000 fidonetFidos by the interface of two XAUI × 4 simultaneously
XAUI signals are changed into SFI signal outputs by conversion chip BCM8727,10,000,000,000 fidonetFido conversion chip BCM8727.
Reference picture 3, the processing board of the system includes four fpga chip EP4SGX230KF40 and 10,000,000,000 fidonetFidos are changed
Chip BCM8727, the signal of backboard are connected on the first fpga chip EP4SGX230KF40 by PCIE interfaces and SRIO interfaces,
First fpga chip EP4SGX230KF40 passes through SRIO interfaces, LVDS interface and the second fpga chip respectively
EP4SGX230KF40, the 3rd fpga chip EP4SGX230KF40, the 4th fpga chip EP4SGX230KF40 connections, second
Fpga chip EP4SGX230KF40 passes through SRIO interfaces, LVDS interface and the first fpga chip EP4SGX230KF40, respectively
Three fpga chip EP4SGX230KF40, the 4th fpga chip EP4SGX230KF40 connections, the 3rd fpga chip
EP4SGX230KF40 passes through SRIO interfaces, LVDS interface and the first fpga chip EP4SGX230KF40, the 2nd FPGA cores respectively
Piece EP4SGX230KF40, the 4th fpga chip EP4SGX230KF40 connections, the 4th fpga chip EP4SGX230KF40 lead to respectively
Cross SRIO interfaces, LVDS interface and the first fpga chip EP4SGX230KF40, the second fpga chip EP4SGX230KF40, the 3rd
Fpga chip EP4SGX230KF40 connections, the first fpga chip EP4SGX230KF40 connect 10,000,000,000 nets by the interface of XUAI × 4
Signal is changed into the output of optical signal form by protocol conversion chip BCM8727,10,000,000,000 fidonetFido conversion chip BCM8727.
The system realizes two passage intermediate frequency 140M（±36M）Analog signal inputs, and first carries out Simulation scale-up and filtering, so
After digitize, digital frequency conversion, demodulation, decoding afterwards, finally realize the multi channel presentation of information of two passages and storage.The system
Data bandwidth is abundant, by digitized signal can without fall a little be continuously transferred to rear end, can directly store.It can also select
Digitized signal entering signal process plate, rear end, or storage are transferred to again after extracting signal.
The analog input card of the system changes into analog signal the crucial board of data signal, and it can be a little logical without falling by data
Cross PCIe（Peripheral Component Interconnect Express, a kind of high speed serialization computer expansion bus mark
It is accurate）Processing board or storage board are crossed to, PCIe can also be not take up and pass through SRIO（Serial Rapid I/O, it is a kind of
High speed interconnecting interface）Interface is transferred to processing board, is exactly that can be not take up PCIe interface and SRIO interfaces in addition, passes through collection
Two 10,000,000,000 smooth network interfaces of board front panel are by data without falling output.
The system is based on VPX architecture designs, is used as data/address bus by PCIe interface, in that context it may be convenient at X86-based
The motherboard interaction of device chip is managed, motherboard has abundant attached peripheral hardware-memory plane and sound card video card, is easy to storage and display,
And it can be operated in rugged environment.
System Working Principle：System function division is four functional module boards:Analog input card, processing board, motherboard
Card, storage board.Wherein analog input card is used for amplification, filtering, the digitlization of analog signal；Board is handled to be used at signal numeral
Reason；Main frame board is that the control centre of system is also PCIe switching centre, and the function display module of final data；Storage
Board is the direct memory module after the digitlization of the message processing module or analog signal after signal transacting.
Analog input card is used for amplification, filtering, the digitlization of analog signal.Its clock has been designed as ensuring that sampling clock has
Higher phase noise, the scheme taken are：Temperature compensating crystal oscillator coordinates debounce chip, it is ensured that the phase that sampling clock keeps higher is made an uproar
Sound, in order to obtain the characteristic of the 1Hz stepping continuously adjustabes of sampling clock, add digital dock generator DDS9954.Simulation is logical
On road：Analog signal can suppress even-order harmonic by difference amplifier ADL5201, can be with then by SAW filter
Obtain preferably selectivity.Analog-digital converter select AD9467, a kind of 200MSPS16bit ADC can allow after analog-to-digital conversion by
Compared with high target.Data can be exported in real time by PCIe interface after digitlization, in order to increase the flexibility of equipment, be added in real time
Output interface, one is that another is two ten thousand of analog input card front panel to the SRIO interfaces for handling board by backboard
Million smooth network interfaces.Interface chip is a kind of ALTERA fpga chip EP4SGX230KF40, and its high speed serial port can not reach
10Gbps, so centre employs 10,000,000,000 fidonetFido conversion chip BCM8727, XAUI signals are changed into SFI signals.
Processing board is used for signal transacting.The signal of backboard is connected to a piece of fpga chip by PCIE interfaces and SRIO interfaces
On EP4SGX230KF40, this piece fpga chip and its excess-three piece fpga chip pass through HSSI High-Speed Serial Interface SRIO and low-speed parallel
Interface LVDS is with FULLMESS frameworks（Each node is connected with each other）Interconnection.FPGA cores as board input/output interface
Piece, also have and 10,000,000,000 fidonetFido conversion chip BCM8727 are entered by XUAI X4 interfaces all the way, signal is changed into optical signal form
Output.
Signal transacting needs many computing resources, and four fpga chip EP4SGX230KF40 carry out FULLMESS（Each
Node is all connected with each other）Connection, sufficient computing resource and flexible data channel, make data processing more flexible.And handle
The Data entries of board are additionally provided with the SRIO interfaces with collection plate except the PCIe interface of standard, external 10GE light network interfaces, allow
The data transfer of board is more flexible.
Main frame board is that the function of the control centre of system, the switching centre of PCIe data, and final data shows mould
Block.Main frame board draws two gigabit network interfaces, is connected respectively to analog input card and processing board, to analog input card and processing board
Function be controlled, main frame board has PCIe-switch（PCIE exchange chip）, the exchange for PCIe bus datas.
Main frame board peripheral components have sound card and video card is used for the display of data, and storage board is used for the storage of data.Storing board is
The peripheral hardware of main frame board, it can be stored data into by PCIe interface on memory plane.
Claims (4)
- A kind of 1. VPX frameworks wide band radio-frequency acquisition system, it is characterised in that including 1 analog input card, 1 processing board, 1 Store board, 1 main frame board, 1 backboard, 1 power subsystem, analog input card, processing board, storage board and main frame board Interconnected respectively by backboard, wherein motherboard card realizes control signal by gigabit network interface connection analog input card, processing board Communication；Motherboard card connects analog input card, processing board by PCIe interface, stores board to realize the interaction of data；Adopt Additionally interconnected between collection board and processing board by SRIO interfaces, to increase data interaction bandwidth；Sent and instructed by main frame board To analog input card, processing board, sample frequency and the gain of analog signal are controlled, controls the solution of Digital Down Convert passage and rear end Adjust, the parameter of decoding, selectable progress signal is shown and storage；Power subsystem is connected with backboard.
- A kind of 2. VPX frameworks wide band radio-frequency acquisition system according to claim 1, it is characterised in that described motherboard It is arranged with three PCIE interfaces, a PCIEX4 interface connects analog input card, and a PCIEX4 interface connection manages board, one PCIEX8 interfaces connection storage board, handles board and analog input card is interconnected by SRIOX4 interfaces；Motherboard is arranged with three GE interfaces, analog input card, processing board, storage board are connected respectively；Two-way analog channel is adopted by analog input card access system Collect the access road that board is provided with two 10GE, process plate is arranged with a 10GE access road.
- A kind of 3. VPX frameworks wide band radio-frequency acquisition system according to claim 2, it is characterised in that described collection plate Card includes fpga chip EP4SGX230KF40, temperature compensating crystal oscillator TCXO, digital dock generator DDS9954, four difference amplifiers ADL5201, two wave filter FILTER, digital dock generator DDS9954, SAW filter CDCE62005, two moduluses Converter AD9467,10,000,000,000 fidonetFido conversion chip BCM8727, the first difference amplifier ADL5201 and the 3rd difference amplifier After ADL5201 connects analog signal respectively, two wave filters FILTER, two wave filter FILTER are connected respectively and connect second respectively Difference amplifier ADL5201, the 4th difference amplifier ADL5201, the second difference amplifier ADL5201 and the 4th difference amplifier ADL5201 connects two analog-digital converter AD9467, temperature compensating crystal oscillator TCXO connection digital dock generator DDS9954 respectively, number Word clock generator DDS9954 connections SAW filter CDCE62005, SAW filter CDCE62005 two moulds of connection Number converter AD9467, two analog-digital converter AD9467 connect described fpga chip EP4SGX230KF40, FPGA core respectively Piece EP4SGX230KF40 is exported to backboard by the interface of the interface of PCIe × 4 and SRIO × 4 respectively；Fpga chip simultaneously EP4SGX230KF40 passes through 10,000,000,000 described fidonetFido conversion chip BCM8727 of two XAUI × 4 interface connections, 10,000,000,000 net associations XAUI signals are changed into SFI signal outputs by view conversion chip BCM8727.
- A kind of 4. VPX frameworks wide band radio-frequency acquisition system according to claim 2, it is characterised in that described process plate Card includes four fpga chip EP4SGX230KF40 and 10,000,000,000 fidonetFido conversion chip BCM8727, and the signal of backboard passes through PCIE Interface and SRIO interfaces are connected on the first fpga chip EP4SGX230KF40, and the first fpga chip EP4SGX230KF40 leads to respectively Cross SRIO interfaces, LVDS interface and the second fpga chip EP4SGX230KF40, the 3rd fpga chip EP4SGX230KF40, the 4th Fpga chip EP4SGX230KF40 connections, the second fpga chip EP4SGX230KF40 pass through SRIO interfaces, LVDS interface respectively With the first fpga chip EP4SGX230KF40, the 3rd fpga chip EP4SGX230KF40, the 4th fpga chip EP4SGX230KF40 connections, the 3rd fpga chip EP4SGX230KF40 pass through SRIO interfaces, LVDS interface and first respectively Fpga chip EP4SGX230KF40, the second fpga chip EP4SGX230KF40, the 4th fpga chip EP4SGX230KF40 connect Connect, the 4th fpga chip EP4SGX230KF40 passes through SRIO interfaces, LVDS interface and the first fpga chip respectively EP4SGX230KF40, the second fpga chip EP4SGX230KF40, the 3rd fpga chip EP4SGX230KF40 connections, first Fpga chip EP4SGX230KF40 passes through XUAI × 10,000,000,000 described fidonetFido conversion chip BCM8727, Wan Zhao of 4 interface connections Signal is changed into the output of optical signal form by fidonetFido conversion chip BCM8727.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112346645A (en) * | 2019-08-06 | 2021-02-09 | 天津光电通信技术有限公司 | Multichannel high-speed signal acquisition and processing board card based on FPGA and single-board PC |
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| CN107769793B (en) | 2024-01-05 |
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