CN107769777A - A kind of optional frequency eliminator of divisor and its eliminating method - Google Patents
A kind of optional frequency eliminator of divisor and its eliminating method Download PDFInfo
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Abstract
The present invention relates to frequency eliminator field, the optional frequency eliminator of more particularly to a kind of divisor and its eliminating method, including input and output portion and control unit, input and output portion includes phase selector, buffer and the frequency eliminator being sequentially connected, input phase is inputted by phase selector, and buffered device to frequency eliminator exports；Control unit includes Deltasigma modulator, divisor selection control and the Selecting phasing controller being sequentially connected；And output phase is supplied to Deltasigma modulator and divisor selection control by frequency eliminator, buffer outputs it result and is supplied to Selecting phasing controller and divisor selection control, Selecting phasing controller sends control signal to phase selector, the optional frequency eliminator of this divisor and its eliminating method are determined the scalability for being currently based on phase rotation Δ Σ frequency eliminators and portable problem, it is particularly suitable for needing switching frequency elimination coefficient in real time, changes the occasion of output frequency.
Description
Technical field
The present invention relates to frequency eliminator technical field, the optional frequency eliminator of more particularly to a kind of divisor and its eliminating method.
Background technology
Traditional phaselocked loop (PLL) is broadly divided into two major classes, and the first kind is integer type phaselocked loop (Integer PLL), the
Two classes are decimal type phaselocked loop (Fractional-N PLL).Integer type PLL uses integer frequency eliminator, can only export integral multiple
Reference frequency, if necessary to export more accurate frequency, then need to reduce reference input frequency, propose high-frequency resolution
Rate.But for PLL, we be typically designed can using the 1/10 of reference frequency as PLL loop bandwidth, if reduce
Reference data frequency, PLL bandwidth will reduce, while increasing the phase noise with interior voltage controlled oscillator (VCO), it is necessary to
Bulky capacitor is used in loop filter, adds the area of chip.Decimal type PLL is using delta-sigma modulator control feedback frequency elimination
Device, frequency eliminator is produced a divisor between N and N+1, because delta-sigma modulator shifts quantizing noise onto high frequency, then pass through
Loop filter is filtered out, and decimal type PLL can use higher reference data frequency, and loop bandwidth can not be limited,
But, the further raising that filters out or can limit loop bandwidth of quantizing noise limited by the modulation capability of delta-sigma modulator,
In the prior art, Publication No. CN1864333, time of disclosure are on November 15th, 2006, entitled " Phase-switching bimodulus frequency elimination
So the Chinese invention patent document of device " is exactly, there is provided a kind of phase-switching dual modulus prescaler with dual-mode frequency divider.It is described
Frequency divider includes：The first and second 2 frequency dividing circuit (A；B), wherein the second 2 frequency dividing circuit (B) is coupled to described one 2 point
The output of frequency circuit (A), and at least described 2nd 2 frequency dividing circuit (B) includes each being separated by 90 ° of four phase outputs.Carry
For phase selection unit (PSU), for selecting four phase outputs (Ip, In, Qp, Qn of the 2nd 2 frequency dividing circuit (B)；INi、
INni, INq, INnq) in one；Further it is provided that phase control unit (RTU), for providing control to phase selection unit
Signal (C0, NC0；C1、NC1；C2, NC2), wherein phase selection unit (PSU) is according to control signal (C0, NC0；C1、NC1；
C2, NC2) perform four phase outputs (Ip, In, Qp, Qn；INi, INni, INq, INnq) selection；According to control logic come
Implement the phase selection unit (PSU).
In order to improve the noise shaping effect of conventional delta-sigma modulator, a kind of effective method is to use to revolve based on phase
Turn the modulator of (phase rotation), and improve the sample frequency of delta-sigma modulator.Quantization so is being greatly lowered
While noise, quantizing noise can be shifted onto at higher frequency, this can further relax the limitation to loop bandwidth, make tune
The quantizing noise of device processed, VCO phase noise and chip area have the result of a comparison balance.But it is traditional based on
Phase rotation delta-sigma modulator realizes that autgmentability and portability are all bad, it is impossible to adapt to using analog form
Special needs are in real time in the PLL of accurate frequency hopping.
The content of the invention
It is an object of the invention to provide a kind of frequency eliminator and its eliminating method that can arbitrarily select divisor, certainly it is currently based on
The scalability of phase place delta-sigma frequency eliminator and portable problem, are particularly suitable for needing switching frequency elimination coefficient in real time, change
Become the occasion of output frequency.
To achieve the above object, technical solution of the present invention is as follows：
A kind of optional frequency eliminator of divisor, it is characterised in that：Including input and output portion and control unit, input and output portion is included successively
Connected phase selector, buffer and frequency eliminator, input phase are inputted by phase selector, and buffered device is defeated to frequency eliminator
Go out；Control unit includes delta-sigma modulator, divisor selection control and the Selecting phasing controller being sequentially connected；And frequency eliminator
Output clock signal and reset signal are respectively supplied to delta-sigma modulator and divisor selection control, after buffer
Clock signal be available to Selecting phasing controller and divisor selection control, Selecting phasing controller is sent out to phase selector
Send control signal.
The input of the delta-sigma modulator also includes preset divisor setting value K, M and PHSEL input point, delta-sigma
The output end of modulator also includes test signal output point.
A kind of optional eliminating method of divisor, it is characterised in that：
Phase selector exports from the Selecting phasing one of input enters row buffering and shaping to buffer, and then buffer will buffer
As a result export to frequency eliminator, divisor selection control and Selecting phasing controller；
Frequency eliminator will buffer result and carry out frequency elimination and export result, and provides reset signal and feed back to divisor as control signal
Selection control, clock signal is provided to delta-sigma modulator；
The reset signal for control signal and the frequency eliminator output that divisor selection control exports according to delta-sigma modulator selects to phase
Select controller output control signal；
Selecting phasing controller selects to control according to the control signal that divisor selection control exports to phase selector output phase
Signal processed, phase corresponding to control phase selector selection, realize circulation selection divisor frequency elimination.
The buffer is exported to be used as to the buffering result of divisor selection control and Selecting phasing controller and selected for divisor
Select the clock of the digit circuit of controller and Selecting phasing controller；It is through too slow that buffer, which is exported to the buffering result of frequency eliminator,
Punching and the phase of shaping.
The later output of the frequency eliminator frequency elimination is exactly the clock signal finally exported；Frequency eliminator provides clock signal
Give clock of the delta-sigma modulator as digit circuit；Frequency eliminator export selection control to output be one be used for reset
Reset signal.
The reset signal make divisor selection control repeated during value corresponding to count down to before action, realization follows
Ring controls the function of Selecting phasing.
The delta-sigma modulator produces one according to its preset divisor setting value K, M and PHSEL value and is used to select to divisor
The signal DIV_CTL of controller output, and a test signal SDMOUT for being used for delta-sigma modulator test.
Beneficial effects of the present invention are as follows：
First, the optional frequency eliminator of a kind of divisor provided by the invention, multiple input phases enter phase selector, phase selector
The MUX selection circuits of a multi input are actually equivalent to, at any time control of the Selecting phasing controller to phase selector
Pulse only has one for height, ensures that any time only has a phase to pass through phase selector；Buffer is defeated by phase selector
The phase information gone out is subject to shaping, improves driving force；Frequency eliminator is a programmable frequency eliminator, its frequency elimination coefficient directly by
External register control, implement by counter form to realize, switchings of the actual frequency elimination coefficient N.f Jing Guo phase with
Afterwards, the number of rising edge is only counted here, N+1 integer frequency elimination is completed, will finally obtain actual N.f frequency elimination coefficients, is counted
The value of number device also needs to output and gives divisor selection control module；Delta-sigma modulator uses single loop framework, single loop framework
Output area is smaller, more preferable for the decimal frequency elimination operating reliability of phase place framework.
2nd, the optional frequency eliminator of a kind of divisor provided by the invention, using two-stage delta-sigma modulator, 2bit quantizations
Width, the divisor 0.f of actual divisor N.f fractional part is set by two input K and M of delta-sigma modulator, according to 0.f's
Size, in the range of the selection control range of divisor is fixed into (0.f-0.1) ~ (0.f+0.3), the control range of this divisor
Selection is by PHSEL [3:0] setting provide because our delta-sigma modulator only have two bit quantify output, we only need by
The control range of divisor is set within the scope of 0 ~ 0.4, after setting K, M, PHSEL according to actual divider value N.f, Δ-
The output of sigma modulator is exactly the control signal for controlling divisor scope to change from (N.f-0.1) ~ (N.f+0.3), this change
The average value of divisor scope is just just equal to f.
3rd, the optional eliminating method of a kind of divisor provided by the invention, input signal are multiple phases at equal intervals, and phase is selected
The selection input signal for selecting device is controlled by Selecting phasing controller, selects one of phase output, subsequently into buffer,
By the shaping of buffer, phase is transmitted further to integer frequency eliminator, divisor selection control and Selecting phasing controller, wherein
The clock exported to divisor selection control and Selecting phasing controller as digit circuit of buffer, to integer frequency eliminator
Phase is exactly that its last needs does the phase divided exactly, and the later output CKOUT of integer frequency eliminator frequency elimination is exactly the clock after frequency elimination
Signal, and used as the clock of the digit circuit of delta-sigma modulator for it, integer frequency eliminator can give output selection in addition
Controller provides a reset signal signal COUNTER, and this reset signal signal is to allow divisor selection control counting down to
Action before being repeated during corresponding value, realizes the function of loop control Selecting phasing, and PH_CTL inputs to Selecting phasing control
Device processed, by certain logical process, then the control signal of multidigit is exported to phase selector, realizes correct Selecting phasing.
4th, the optional eliminating method of a kind of divisor provided by the invention, K, M, PHSEL are that according to specific needs preset removes
Number setting value, it generates two signals, and one is DIV_CTL, this input of control signal as divisor selection control
Signal, produce PH_CTL again by logical process and give Selecting phasing controller, SDMOUT then as test signal, tests delta-sigma
The working condition of modulator.
5th, the optional eliminating method of a kind of divisor provided by the invention, completely using verilog code modes come real
It is existing, more than 2 any divisor is supported, and use the phase-rotation of ten phase compositions mode to make divisor can be with
Be accurate to 0.1, than traditional decimal frequency eliminator quantizing noise optimize it is more preferable, reduce the requirement of PLL bandwidth, be applicable model
Enclose widely, it is portable also very good.
Brief description of the drawings
Fig. 1 is a kind of structural representation of preferred scheme of frequency eliminator of the present invention；
Fig. 2 is a kind of schematic diagram of preferred scheme of input phase of the present invention；
Fig. 3 is a kind of Selecting phasing controller schematic diagram of preferred scheme of the present invention；
Fig. 4 is a kind of phase schematic diagram of preferred scheme of the present invention；
Fig. 5 is a kind of preferred scheme schematic diagram of Phase-switching of the present invention；
Fig. 6 is another preferred scheme schematic diagram of Phase-switching of the present invention；
Embodiment
Below by way of several specific embodiments come further illustrate realize the object of the invention technical scheme, it is necessary to explanation
It is that technical scheme is including but not limited to following examples.
Embodiment 1
Such as Fig. 1, a kind of optional frequency eliminator of divisor, including input and output portion and control unit, input and output portion include being sequentially connected
Phase selector, buffer and frequency eliminator, input phase inputs by phase selector, and buffered device to frequency eliminator exports；Control
Portion processed includes delta-sigma modulator, divisor selection control and the Selecting phasing controller being sequentially connected；And frequency eliminator will export
Phase is supplied to delta-sigma modulator and divisor selection control, and buffer outputs it result and is supplied to Selecting phasing controller
With divisor selection control, Selecting phasing controller sends control signal to phase selector.
This is a kind of most basic embodiment of the optional frequency eliminator of divisor of the present invention.Multiple input phases enter applying aspect choosing
Device is selected, the actual MUX selection circuits for being equivalent to a multi input of phase selector, Selecting phasing controller is to phase at any time
The control pulse of digit selector only has one for height, ensures that any time only has a phase to pass through phase selector；Buffer
The phase information that phase selector exports is subject to shaping, improves driving force；Frequency eliminator is a programmable frequency eliminator, its
Frequency elimination coefficient is directly controlled by external register, is implemented by counter form to realize, actual frequency elimination coefficient N.f warps
Cross after the switching of phase, only count the number of rising edge here, complete N+1 integer frequency elimination, will finally obtain actual
N.f frequency elimination coefficients, the value of counter also need to output and give divisor selection control module；Delta-sigma modulator uses single loop frame
Structure, the output area of single loop framework is smaller, more preferable for the decimal frequency elimination operating reliability of phase place framework.
Embodiment 2
Such as Fig. 1, a kind of optional frequency eliminator of divisor, including input and output portion and control unit, input and output portion include being sequentially connected
Phase selector, buffer and frequency eliminator, input phase inputs by phase selector, and buffered device to frequency eliminator exports；Control
Portion processed includes delta-sigma modulator, divisor selection control and the Selecting phasing controller being sequentially connected；And frequency eliminator will export
Phase is supplied to delta-sigma modulator and divisor selection control, and buffer outputs it result and is supplied to Selecting phasing controller
With divisor selection control, Selecting phasing controller sends control signal to phase selector；The input of the delta-sigma modulator
End also includes preset divisor setting value K, M and PHSEL input point, and the output end of delta-sigma modulator also includes test signal
Output point.
This is a kind of preferred embodiment of the optional frequency eliminator of divisor of the present invention.Multiple input phases enter applying aspect choosing
Device is selected, the actual MUX selection circuits for being equivalent to a multi input of phase selector, Selecting phasing controller is to phase at any time
The control pulse of digit selector only has one for height, ensures that any time only has a phase to pass through phase selector；Buffer
The phase information that phase selector exports is subject to shaping, improves driving force；Frequency eliminator is a programmable frequency eliminator, its
Frequency elimination coefficient is directly controlled by external register, is implemented by counter form to realize, actual frequency elimination coefficient N.f warps
Cross after the switching of phase, only count the number of rising edge here, complete N+1 integer frequency elimination, will finally obtain actual
N.f frequency elimination coefficients, the value of counter also need to output and give divisor selection control module；Delta-sigma modulator uses single loop frame
Structure, the output area of single loop framework is smaller, more preferable for the decimal frequency elimination operating reliability of phase place framework；Using two
Level delta-sigma modulator, 2bit quantify bit wide, and the divisor 0.f of actual divisor N.f fractional part is by two of delta-sigma modulator
Input K and M is set, and according to 0.f size, the selection control range of divisor is fixed to (0.f-0.1) ~ (0.f+0.3) model
In enclosing, the selection of the control range of this divisor is by PHSEL [3:0] setting provides, because our delta-sigma modulator only has two
Bit quantifies output, and we are only needed within the scope of the control range of divisor is set in into 0 ~ 0.4, according to actual divider value N.f
After setting K, M, PHSEL, the output of delta-sigma modulator is exactly to control divisor scope to become from (N.f-0.1) ~ (N.f+0.3)
The control signal of change, the average value of the divisor scope of this change are just just equal to f.
Embodiment 3
Such as Fig. 1 to 6, a kind of optional eliminating method of divisor：
Phase selector exports from the Selecting phasing one of input enters row buffering and shaping to buffer, and then buffer will buffer
As a result export to frequency eliminator, divisor selection control and Selecting phasing controller；
Frequency eliminator will buffer result and carry out frequency elimination and export result, and provides reset signal and feed back to divisor as control signal
Selection control, clock signal is provided to delta-sigma modulator；
The reset signal for control signal and the frequency eliminator output that divisor selection control exports according to delta-sigma modulator selects to phase
Select controller output control signal；
Selecting phasing controller selects to control according to the control signal that divisor selection control exports to phase selector output phase
Signal processed, phase corresponding to control phase selector selection, realize circulation selection divisor frequency elimination.
This is a kind of most basic embodiment of the optional eliminating method of divisor of the present invention.Input signal for it is multiple at equal intervals
Phase, the selection input signal of phase selector are controlled by Selecting phasing controller, select one of phase output, then
Into buffer, by the shaping of buffer, phase is transmitted further to integer frequency eliminator, divisor selection control and Selecting phasing
The clock of divisor selection control and Selecting phasing controller as digit circuit is given in exporting for controller, wherein buffer, gives
The phase of integer frequency eliminator is exactly that its last needs does the phase divided exactly, and the later output CKOUT of integer frequency eliminator frequency elimination is exactly
Clock signals after frequency elimination, and used as the clock of the digit circuit of delta-sigma modulator for it, integer frequency elimination in addition
Device can give output selection control to provide a reset signal signal COUNTER, and this reset signal signal is to allow divisor to select
Controller repeated during value corresponding to count down to before action, realize the function of loop control Selecting phasing, PH_CTL is defeated
Enter and give Selecting phasing controller, by certain logical process, then export the control signal of multidigit to phase selector, realize just
True Selecting phasing.
Embodiment 4
Such as Fig. 1 to 6, a kind of optional eliminating method of divisor：
Phase selector exports from the Selecting phasing one of input enters row buffering and shaping to buffer, and then buffer will buffer
As a result export to frequency eliminator, divisor selection control and Selecting phasing controller；
Frequency eliminator will buffer result and carry out frequency elimination and export result, and provides reset signal and feed back to divisor as control signal
Selection control, clock signal is provided to delta-sigma modulator；
The reset signal for control signal and the frequency eliminator output that divisor selection control exports according to delta-sigma modulator selects to phase
Select controller output control signal；
Selecting phasing controller selects to control according to the control signal that divisor selection control exports to phase selector output phase
Signal processed, phase corresponding to control phase selector selection, realize circulation selection divisor frequency elimination；
The buffer exports to be used as divisor selection control to the buffering result of divisor selection control and Selecting phasing controller
The clock of the digit circuit of device and Selecting phasing controller processed；Buffer export to frequency eliminator buffering result be by buffering and
The phase of shaping；
The later output of the frequency eliminator frequency elimination is exactly the clock signal finally exported；Clock signal is supplied to by frequency eliminator
Clock of the delta-sigma modulator as digit circuit；It is a weight for being used to reset that frequency eliminator, which is exported to output selection control,
Confidence number；
The reset signal make divisor selection control repeated during value corresponding to count down to before action, realize that circulation is controlled
The function of Selecting phasing processed；
The delta-sigma modulator produces one according to its preset divisor setting value K, M and PHSEL value and is used to select to control to divisor
The signal DIV_CTL of device controller output, and a test signal SDMOUT for being used for delta-sigma modulator test.
This is a kind of preferred embodiment of the optional eliminating method of divisor of the present invention.Input signal for it is multiple at equal intervals
Phase, the selection input signal of phase selector are controlled by Selecting phasing controller, select one of phase output, then
Into buffer, by the shaping of buffer, phase is transmitted further to integer frequency eliminator, divisor selection control and Selecting phasing
Exporting to divisor selection control and Selecting phasing controller as the clock of digit circuit for controller, wherein buffer, gives
The phase of integer frequency eliminator is exactly that its last needs does the phase divided exactly, and the later output CKOUT of integer frequency eliminator frequency elimination is exactly
Clock signals after frequency elimination, and used as the clock of the digit circuit of delta-sigma modulator for it, integer frequency elimination in addition
Device can give output selection control to provide a reset signal signal COUNTER, and this reset signal signal is to allow divisor to select
Controller repeated during value corresponding to count down to before action, realize the function of loop control Selecting phasing, PH_CTL is defeated
Enter and give Selecting phasing controller, by certain logical process, then export the control signal of multidigit to phase selector, realize just
True Selecting phasing；K, M, PHSEL are preset divisor setting values according to specific needs, and it generates two signals, and one is
DIV_CTL, this input signal of control signal as divisor selection control, PH_CTL is produced by logical process to phase again
Position selection control, SDMOUT then as signal is tested, test the working condition of delta-sigma modulator；Verilog is used completely
Code modes are realized, support more than 2 any divisor, and using ten phase phase-rotation's formed
Mode makes divisor can be as accurate as 0.1, than traditional decimal frequency eliminator quantizing noise optimize it is more preferable, reduce PLL band
Wide requirement, the scope of application is very extensive, portable also very good.
Embodiment 5
Such as Fig. 1 to 6, input signal is 10 phase at equal intervals clock CKIN [9:0] clock signals, are inputted by PH_SEL
[9:0] control, select one of clock to export, subsequently into buffer, by the shaping of buffer, clock is passed again
Integer frequency eliminator, divisor selection control are defeated by, divisor selection control is given in exporting for Selecting phasing controller, wherein buffer
Clock with Selecting phasing controller as digit circuit, the clock to integer frequency eliminator are exactly that it finally needs to do to divide exactly
Clock, the later output CKOUT of integer frequency eliminator frequency elimination are exactly the clock signals after frequency elimination, and are modulated as delta-sigma
The clock of the digit circuit of device uses for it, K, M, and PHSEL is the value of divisor register settings according to specific needs, and it is produced
Two signals are given birth to, one is DIV_CTL, this input signal of control signal as divisor selection control, by logic
Processing produces PH_CTL and gives Selecting phasing controller again, and SDMOUT then as signal is tested, tests the work shape of delta-sigma modulator
State, integer frequency eliminator, which can be given, in addition exports selection control one reset signal COUNTER of offer, and this reset signal is to allow
Divisor selection control repeated during value corresponding to count down to before action, realize the function of loop control Selecting phasing,
PH_CTL inputs to Selecting phasing controller, by certain logical process, then exports the control signal of 10 to Selecting phasing
Device, realize correct Selecting phasing.
10 phase input clock enter phase selector, and phase selector is actual to be equivalent to one 10 input
MUX selection circuits, at any time PH_SEL [9:0] there was only one for height, ensure that any time only has a phase to pass through phase
Digit selector.The phase information that phase selector exports is subject to shaping by buffer, improves driving (drive) ability.Integer division
Frequency device is a programmable integer frequency eliminator, and its frequency elimination coefficient is directly controlled by external register, and specific implementation passes through counting
Device form realizes that actual frequency elimination coefficient N.f only counts the number of rising edge here after phase switching, completes
N+1 integer frequency elimination, will finally obtain actual N.f frequency elimination coefficients, and the value of counter also needs to output and selects to control to divisor
Device module processed.Delta-sigma modulator uses single loop framework, and the output area of single loop framework is smaller, for phase
The decimal frequency elimination operating reliability of rotation frameworks is more preferable, and this example employs two-stage delta-sigma modulator, 2bit quantizations
Width, the divisor 0.f of actual divisor N.f fractional part is set by two input K and M of delta-sigma modulator, according to 0.f's
Size, in the range of the selection control range of divisor is fixed into (0.f-0.1) ~ (0.f+0.3), the control range of this divisor
Selection is by PHSEL [3:0] setting provide because our delta-sigma modulator only have two bit quantify output, we only need by
The control range of divisor is set within the scope of 0 ~ 0.4, after setting K, M, PHSEL according to actual divider value N.f, Δ-
The output of sigma modulator is exactly the control signal for controlling divisor scope to change from (N.f-0.1) ~ (N.f+0.3), this change
The average value of divisor scope is just just equal to f.
| {PHSEL,SDMOUT} | DIV_CTL | DIV NUMBER |
| 000000~000011 | 1000~1011 | (N-2).8~(N-1).1 |
| 000100~000111 | 0111~1010 | (N-2).9~(N-1).2 |
| 001000~001011 | 0110~1001 | (N-1).0~(N-1).3 |
| 001100~001111 | 0101~1000 | (N-1).1~(N-1).4 |
| 010000~010011 | 0100~0111 | (N-1).2~(N-1).5 |
| 010100~010111 | 0011~0110 | (N-1).3~(N-1).6 |
| 011000~011011 | 0010~0101 | (N-1).4~(N-1).7 |
| 011100~011111 | 0001~0100 | (N-1).5~(N-1).8 |
| 100000~100011 | 0000~0011 | (N-1).6~(N-1).9 |
| 100100~100111 | 1100~0010 | (N-1).7~N.0 |
Control signal in upper table corresponds with actual divisor, delta-sigma modulator at most four controls of output of second order
Signal processed, this four control signals are just corresponding（N.f-0.1）Four divisors of ~ (N.f+0.3), N can value as needed do
Corresponding setting.This is to work as behind actual divisor decimal point situation about being used when more than 1, when the divisor decimal point of reality
N.0 or N.1 when being less equal than 1 below, for example, ~ N.9, then delta-sigma modulator does not need work, it is only necessary to logical
Cross divisor control signal corresponding to judgement PHSEL outputs:
| PHSEL | DIV_CTL | DIV NUMBER |
| 0000 | 1011 | (N-2).8 |
| 0001 | 1010 | (N-2).9 |
| 0010 | 1001 | (N-1).0 |
| 0011 | 1000 | (N-1).1 |
| 0100 | 0111 | (N-1).2 |
| 0101 | 0110 | (N-1).3 |
| 0110 | 0101 | (N-1).4 |
| 0111 | 0100 | (N-1).5 |
| 1000 | 0011 | (N-1).6 |
| 1001 | 0010 | (N-1).7 |
| 1010 | 0001 | (N-1).8 |
| 1011 | 0000 | (N-1).9 |
| Other | 1100 | N.0 |
It is one group of combinational logic circuit to export selection control, according to the situation of input setting value, directly by previously given one
Class value is assigned to PH_CTL, and in divisor selection control, COUNTER is exported from integer frequency eliminator, there is provided is selected to divisor
Controller, the clock signals of cycle phase control signal are produced, are count down in COUNTER from 1 in N+1 a cycle, divisor
N+1 groups 2bit phase controlling signal corresponding to selection control output, this N+1 group two of recycling output in next cycle
Bit phase control signals, the phase controlling signal among each cycle control phase of the phase among each cycle
The total amount being moved along, then it is evenly distributed among N+1 cycle, the total amount of the advance of mean allocation phase can be with maximum limit
The working frequency of the raising circuit of degree, adapts to more high speed situations.PH_SEL is in N>When 5,6 groups of 2bit controls can be exported
Signal, 6 groups of 2bit control signals are then synchronously sequentially output with COUNTER values and are come out, in N<When=5, corresponding N can be exported
Group 2bit control signals, output are also synchronously to be sequentially output N groups 2bit control signals with COUNTER values.
Specific transformational relation is as follows：
| DIV_CTL | DIV NUMBER | PH_CTL |
| 1011 | (N-2).8 | 10→10→10→10→10→10 |
| 1010 | (N-2).9 | 01→10→10→10→10→10 |
| 1001 | (N-1).0 | 01→10→10→01→10→10 |
| 1000 | (N-1).1 | 01→01→10→01→10→10 |
| 0111 | (N-1).2 | 01→01→10→01→01→10 |
| 0110 | (N-1).3 | 01→01→01→01→01→10 |
| 0101 | (N-1).4 | 01→01→01→01→01→01 |
| 0100 | (N-1).5 | 00→01→01→01→01→01 |
| 0011 | (N-1).6 | 00→01→01→00→01→01 |
| 0010 | (N-1).7 | 00→00→01→00→01→01 |
| 0001 | (N-1).8 | 00→00→01→00→00→01 |
| 0000 | (N-1).9 | 00→00→00→00→00→01 |
| 1100 | N.0 | 00→00→00→00→00→00 |
N>PH_CTL corresponds to the setting value of corresponding divisor when 5
| DIV_CTL | DIV NUMBER | PH_CTL |
| 1011 | 3.8 | 10→00→00→00→01 |
| 1010 | 3.9 | 00→01→00→00→01 |
| 1001 | 4.0 | 00→01→00→01→01 |
| 1000 | 4.1 | 01→01→00→01→01 |
| 0111 | 4.2 | 01→01→01→01→01 |
| 0110 | 4.3 | 01→01→01→01→01 |
| 0101 | 4.4 | 01→01→01→01→10 |
| 0100 | 4.5 | 01→10→01→01→10 |
| 0011 | 4.6 | 01→10→01→10→10 |
| 0010 | 4.7 | 10→10→01→10→10 |
| 0001 | 4.8 | 10→10→10→10→10 |
| 0000 | 4.9 | 10→10→10→10→10 |
| 1100 | 5.0 | 00→00→00→00→00 |
PH_CTL corresponds to the setting value of corresponding divisor during N=5
| DIV_CTL | DIV NUMBER | PH_CTL |
| 1011 | 2.8 | 11→11→11→11 |
| 1010 | 2.9 | 10→11→11→11 |
| 1001 | 3.0 | 10→11→10→11 |
| 1000 | 3.1 | 10→10→10→11 |
| 0111 | 3.2 | 10→10→10→10 |
| 0110 | 3.3 | 01→10→10→10 |
| 0101 | 3.4 | 01→10→01→10 |
| 0100 | 3.5 | 01→01→01→10 |
| 0011 | 3.6 | 01→01→01→01 |
| 0010 | 3.7 | 00→01→01→01 |
| 0001 | 3.8 | 00→01→00→01 |
| 0000 | 3.9 | 00→00→00→01 |
| 1100 | 4.0 | 00→00→00→00 |
PH_CTL corresponds to the setting value of corresponding divisor during N=4
| DIV_CTL | DIV NUMBER | PH_CTL |
| 1011 | 1.8 | 00→00→01 |
| 1010 | 1.9 | 00→00→01 |
| 1001 | 2.0 | 00→01→01 |
| 1000 | 2.1 | 11→11→11 |
| 0111 | 2.2 | 11→10→11 |
| 0110 | 2.3 | 10→10→11 |
| 0101 | 2.4 | 10→10→10 |
| 0100 | 2.5 | 10→01→10 |
| 0011 | 2.6 | 01→01→10 |
| 0010 | 2.7 | 01→01→01 |
| 0001 | 2.8 | 01→00→01 |
| 0000 | 2.9 | 00→00→01 |
| 1100 | 3.0 | 00→00→00 |
PH_CTL corresponds to the setting value of corresponding divisor during N=3
Selecting phasing controller is actually a 10bit shift register, initial value 1000000000, is selected by divisor
The output signal PH_CTL of controller, to control the digit that the position of high level is moved, the control signal point of 12 6 times backward
To judge DFF EN signals, EN initial voltages are low, and 00 to keep enabled signal EN be a low clock cycle, PH_SEL [9:
0] high level position keeps a cycle, and 01 draws high enabled mono- clock cycle of signal EN, makes high level shift mono-,
10 draw high enabled two clock cycles of signal EN, make high level shift two, and 11 draw high enabled tri- cycles of signal EN, make height
Level shift tri-, realize that circulation of the high level in 10bit control signals occurs, and ensure only one as height.
The value of such as Fig. 4 shift register is directly controlled into MUX circuit, it is possible to which phase component passes through corresponding to selection
MUX circuit, it is achieved thereby that the decimal frequency elimination based on phase rotation.
Claims (7)
- A kind of 1. optional frequency eliminator of divisor, it is characterised in that：Including input and output portion and control unit, input and output portion include according to Secondary connected phase selector, buffer and frequency eliminator, input phase are inputted by phase selector, and buffered device is defeated to frequency eliminator Go out；Control unit includes delta-sigma modulator, divisor selection control and the Selecting phasing controller being sequentially connected；And frequency eliminator Output phase is supplied to delta-sigma modulator and divisor selection control, buffer outputs it result and is supplied to Selecting phasing Controller and divisor selection control, Selecting phasing controller send control signal to phase selector.
- A kind of 2. optional frequency eliminator of divisor as claimed in claim 1, it is characterised in that：The input of the delta-sigma modulator End also includes preset divisor setting value K, M and PHSEL input point, and the output end of delta-sigma modulator also includes test signal Output point.
- A kind of 3. optional eliminating method of divisor, it is characterised in that：Phase selector exports from the Selecting phasing one of input enters row buffering and shaping to buffer, and then buffer will buffer As a result export to frequency eliminator, divisor selection control and Selecting phasing controller；Frequency eliminator will buffer result and carry out frequency elimination and export result, and provides reset signal and feed back to divisor as control signal Selection control, clock signal is provided to delta-sigma modulator；The reset signal for control signal and the frequency eliminator output that divisor selection control exports according to delta-sigma modulator selects to phase Select controller output control signal；Selecting phasing controller selects to control according to the control signal that divisor selection control exports to phase selector output phase Signal processed, phase corresponding to control phase selector selection, realize circulation selection divisor frequency elimination.
- A kind of 4. optional eliminating method of divisor as claimed in claim 3, it is characterised in that：The buffer is exported to divisor The buffering result of selection control and Selecting phasing controller is as the number for divisor selection control and Selecting phasing controller The clock of position circuit；It is by buffering the phase with shaping that buffer, which is exported to the buffering result of frequency eliminator,.
- A kind of 5. optional eliminating method of divisor as claimed in claim 3, it is characterised in that：The frequency eliminator frequency elimination is later Output is exactly the clock signal finally exported；Clock signal is supplied to delta-sigma modulator as digit circuit by frequency eliminator Clock；It is a reset signal for being used to reset that frequency eliminator, which is exported to output selection control,.
- A kind of 6. optional eliminating method of divisor as claimed in claim 5, it is characterised in that：The reset signal selects divisor The action before controller repeats in value corresponding to counting down to is selected, realizes the function of loop control Selecting phasing.
- A kind of 7. optional eliminating method of divisor as claimed in claim 3, it is characterised in that：The delta-sigma modulator according to Its preset divisor setting value K, M and PHSEL value produces a signal DIV_CTL for being used to export to divisor selection control, with An and test signal SDMOUT for being used for delta-sigma modulator test.
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| US20100183109A1 (en) * | 2009-01-21 | 2010-07-22 | National Taiwan University | Phase locked loop capable of fast locking |
| CN103001631A (en) * | 2011-09-16 | 2013-03-27 | 英飞凌科技奥地利有限公司 | Fractional-n phase locked loop |
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