CN107764313A - A kind of tiny satellite star upper-part intelligent test system - Google Patents
A kind of tiny satellite star upper-part intelligent test system Download PDFInfo
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- CN107764313A CN107764313A CN201711027060.2A CN201711027060A CN107764313A CN 107764313 A CN107764313 A CN 107764313A CN 201711027060 A CN201711027060 A CN 201711027060A CN 107764313 A CN107764313 A CN 107764313A
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- arm
- fpga
- serial ports
- computer
- host computer
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D21/00—Measuring or testing not otherwise provided for
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0421—Multiprocessor system
Abstract
The present invention proposes a kind of tiny satellite star upper-part intelligent test system, including slave computer and host computer, wherein, slave computer is embedded-type ARM+FPGA plates, host computer is general industrial computer, and various controls realize that program of lower computer is without change by being noted on host computer；The switch of the program-controlled multiple control units of system, and acquisition component voltage x current state, part serial data frame and parse；The FPGA of slave computer achieves a butt joint the expansion of mouthful quantity, and ARM realizes the processing to data, is connected between ARM and FPGA by 11 bit address buses with 8 bit data bus, serial ports SECO is grasped by ARM；The software of the system includes PC upper computer softwares, lower computer FPGA software and ARM softwares, wherein, communicated by telemetry frame, program control command and upper note instruction between host computer and ARM, communicated between FPGA and ARM by part serial ports request signal, part serial ports answer signal, switch block power supply signal and part analog signalses.
Description
Technical field
The present invention relates to spacecraft-testing technical field, more particularly to a kind of tiny satellite star upper-part intelligence test system
System.
Background technology
Time-consuming for the environmental test of microsatellite product, it is stronger that manpower is relied on, and product test at present need to match somebody with somebody special survey
Try equipment.With company's Spot Purchasing product increase, there is the situation that same bulk article is tested, will by the way of traditional
A large amount of test equipments are taken, cause the nervous situation of resource.Therefore need badly and develop a kind of automated test device, part can be substituted
Operating function, human hand is liberated, save device resource.
The content of the invention
In order to solve the problems of the prior art, the present invention proposes a kind of tiny satellite star upper-part intelligence test system
System.The present invention adopts the following technical scheme that：
A kind of tiny satellite star upper-part intelligent test system, including slave computer and host computer, wherein, slave computer is insertion
Formula ARM+FPGA plates, host computer are general industrial computer, and various controls realize that program of lower computer need not change by being noted on host computer
It is dynamic；The switch of the program-controlled multiple control units of system, and acquisition component voltage x current state, part serial data frame and solve
Analysis；The FPGA of slave computer achieves a butt joint the expansion of mouthful quantity, and ARM realizes the processing to data, passes through 11 between ARM and FPGA
Address bus is connected with 8 bit data bus, and serial ports SECO is grasped by ARM；Interface between FPGA and star upper-part includes：
Serial ports, for being communicated with part；Relay corresponding component adds power-off, and DO interfaces are used for 422 interfaces for driving gyro, and A/D connects
Mouth is used to gather magnetometer data；The software of the system includes PC upper computer softwares, lower computer FPGA software and ARM softwares,
Wherein, communicated between host computer and ARM by telemetry frame, program control command and upper note instruction, pass through portion between FPGA and ARM
Part serial ports request signal, part serial ports answer signal, switch block power supply signal and part analog signalses are communicated；
Further, the serial port protocol of part is changed using upper note instruction dynamic.
Further, the system is not powered to part, simply accesses D.C. regulated power supply path, ensures part power supply peace
Quan Xing；Slave computer board is powered to be provided by the USB interface of host computer, while USB interface also is responsible for remote measurement serial communication.
Further, the hardware of slave computer is realized using the scheme using serial port drive chip, negative to reduce FPGA programmings
Load, FPGA are only responsible for serial ports gating being mapped to ARM.
Further, the remote measurement framing is that all 8 serial ports reply datas are formed into 1 to fix 1280 big frames, each
The fixed length of serial ports distribution, then passed once by under per second to realize.
Further, FPGA and ARM interfaces are three address blocks, i.e.,：Director data, reply data, rdy signals；Wherein,
Director data is communicated by 128 byte FIFO with reply data and realized, i.e., only need to be by continuously writing row to same address.
Further, the host computer send configuration cycle command, the timing round robin cycle to part serial communication are carried out
Configuration.
Further, it is defeated to include bus control module, serial communication module, AD sampling modules and PWM for the FPGA softwares
Go out module；Wherein, bus control module is realized and ARM bus communications；Serial communication module includes serial ports and receives and send；
PWM output module output multi-channel pwm signals, drive relay switch；AD communication modules mainly communicate with A/D chip.
Further, the host computer realizes that automatized script configures by making script configuration txt file.
Further, the serial ports primitive frame of the host computer timing parsing ARM passbacks, carries out parsing real-time display, follows up
Unit status, and the data to receiving preserve.
Brief description of the drawings
Fig. 1 is the systematic schematic diagram of the tiny satellite star upper-part intelligent test system of the present invention；
Fig. 2 is the hardware implementations schematic diagram of slave computer；
Fig. 3 is the software implement scheme schematic diagram of system；
Fig. 4 is FPGA functional block diagram；
Fig. 5 is ARM process charts；
Fig. 6 is host computer process chart.
Embodiment
The present invention is further described for explanation and embodiment below in conjunction with the accompanying drawings.
The present invention tiny satellite star upper-part intelligent test system, principle as shown in Figure 1, using slave computer with it is upper
Machine designs, and slave computer is embedded-type ARM+FPGA plates, and host computer is general industrial computer.Various controls are real by being noted on host computer
Existing, program of lower computer is without change.The switch of the program-controlled multiple control units of system, and acquisition component voltage x current state, portion
Part serial data frame simultaneously parses.The serial port protocol system of part also can be changed dynamically.System is not powered to part, and simply access is straight
Voltage-stabilized power supply path is flowed, ensures part Supply Security.Slave computer board is powered to be provided by the USB interface of host computer, while USB
Interface also is responsible for remote measurement serial communication.
The function and performance requirement of the system of the present invention are as follows：
[functional requirement]
1. can preset equipment plus power-off time, according to add power-off time to carry out test product plus, power operation；
2. pair 422 serial communication equipment carry out periodicity poll, polling cycle 250ms, 500ms, 1ms can configure；
3. the analog output of pair equipment under test carries out periodicity poll, polling cycle 250ms, 500ms, 1ms can configure；
4. the electric current of pair equipment under test is monitored；
5. pair equipment carries out safety management, discovering device continuous communiction mistake or electric current exceed threshold value, then to equipment under test
Resetted；
6. the key parameter can show, recorded equipment under test, the number of resets of equipment.
[performance requirement]
1. can enter the control of the between-line spacing duration time switch of 1 week, control sequence is up to 50；
2. equipment under test is no less than 8,8 serial communications can be connect simultaneously；
3. communication polling cycle 250ms, 500ms, 1ms can configure；
4. the tunnel of analog acquisition 4：Scope -5V~+5V, 5 ‰ ± 1mV of precision；
5. the tunnel of analog acquisition 21：0~+3.3V of scope.
The hardware of slave computer is mainly realized with ARM+FPGA frameworks, the expansion for mouthful quantity that achieved a butt joint with FPGA, uses ARM
The processing to data is realized, as shown in Fig. 2 be connected between ARM and FPGA by 11 bit address buses with 8 bit data bus,
Interface between FPGA and star upper-part includes：Serial ports, for being communicated with part；Relay corresponding component adds power-off, and DO connects
Mouth is used for 422 interfaces for driving gyro, and A/D interfaces are used to gather magnetometer data.
Slave computer may realize that hardware implementations have two kinds, and the main distinction of both schemes is：Whether serial ports is used
Control chip 16C554, that is, increase hardware circuit.Conventional spaceborne machine design can subtract using the scheme using serial port drive chip
Few FPGA programmings burden, FPGA are only responsible for serial ports gating being mapped to ARM.Serial ports SECO is grasped by ARM.
The software implement scheme of system is as shown in figure 3, including PC upper computer softwares, lower computer FPGA software, ARM softwares.
Wherein, communicated between host computer and ARM by telemetry frame, program control command and upper note instruction.Pass through portion between FPGA and ARM
Part serial ports request signal, part serial ports answer signal, switch block power supply signal and part analog signalses are communicated.
Remote measurement framing is that all 8 serial ports reply datas are formed into 1 to fix 1280 big frames, each serial ports distribution fixation
Length, then passed once by under per second to realize.Because big frame is transmitted by 115200bps, i.e., most 11520 bytes per second, institute
State the biography down of enough telemetries.Each byte of frame length 128, it is as shown in table 1 that it forms form.
The remote measurement frame format of table 1
| Byte | Title | Explanation | Remarks |
| 1-4 | Markers 1 | Component request instructs markers | |
| 5-8 | Markers 2 | Part reply data markers | |
| 9 | Source of stable pressure voltage | ||
| 10 | Voltage stabilizing ource electric current | ||
| 12 | Response frame length | ||
| 13-128 | Part response primitive frame | Data length is indefinite because part is different | Not enough fill out 0 |
Data communication between FPGA and ARM uses bus, and its principle is identical with PXI shared drive mechanism.To ARM's
Memory address carries out planning distribution, is associated with the peripheral hardwares such as serial ports, relay, AD.Bus address width 9, data width 8
Position.Similar shared drive is operated, and various register manipulations are mapped to memory headroom corresponding to ARM by FPGA.It is corresponding by ARM read-writes
Address is realized.
8 road serial communications, FPGA and ARM interfaces are three address blocks, i.e.,：Director data, reply data, rdy signals.Its
In, director data is communicated by 128 byte FIFO with reply data and realized, i.e., only need to be by continuously writing row to same address.
Internal memory agreed address is as shown in table 2.
The memory address of table 2 is arranged
| ARM addresses | FPGA | Length | Remarks |
| 0x68000000 | 9’h0000 | 16 bytes | The area of serial ports 1 |
| 0x68000010 | 9’h0010 | 16 bytes | The area of serial ports 2 |
| 0x68000020 | 9’h0020 | 16 bytes | The area of serial ports 3 |
| 0x68000030 | 9’h0030 | 16 bytes | The area of serial ports 4 |
| 0x68000040 | 9’h0040 | 16 bytes | The area of serial ports 5 |
| 0x68000050 | 9’h0050 | 16 bytes | The area of serial ports 6 |
| 0x68000060 | 9’h0060 | 16 bytes | The area of serial ports 7 |
| 0x68000070 | 9’h0070 | 16 bytes | The area of serial ports 8 |
| 0x68000080 | 9’h0080 | 16 bytes | 4 road AD register sections |
| 0x68000090 | 9’h0090 | 16 bytes | No. 9 relay switch area |
Note：Each serial ports area should be FIFO containing register, just continuously can read whole frame for single-address.
Note is mainly the loading of command sequence script with noting instruction processing on processing, serial ports in command script.Host computer passes through
Note is handled into ARM on serial ports, the switching manipulation as corresponding to ARM is transmitted to FPGA progress.
Part serial communication uses timing repeating query mode, can be carried out once using configuration cycle as per 100ms, after sending instruction
50ms is waited to gather again.
FPGA softwares, as shown in figure 4, mainly by following several Implement of Function Module：Bus control module, serial communication mould
Block, AD sampling modules and PWM output modules.Wherein, in bus control module, address bus is designed as 11, to each serial ports
Data reserve enough memory headrooms.Bus control module is realized and ARM bus communications.Serial communication module includes serial ports and connect
Receive and send, FPGA each serial-port mapping is director data, reply data, rdy signals these three byte addresses.ARM
Continuously it need to only read and be continuously written into just, equivalent to memory headroom read-write operation.PWM output module output multi-channel pwm signals,
Drive relay switch.Pwm signal is positive pulse, pulsewidth 20ms.Part pwm signal is output to I/O port driving part.AD is communicated
Module mainly communicates with A/D chip, chronologically carries out.
The total sequential flow of ARM softwares, as shown in Figure 5.Bus communication is used between ARM and FPGA, including：Read FPGA
8 serial ports reply data frames of memory address, the claim frame for writing FPGA 8 serial ports of memory address, write-in FPGA memory address
9 relay switch values, read FPGA memory address 4 tunnel bipolarity AD values.
ARM receives the command sequence of host computer, carries out dissection process immediately, you can realizes that programmable data is handled.AD numbers
Chip AD passages are directly used according to acquisition process, gather 21 AD data.Serial ports, which receives data processing, to be included receiving FPGA transmissions
Serial data frame, plus markers.ARM will also collect all data, carry out packing framing.Mainly have：8 serial ports receive
Data frame and 9 current-voltage samplings data.
Upper computer software realizes on PC, for data monitoring and control unit time switch, using Labcvi rings
Border is developed, and the flow of upper computer software is as shown in Figure 6.Upper computer software can be realized automatically by making script configuration txt file
Change script configuration.
Command sequence is the operating time sequence for each relay, and host computer is stored in after disposably loading command sequence
Queue, switch order then is sent to slave computer to the time.Command sequence script format is as shown in table 3.The component request of 8 serial ports
Instruction can be changed dynamically, and it is as shown in table 4 that script format is noted on serial ports.
The program control command sequence TXT script formats of table 3
| // the date | Time | Relay number | On or off | Remarks |
| 20170413 | 15:00 | 1 | 1 | Open |
| 20170413 | 16:00 | 1 | 0 | Close |
| 20170414 | 09:00 | 2 | 1 | Open |
| 20170414 | 14:00 | 2 | 0 | Close |
Note instruction TXT script formats on the serial ports of table 4
| // serial port | Upper note data frame content |
| 1 | D9 11 22 33 44 55 66 77 |
| 2 | DA 11 22 33 44 55 66 77 |
The serial ports primitive frame of host computer timing parsing ARM passbacks, carries out parsing real-time display, follow up unit status, and right
The data received are preserved.
Above content is to combine specific preferred embodiment further description made for the present invention, it is impossible to is assert
The specific implementation of the present invention is confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of not departing from present inventive concept, some simple deduction or replace can also be made, should all be considered as belonging to the present invention's
Protection domain.
Claims (10)
1. a kind of tiny satellite star upper-part intelligent test system, including slave computer and host computer, it is characterised in that：The bottom
Machine is embedded-type ARM+FPGA plates, and host computer is general industrial computer, and various controls are realized by being noted on host computer, slave computer journey
Sequence is without change；The switch of the program-controlled multiple control units of system, and acquisition component voltage x current state, part serial ports number
According to frame and parse；The FPGA of slave computer achieves a butt joint the expansion of mouthful quantity, and ARM realizes the processing to data, between ARM and FPGA
It is connected by 11 bit address buses with 8 bit data bus, serial ports SECO is grasped by ARM；Between FPGA and star upper-part
Interface includes：Serial ports, for being communicated with part；Relay corresponding component adds power-off, and DO interfaces are used to drive the 422 of gyro to connect
Mouthful, A/D interfaces are used to gather magnetometer data；The software of the system include PC upper computer softwares, lower computer FPGA software and
ARM softwares, wherein, communicated between host computer and ARM by telemetry frame, program control command and upper note instruction, FPGA and ARM it
Between pass through part serial ports request signal, part serial ports answer signal, switch block power supply signal and part analog signalses carry out
Communication.
2. system according to claim 1, it is characterised in that：The serial port protocol of part is changed using upper note instruction dynamic.
3. system according to claim 1, it is characterised in that：The system is not powered to part, and it is steady simply to access direct current
Voltage source path, ensure part Supply Security；Slave computer board is powered to be provided by the USB interface of host computer, while USB interface
It also is responsible for remote measurement serial communication.
4. system according to claim 1, it is characterised in that：The hardware of slave computer, which is realized to use, uses serial port drive chip
Scheme, with reduce FPGA programming burden, FPGA only be responsible for by serial ports gating is mapped to ARM.
5. system according to claim 1, it is characterised in that：The remote measurement framing is by all 8 serial ports reply datas
Composition 1 fixes 1280 big frames, the fixed length of each serial ports distribution, is then passed once by under per second to realize.
6. system according to claim 1, it is characterised in that：FPGA and ARM interfaces are three address blocks, i.e.,：Instruct number
According to, reply data, rdy signals；Wherein, director data is communicated by 128 byte FIFO with reply data and realized.
7. system according to claim 1, it is characterised in that：The host computer send configuration cycle command, to part string
The timing round robin cycle of mouth communication is configured.
8. system according to claim 1, it is characterised in that：The FPGA softwares include bus control module, serial ports leads to
Interrogate module, AD sampling modules and PWM output modules；Wherein, bus control module is realized and ARM bus communications；Serial communication mould
Block includes serial ports and receives and send；PWM output module output multi-channel pwm signals, drive relay switch；AD communication module masters
To be communicated with A/D chip.
9. system according to claim 1, it is characterised in that：The host computer configures txt file reality by making script
Existing automatized script configuration.
10. system according to claim 1, it is characterised in that：The serial ports of the host computer timing parsing ARM passbacks is original
Frame, parsing real-time display is carried out, follow up unit status, and the data to receiving preserve.
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| CN110531708A (en) * | 2019-07-02 | 2019-12-03 | 上海大学 | A kind of identification of Three Degree Of Freedom piezoelectric actuating platform and compensating control method |
| CN110837449A (en) * | 2019-11-04 | 2020-02-25 | 深圳航天东方红海特卫星有限公司 | UVM-based onewire communication special verification platform and method |
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