CN107733440B

CN107733440B - Polygonal structured LDPC processing method and device

Info

Publication number: CN107733440B
Application number: CN201610666791.0A
Authority: CN
Inventors: 李立广; 徐俊; 许进
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2016-08-12
Filing date: 2016-08-12
Publication date: 2022-12-02
Anticipated expiration: 2036-08-12
Also published as: CN107733440A

Abstract

The invention provides a polygonal structured LDPC processing method and a device, wherein the method comprises the following steps: determining a basic check matrix and an expansion factor Z, wherein the basic check matrix comprises at least one of a first type element and a second type element and a third type element, the difference value of any 2 shift values in all shift values of the third type element is an integral multiple of a parameter B, the parameter B is a positive integer factor of the expansion factor Z, and Z is a positive integer; and performing polygonal type structured low-density parity check (LDPC) coding or polygonal type structured LDPC decoding according to the basic check matrix and the expansion factor Z. The invention solves the problems of the multilateral LDPC code in the prior art that the decoding hardware is increased and the decoding speed is low because of the increase of the column weight and the multiple elements.

Description

Multilateral structured LDPC processing method and device

Technical Field

The invention relates to the field of communication, in particular to a multilateral structured LDPC processing method and device.

Background

Digital communication systems in the related art generally include three parts: a transmitting end, a channel, and a receiving end. The transmitting end can perform channel coding on the information sequence to obtain a coded codeword, interleave the coded codeword, map the interleaved bits into modulation symbols, and then process and transmit the modulation symbols according to the communication channel information. In the channel, the data transmission is distorted due to multipath, motion, etc., which cause a specific channel response, and is further deteriorated due to noise and interference. The receiving end receives the modulation symbol data after passing through the channel, and the modulation symbol data is distorted and needs to be specially processed to restore the original information sequence.

According to the method for coding the information sequence by the sending end, the receiving end can carry out corresponding processing on the received data so as to reliably recover the original information sequence. The encoding method must be visible at both the transmitting and receiving ends. Generally, the coding process is based on Forward Error Correction (FEC) coding, which adds some redundant information to the information sequence. The receiving end can reliably recover the original information sequence by using the redundant information. Currently, channel coding is commonly used, such as Low Density Parity Check (LDPC) code. In the FEC encoding process, FEC encoding is performed on an information sequence with k bits to obtain an FEC encoded codeword with n bits (redundant bits are n-k), and the FEC encoding rate is k/n. The LDPC code is a linear block code that can be defined by a very sparse parity check matrix or bipartite graph, and low-complexity coding and decoding can be realized only by using the sparsity of the parity check matrix thereof, so that the LDPC code is put to practical use. Various practices and theories prove that the LDPC code is the channel code with the most excellent performance under an Additive White Gaussian Noise (AWGN) channel, the performance is very close to the Shannon limit, and the LDPC code is superior to a convolutional code and a Turbo code. In particular, structured LDPC codes have been becoming mainstream applications due to their structural features, and are being used in many applications such as ieee802.11ac, ieee802.11ad, ieee802.11aj, ieee802.11e, ieee802.11n, DVB, microwave communication, and optical fiber communication.

The parity check matrix H of the structured LDPC code is a matrix of mb x z rows and nb x z columns, which is composed of mb x nb block matrixes, each block matrix is different powers of a basic permutation matrix of z x z, and the block matrixes are cyclic shift matrixes of a unit matrix. Having the form:

if it is not

Is provided with

I.e. a full zero square matrix of size zxz; if it is used

Is an integer greater than or equal to 0, is defined

I.e. a non-all-zero square matrix of size zxz, such as: p here is a standard permutation matrix of z × z, as follows:

by such powers

Each block matrix can be uniquely identified, and if a certain block matrix is an all-0 matrix, the matrix is generally represented by-1; if the cyclic shift s of the unit array is obtained, the method

Is equal to s, so all

A base check matrix Hb may be constructed, and we take the non-1 elements in the base check matrix to be non-zero square matrix element values. And z is a dimension indicating the standard permutation matrix, which we refer to herein as a spreading factor, and may also be a lifting value or a sub-matrix shift size. Therefore, the structured LDPC code can be completely uniquely determined by the base check matrix Hb and the spreading factor z. The basic check Matrix Hb is also called a basic Matrix (Base Matrix) or a prototype diagram (basegraph), and the like.

In the structured LDPC code described above, in the basic check matrix Hb, there are only 1 non-zero square matrix element values in any row-column index, but in the actual structured LDPC code, there is another structure, that is, in the basic check matrix Hb, there are not only 1 non-zero square matrix element value in any row-column index, but also a plurality of non-zero square matrix element values, and we refer to this LDPC code as a polygonal structured LDPC code. And expanding the polygonal structured LDPC basic check matrix Hb into a parity check matrix H, and if a certain row index has a plurality of non-zero square matrix element values, adding the square matrices after the cyclic shift of a plurality of unit matrices by corresponding shift values. As a simple example, the base check matrix size is 2 x 3, the spreading factor is 4, it can be seen that the row 0 column element and the row 1 column element both contain 2 non-zero square matrix element values,

the parity check matrix obtained after the expansion is:

when decoding structured LDPC code and the above mentioned multilateral structured LDPC code, layered decoding is generally adopted, which can greatly reduce iteration times compared with full parallel decoding. The parity check matrix H has 8 rows, which means that there are 8 parity check codes, and each parity check code needs to be decoded separately during decoding, and if all 8 parity check codes update data, an iteration is performed. In the layered decoding, the decoding parallelism can be adopted as p to reduce the hardware overhead, namely p parity check codes are updated simultaneously, the current parity check code and the next parity check code in the iteration run by the same updating module, the hardware is reusable, and the complexity is low. When the decoding parallelism is p, and the value of p is generally equal to the integer factor of the spreading factor, then the soft information to be decoded in the z length needs to be stored in a plurality of storage blocks in a layered mode respectively, which can be well solved in a decoder of a general structured LDPC code, but when the multi-edge structured LDPC structure is adopted, the soft information in one parallelism p can not be stored in one storage block, which brings the problem of increased decoding complexity, and certain processing time delay is needed due to the occurrence of hardware problems such as decoding address conflict.

Aiming at the problems that in the related art, a layered decoder of a multilateral structured LDPC code needs different storage, so that the decoding speed of the decoder is greatly reduced and the decoding complexity is increased, no effective solution is provided at present.

Disclosure of Invention

The embodiment of the invention provides a multilateral structured LDPC processing method and a multilateral structured LDPC processing device, which are used for at least solving the problems of increased decoding hardware and low decoding speed of multilateral LDPC codes due to increased column weight and multiple elements.

According to an embodiment of the present invention, there is provided a method for processing a multi-edge structured LDPC, including: determining a basic check matrix and a spreading factor Z, wherein the basic check matrix comprises at least one of a first type of elements, a second type of elements and a third type of elements, the first type of elements correspond to a Z multiplied by Z all-zero matrix, the second type of elements correspond to a matrix obtained by circularly right shifting a Z multiplied by Z unit matrix by corresponding 1 shift value, and the third type of elements correspond to a matrix obtained by adding all matrices obtained by circularly right shifting the Z multiplied by Z unit matrix by corresponding at least 2 shift values respectively; the difference value of any 2 shift values in all the shift values of the third type element is an integral multiple of a parameter B, wherein the parameter B is a positive integer factor of an expansion factor Z, and Z is a positive integer; and performing polygonal type structured low-density parity check (LDPC) coding or polygonal type structured LDPC decoding according to the basic check matrix and the expansion factor Z.

Optionally, the parameter B is equal to an integer value obtained by dividing a spreading factor Z by a parameter P, where the parameter P is a coding parallelism in the polygonal-type structured LDPC coding, the coding parallelism is P that indicates that P parity check codes in the polygonal-type structured LDPC coding are updated simultaneously, and the parameter P is a positive integer.

Optionally, the parameter P is selected according to one of the following manners:

selecting according to the prearranged convention of the encoding end and the decoding end;

selecting according to the indication of the signaling sent from the coding end to the decoding end;

selecting according to the instruction of the signaling sent from the decoding end to the encoding end;

the selection is made according to system predefined settings.

Optionally, in the basic check matrix, a specific value of the first type element is represented by a null value or-1, and shift values of the second type element and the third type element are integers greater than or equal to 0 and smaller than Z.

Optionally, the basic check matrix is a basic check matrix with M rows and N columns, and includes: the system matrix block C0 of M x (N-M) formed by (N-M) columns and the check matrix block C1 of M x M formed by M columns, wherein at least 1 third-type element exists in the check matrix block C1, the sub-matrix C2 in the check matrix block C1 is in a dual diagonal structure, and the number of all shift values in the sub-matrix C2 is an odd number.

Optionally, the sub-matrix C2 is a matrix formed by rows 0 to M0-1 and columns 0 to M0-1 in the check matrix block C1, where M0 is an integer greater than 1 and less than or equal to M.

Optionally, the sub-matrix C2 includes 1 odd column and M0-1 even column, where the odd column is only odd shift values in the columns, and the even column is only even shift values in the columns.

Optionally, the number of any shift values in all the shift values of the odd columns except for 1 shift value is an even number, and/or the number of any shift values in all the shift values of the even columns is an even number.

Optionally, the basic check matrix is a basic check matrix with M rows and N columns, and includes: d0 elements of the first type, D1 elements of the second type and D2 elements of the third type, M being a positive integer, N being an integer greater than M, D2 being a positive integer, D0 and D1 both being non-negative integers, D0+ D1+ D2 being less than or equal to mxn.

Optionally, the performing the polygonal-type structured LDPC encoding or the polygonal-type structured LDPC decoding according to the base check matrix and the spreading factor Z includes: coding the source sequence to be coded with the length of (N-M) xZ bits according to the basic check matrix and the spreading factor Z to obtain an LDPC codeword sequence with the length of NxZ bits; and decoding the data sequence to be decoded with the length of N multiplied by Z according to the basic check matrix and the spreading factor Z to obtain a decoding bit sequence with the length of (N-M) multiplied by Z bits.

Optionally, the basic check matrix has two code rate thresholds: r0 and R1, wherein R0 is a real number greater than 0 and less than 1, and R1 is a real number greater than R0 and less than 1; wherein the code rate is a code rate supported by a basic check matrix formed by all rows and all columns in the basic check matrix corresponding to R0, where R0= (N-M)/N; the code rate is a code rate supported by a first basic check matrix formed by a 0- (M2-1) th row and a 0- (N2-1) th column in the basic check matrix, wherein R1= (N2-M2)/N2; wherein M2 is an integer greater than 0 and N2 is an integer greater than M2.

Optionally, performing polygonal-type structured LDPC coding according to the basic check matrix and the spreading factor Z to obtain a polygonal-type structured LDPC code sequence, including one of the following manners:

performing polygonal type structured LDPC coding with a code rate of R0 by using the basic check matrix to obtain a second polygonal type structured LDPC code bit sequence, and obtaining the polygonal type structured LDPC code sequence from the second polygonal type structured LDPC code bit sequence by an expansion method;

coding by adopting a sub-base check matrix formed by the 0- (M3-1) th row and the 0- (N3-1) th column in the base check matrix to obtain the multilateral type structured LDPC code sequence, wherein M3 and N3 are integers larger than 0, and M3 is less than N3;

and performing polygonal type structured LDPC coding by adopting the first basic check matrix to obtain a first polygonal type structured LDPC code bit sequence, wherein the polygonal type structured LDPC code sequence is a subset sequence of the first polygonal type structured LDPC code bit sequence.

Optionally, the obtaining the code sequence of the second structured LDPC code by using an extension method includes one of the following manners:

dividing the second polygonal-type structured LDPC code bit sequence into multiple subsequences, selecting F groups of subsequences from the multiple subsequences, wherein each group of subsequences at least comprises 2 subsequences, performing binary addition on bits at corresponding positions of all subsequences in each group of subsequences respectively to obtain a first extended bit sequence formed by the F parts of bit sequences, and a subset sequence of the second polygonal-type structured LDPC code bit sequence and a subset sequence of the first extended bit sequence form the polygonal-type structured LDPC code sequence, wherein F is an integer greater than 0;

repeating G times to a second polygonal type structured LDPC code bit sequence to obtain a second spreading bit sequence, wherein a subset sequence of the second spreading bit sequence constitutes the polygonal type structured LDPC code sequence, and G is an integer greater than 1.

Optionally, the parameters M3 and N3 satisfy (N3-M3)/N3 ≦ R, where R is a code rate of the polygonal-type structured LDPC code sequence, and R is a real number greater than 0 and less than 1.

According to another embodiment of the present invention, there is provided a polygonal-type structured LDPC processing apparatus including: the device comprises a determining module, a calculating module and a calculating module, wherein the determining module is used for determining a basic check matrix and an expansion factor Z, the basic check matrix comprises at least one of a first type element and a second type element and a third type element, the first type element corresponds to a Z multiplied by Z all-zero matrix, the second type element corresponds to a matrix obtained by circularly right shifting a Z multiplied by Z unit matrix by corresponding 1 shift value, and the third type element corresponds to a matrix obtained by adding all matrixes obtained by circularly right shifting the Z multiplied by Z unit matrix by corresponding at least 2 shift values; the difference value of any 2 shift values in all the shift values of the third type elements is an integral multiple of a parameter B, wherein the parameter B is a positive integer factor of an expansion factor Z, and Z is a positive integer; and the processing module is used for carrying out polygonal type structured low-density parity check (LDPC) coding or polygonal type structured LDPC decoding according to the basic check matrix and the expansion factor Z.

Optionally, the parameter P is selected in one of the following manners:

selecting according to the pre-convention of the encoding end and the decoding end;

selecting according to the indication of the signaling sent from the decoding end to the encoding end;

the selection is made according to system predefined settings.

Optionally, the basic check matrix is a basic check matrix with M rows and N columns, and includes: the system matrix block C0 is formed by M x (N-M) system matrix blocks C0 formed by (N-M) columns and the check matrix block C1 is formed by M x M columns, wherein at least 1 third type element is arranged in the check matrix block C1, a sub-matrix C2 in the check matrix block C1 is of a dual diagonal structure, and the number of all shift values in the sub-matrix C2 is an odd number.

Optionally, the sub-matrix C2 includes 1 odd column and M0-1 even column, where the odd column is only an odd shift value in the column, and the even column is only an even shift value in the column.

Optionally, the processing module comprises: the encoding unit is used for encoding a source sequence to be encoded with (N-M) xZ bits according to the basic check matrix and the spreading factor Z to obtain an LDPC codeword sequence with the length of N x Z bits; and/or the decoding unit is used for decoding the data sequence to be decoded with the length of NxZ according to the basic check matrix and the spreading factor Z to obtain a decoding bit sequence with the length of (N-M) xZ bits.

According to still another embodiment of the present invention, there is also provided a storage medium. The storage medium is configured to store program code for performing the steps of:

determining a basic check matrix and a spreading factor Z, wherein the basic check matrix comprises at least one of a first type of elements, a second type of elements and a third type of elements, the first type of elements correspond to a Z multiplied by Z all-zero matrix, the second type of elements correspond to a matrix obtained by circularly right shifting a Z multiplied by Z unit matrix by corresponding 1 shift value, and the third type of elements correspond to a matrix obtained by adding all matrices obtained by circularly right shifting the Z multiplied by Z unit matrix by corresponding at least 2 shift values respectively; the difference value of any 2 shift values in all the shift values of the third type elements is an integral multiple of a parameter B, wherein the parameter B is a positive integer factor of an expansion factor Z, and Z is a positive integer;

performing polygonal type structured low-density parity check (LDPC) coding or polygonal type structured LDPC decoding according to the basic check matrix and the expansion factor Z

According to the invention, in the basic check matrix adopted by the multilateral structured LDPC code, a plurality of shift values belonging to the third type elements have a certain relation, so that the multilateral structured LDPC code can access data and read simultaneously during decoding without additional hardware, and the problems of increased decoding hardware and low decoding speed of the multilateral structured LDPC code due to increased column weight and multiple elements are solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention and do not constitute a limitation of the invention. In the drawings:

FIG. 1 is a flow diagram of a method of polygonal-type structured LDPC processing according to an embodiment of the present invention;

FIG. 2 is a block diagram of the structure of a polygonal-type structured LDPC encoding apparatus according to an embodiment of the present invention;

FIG. 3 is a block diagram of an alternative structure of a polygonal-type structured LDPC encoding apparatus according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a basic check matrix of a structured LDPC code of a multi-edge type in example 1 of the present invention;

FIG. 5 is a schematic diagram of data address storage within 1 spreading factor Z =12 for a multi-edge structured LDPC code in example 1 of the present invention;

FIG. 6 is a schematic diagram of a basic check matrix of a structured LDPC code of a multi-edge type in example 2 of the present invention;

FIG. 7 is a schematic diagram of the basic check matrix of the structured LDPC code of the multi-edge type in example 3 of the present invention.

Detailed Description

The invention will be described in detail hereinafter with reference to the drawings and embodiments. It should be noted that, in the present application, the embodiments and features of the embodiments may be combined with each other without conflict.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

Example 1

In this embodiment, a method for processing a structured LDPC of a multi-edge type is provided, and fig. 1 is a flowchart of the method for processing a structured LDPC of a multi-edge type according to an embodiment of the present invention, as shown in fig. 1, the flowchart includes the following steps:

step S102, determining a basic check matrix and an expansion factor Z, wherein the basic check matrix comprises at least one of a first type element and a second type element and a third type element, the first type element corresponds to a Z multiplied by Z all-zero matrix, the second type element corresponds to a matrix obtained by circularly right shifting a Z multiplied by Z unit matrix by corresponding 1 shift value, and the third type element corresponds to a matrix obtained by adding all matrices obtained by respectively circularly right shifting the Z multiplied by Z unit matrix by corresponding at least 2 shift values; the difference value of any 2 shift values in all the shift values of the third type element is integral multiple of a parameter B, the parameter B is a positive integer factor of an expansion factor Z, and Z is a positive integer;

and step S104, performing polygonal type structured low-density parity check (LDPC) coding or polygonal type structured LDPC decoding according to the basic check matrix and the expansion factor Z.

Through the steps, in a basic check matrix adopted by the polygonal type structured LDPC code, a plurality of shift values belonging to the third type elements have a certain relation, so that the data can be accessed and read simultaneously when the polygonal type structured LDPC code is decoded, no additional hardware is needed, and the problems of decoding hardware increase and low decoding speed caused by column weight increase and multiple elements of the polygonal type LDPC code are solved.

Alternatively, the main body for performing the above steps may be a transmitter, a receiver, such as a base station, a terminal, etc., but is not limited thereto.

Optionally, the parameter B is equal to an integer value obtained by dividing the expansion factor Z by a parameter P, where the parameter P is a decoding parallelism in the polygonal-type structured LDPC decoding, the decoding parallelism indicates that P parity check codes are updated simultaneously in the polygonal-type structured LDPC decoding, and the parameter P is a positive integer factor of the expansion factor Z.

Optionally, the parameter P is selected (or predefined) in one of the following ways: selecting according to the pre-convention of the encoding end and the decoding end; selecting according to the indication of the signaling sent from the coding end to the decoding end; selecting according to the indication of the signaling sent from the decoding end to the encoding end; the selection is made according to system predefined settings.

Optionally, in the basic check matrix, a specific value of the first type element is represented by a null value or-1, and a shift value of the second type element and the third type element is an integer greater than or equal to 0 and less than Z.

Optionally, the sub-matrix C2 is a matrix formed by rows 0 to M0-1 and columns 0 to M0-1 in the check matrix block C1, where M0 is an integer greater than 1 and less than or equal to M. The sub-matrix C2 includes 1 odd column and M0-1 even columns, wherein the odd column is only odd shift values in the columns, and the even column is only even shift values in the columns. Specifically, the number of any shift value in all the shift values of the odd-numbered columns is an even number except 1 shift value, and/or the number of any shift value in all the shift values of the even-numbered columns is an even number.

In a specific implementation manner according to this embodiment, performing the polygonal-type structured LDPC encoding or the polygonal-type structured LDPC decoding according to the base check matrix and the spreading factor Z includes:

coding a source sequence to be coded with the length of (N-M) multiplied by Z bits according to a basic check matrix and a spreading factor Z to obtain an LDPC codeword sequence with the length of Nmultiplied by Z bits;

and decoding the data sequence to be decoded with the length of NxZ according to the basic check matrix and the spreading factor Z to obtain a decoding bit sequence with the length of (N-M) xZ bits.

Optionally, the basic check matrix has two code rate thresholds: r0 and R1, wherein R0 is a real number greater than 0 and less than 1, and R1 is a real number greater than R0 and less than 1; wherein the code rate is a code rate supported by a basic check matrix formed by all rows and all columns in the basic check matrix, where R0= (N-M)/N; the code rate is a code rate supported by a first basic check matrix formed by a 0- (M2-1) th row and a 0- (N2-1) th column in the basic check matrix, wherein R1= (N2-M2)/N2; wherein M2 is an integer greater than 0 and N2 is an integer greater than M2.

Optionally, performing a polygonal-type structured LDPC coding according to the basic check matrix and the spreading factor Z to obtain a polygonal-type structured LDPC code sequence, specifically including one of the following modes:

Optionally, the obtaining the polygonal-type structured LDPC code sequence by the second polygonal-type structured LDPC code bit sequence through an extension method specifically includes one of the following manners:

repeating the bit sequence of the second polygon type structured LDPC code by G times to obtain a second spreading bit sequence, wherein a subset sequence of the second spreading bit sequence constitutes the code sequence of the polygon type structured LDPC code, and G is an integer greater than 1.

Optionally, the parameters M3 and N3 satisfy (N3-M3)/N3 ≦ R, where R is a code rate of the polygonal-type structured LDPC code sequence, and R is a real number greater than 0 and smaller than 1.

Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention or portions thereof contributing to the prior art may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (which may be a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.

Example 2

In this embodiment, a multi-edge structured LDPC encoding apparatus is further provided, and the apparatus is used to implement the foregoing embodiments and preferred embodiments, and the description of the apparatus is omitted. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware or a combination of software and hardware is also possible and contemplated.

Fig. 2 is a block diagram of a structure of a multi-edge type structured LDPC encoding apparatus according to an embodiment of the present invention, as shown in fig. 2, the apparatus including:

a determining module 20, configured to determine a basic check matrix and an expansion factor Z, where the basic check matrix includes at least one of a first type element and a second type element, and a third type element, where the first type element corresponds to a Z × Z all-zero matrix, the second type element corresponds to a matrix obtained by cyclically shifting a Z × Z unit matrix by 1 shift value, and the third type element corresponds to a matrix obtained by adding all matrices obtained by cyclically shifting a Z × Z unit matrix by at least 2 shift values; the difference value of any 2 shift values in all the shift values of the third type element is integral multiple of a parameter B, the parameter B is a positive integer factor of an expansion factor Z, and Z is a positive integer;

and the processing module 22 is configured to perform polygonal type structured low density parity check LDPC encoding or polygonal type structured LDPC decoding according to the basic check matrix and the spreading factor Z.

Optionally, the parameter B is equal to an integer value obtained by dividing the expansion factor Z by a parameter P, where the parameter P is a decoding parallelism in the polygonal-type structured LDPC decoding, the decoding parallelism is that P represents that P parity check codes are updated simultaneously in the polygonal-type structured LDPC decoding, and the parameter P is a positive integer factor of the expansion factor Z.

Optionally, the parameter P is selected (or predefined) in one of the following ways: selecting according to the prearranged convention of the encoding end and the decoding end; selecting according to the indication of the signaling sent from the coding end to the decoding end; selecting according to the instruction of the signaling sent from the decoding end to the encoding end; the selection is made according to system predefined settings.

Optionally, in the basic check matrix, the specific value of the first type element is represented by a null value or-1, and the shift value of the second type element and the third type element is an integer greater than or equal to 0 and less than Z.

Optionally, the sub-matrix C2 is a matrix formed by rows 0 to M0-1 and columns 0 to M0-1 in the check matrix block C1, where M0 is an integer greater than 1 and less than or equal to M. The sub-matrix C2 includes 1 odd column and M0-1 even columns, wherein the odd column is only odd shift values in the columns, and the even column is only even shift values in the columns. Specifically, the number of any shift value in all the shift values of the odd columns is an even number except 1 shift value, and/or the number of any shift value in all the shift values of the even columns is an even number.

Optionally, the basic check matrix has two code rate thresholds: r0 and R1, wherein R0 is a real number greater than 0 and less than 1, and R1 is a real number greater than R0 and less than 1; wherein the code rate is a code rate supported by a basic check matrix formed by all rows and all columns in the basic check matrix corresponding to R0, where R0= (N-M)/N; the code rate is a code rate supported by a first basic check matrix composed of a 0- (M2-1) th row and a 0- (N2-1) th column in the basic check matrix, where R1= (N2-M2)/N2; wherein M2 is an integer greater than 0 and N2 is an integer greater than M2.

dividing the second polygonal type structured LDPC code bit sequence into multiple subsequences, selecting F groups of subsequences from the multiple subsequences, wherein each group of subsequences at least comprises 2 subsequences, binary adding is performed on bits at corresponding positions of all subsequences in each group of subsequences respectively to obtain a first extended bit sequence formed by the F parts of bit sequences, one subset sequence of the second polygonal type structured LDPC code bit sequence and one subset sequence of the first extended bit sequence form the polygonal type structured LDPC code sequence, and F is an integer larger than 0;

Fig. 3 is a block diagram of an alternative structure of the multi-edge type structured LDPC encoding apparatus according to an embodiment of the present invention, as shown in fig. 3, the apparatus includes, in addition to all the modules shown in fig. 2, a processing module 22 including:

the encoding unit 30 is configured to encode the source sequence to be encoded with (N-M) × Z bits according to the basic check matrix and the spreading factor Z to obtain an LDPC codeword sequence with nxz bits;

the decoding unit 32 is configured to decode the data sequence to be decoded with the length of nxz according to the basic check matrix and the spreading factor Z to obtain a decoded bit sequence with the length of (N-M) × Z bits.

It should be noted that the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are located in different processors in any combination.

Example 3

The embodiment is an optional embodiment according to the present invention, and is used for explaining the present application in detail by combining with a specific scenario, and includes a plurality of specific examples:

example 1

The method provided in the optional example of the present invention may be used in an LTE mobile communication system or a future fifth generation mobile communication system or other wireless and wired communication systems, where the data transmission direction is that a base station sends data to a mobile user (downlink transmission service data), or the data transmission direction is that a mobile user sends data to a base station (uplink transmission service data). The mobile user comprises: a mobile device, as an access terminal, user terminal, subscriber station, subscriber unit, mobile station, remote terminal, user agent, user device, user equipment, or some other terminology. The base station includes an Access Point (AP), or may be referred to as a Node B, a Radio Network Controller (RNC), an Evolved Node B (eNB), a Base Station Controller (BSC), a Base Transceiver Station (BTS), a Base Station (BS), a Transceiver Function (TF), a radio router, a radio transceiver, a basic service set (BSs), an Extended Service Set (ESS), a Radio Base Station (RBS), or some other terminology.

According to an aspect of this optional example of the present invention, this optional example provides a method for constructing a multi-edge structured LDPC code, which is applied to an enhanced Mobile Broadband (eMBB) scenario, an Ultra-Reliable and Low Latency Communications (URLLC) scenario, or an mtc (massive Machine Type Communications, internet of things) scenario in a New RAT (New Radio Access Technology). The maximum downlink throughput in the eMBB scene can reach 20Gbps, and the maximum uplink data throughput can reach 10Gbps; in URLLC, the BLER (Block Error Rate) with the lowest reliability reaching 10e-5 and the shortest time delay of uplink and downlink reaching 0.5 millisecond can be supported; and mtc enables the device battery to be used for years without powering down.

The embodiment is mainly used for a receiving decoding end, and a data sequence to be decoded is decoded according to a basic check matrix and a spreading factor Z of the polygonal structured LDPC code to obtain a decoding bit sequence. Assuming that the length of a source sequence to be coded transmitted by a transmitting end is 60 bits, the code rate of channel coding is 5/12, the channel coding adopts a polygonal structured LDPC code, and the LDPC code obtains an LDPC code word of 144 bits. Fig. 4 is a schematic diagram of a basic check matrix of the multi-edge structured LDPC code in example 1 of the present invention, where the basic check matrix of the multi-edge structured LDPC code is as shown in fig. 4, and parameters of the basic check matrix are: the number of matrix rows is M =7, the number of matrix columns is N =12, and the spreading factor is Z =12. As can be seen from fig. 4, the provided basic check matrix includes: d0=56 elements of the first class, D1=25 elements of the second class and D2=3 elements of the third class. Wherein the first type element is represented by-1, as 501 in the figure, corresponding to an all-zero matrix with size Z × Z =12 × 12, as 504 in the figure; only 1 shift value in the second type element, 500 as shown in the figure, the size of the shift value being greater than or equal to 0 and less than an integer of Z =12, corresponds to a matrix obtained by cyclically shifting 1Z × Z unit array by 1 shift value, 500 as shown in fig. 4 has a shift value equal to 0, so it corresponds to a unit array cyclically shifted by 0, so it is also a unit array, 503 as shown in fig. 4; the third kind of element has at least 2 shift values, corresponding to the matrix obtained by adding all the matrices circularly right-shifted by the unit matrix with Z × Z =12 × 12 corresponding to the at least 2 shift values, in this example, the third kind of element includes 2 shift values, such as 502 in the figure, including 2 shift values [5,9], and the corresponding matrix is 505 in fig. 4; the other elements of the first type, the second type and the third type are not described in detail here. The basic check matrix is expanded, that is, the first type elements, the second type elements and the third type elements in the basic check matrix are respectively replaced by corresponding matrixes, so that a parity check matrix H with dimensions of M × Z =7 × 12=84 rows and N × Z =12 × 12=144 columns can be obtained.

According to the basic check matrix of the multi-edge structured LDPC code, it can be seen that there are 3 third-type elements in the basic check matrix, as follows: [5,9], [4,8] and [0,4]. In all shift values of the third type element of the M rows and N columns of the basic check matrix, a difference value of any 2 shift values is an integer multiple of a parameter B, where the parameter B is a positive integer factor with a spreading factor Z =12, and in this example, the parameter B =4; the 2 shift values of the 3 third type elements are [5,9], [4,8] and [0,4], and their differences are-4, -4 and 4, which are all integer multiples of B = 4.

According to the above-mentioned parameter B =4, and the parameter B is equal to the integer value obtained by dividing the spreading factor Z by the parameter P, it is known that the decoding parallelism of the polygonal structured LDPC code is P =3. That is, in the layered decoding of the LDPC code, P =3 parity check codes or check equations may be updated simultaneously each time, that is, an update algorithm or module for P =3 parity check codes operates simultaneously; fig. 5 is a schematic diagram of data address storage in 1 spreading factor Z =12 of a multi-edge structured LDPC code in example 1 of the present invention, and in the example of fig. 5, 1 spreading factor Z =12 is used for explanation, since the parallelism P =3, B =4 storage blocks are included in 1 spreading factor Z =12, and if the corresponding shift value in fig. 5 (a) is 0, the first read 3 variable bits are 0,4, and 8 soft information, each variable information is used for updating 1 parity check code, and since the 0,4, and 8 soft information are all read at the same time and updated at the same time, the 0,4, and 8 soft information may exist in the same address space, which is called word0, and if each variable soft information is quantized with 8 bits, the size of word0 is 3 × 8=24 bits; similarly, the other variables within 1 spreading factor Z =12 constitute another 3 words, as shown in fig. 5 (a), word1 being [ 15 ], word2 being [2 6 ], word3 being [3 7 11]; when data is updated, reading in sequence according to element values in the basic check matrix, and if the shift value is 0, reading in sequence according to word0, word1, word2 and word 3; if the shift value is equal to 5, as in 601 in FIG. 5 (b), then the read order is word1, word2, word3, word0 first. From the above, in word0, word1, word2, and word3, no matter how many shift values are, the soft information of 0,4, and 8 always exists in word0, and only needs to be slightly interleaved during reading. If the basic check matrix has the third kind of elements, that is, at least 2 shift values, the line connection of the decoder is very complicated if data needs to be read from different word, and the decoding complexity is high, while if data is read from the same word, the complexity of the decoder can be greatly reduced. As shown in fig. 5 (a), the shift value is 0, if there are other shift values, only 4 and 8 can be selected, so that the soft information can be read from the same word, that is, the rule is satisfied: the difference of any 2 shift values is an integer multiple of the parameter B =4 or is divisible by the parameter B = 4. As in fig. 5 (B), the element (belonging to the third category of elements) corresponding to row 3 and column 0 of the basic check matrix shown in fig. 4 contains 2 shift values [5,9], and it can be seen that the difference value of the 2 shift values can be divided by the parameter B =4, i.e. 1 or-1 times of B =4, so as to be seen from fig. 5 (B), the reading order is word1, word2, word3, word0 first. Therefore, even if the third-class element contains a plurality of shift values, the third-class element can read data from the same memory word block, and in the other 2 third-class elements, because 2 of the shift values also satisfy the above rule, the data read from the P =3 parity codes in each group are all read from the same memory word and the sequence is the same, thereby being beneficial to reducing the complexity of a decoder and reducing the area and the power consumption of the decoder.

According to the invention, the multilateral structured LDPC decoding method is provided, which comprises the following steps:

s700, receiving and demodulating 144 soft information of the LDPC code word;

s701, determining M rows and N columns of basic check matrixes and expansion factors Z used by the multi-edge structured LDPC coding. The basic check matrix of the multi-edge structured LDPC code is shown in FIG. 4, and the spreading factor Z =12. In all shift values of all third type elements of the M rows and N columns of basic check matrix, a difference value of any 2 shift values is an integer multiple of a parameter B =4, and the parameter B is a positive integer factor of a spreading factor Z =12.

S702, decoding a data sequence to be decoded (144 soft information) with a length of N × Z =12 × 12=144 according to the basic check matrix and the spreading factor Z =12 to obtain a decoded bit sequence with a length of (N-M) × Z = (12-7) × 12=60 bits; wherein, the decoding structure is adopted, and the decoding parallelism P =3.

Example 2

The method proposed in this alternative example of the present invention may be used in a fifth generation mobile communication system or other wireless and wired communication systems, where the data transmission direction is that the base station sends data to the mobile subscriber (downlink transmission service data), or the data transmission direction is that the mobile subscriber sends data to the base station (uplink transmission service data). The embodiment is used for a transmitting end, an information source sequence with the length of 3000 bits needs to be transmitted, and the information source sequence is subjected to LDPC coding with the 3/4 code rate to obtain the multilateral structured LDPC coding with the length of 4000. Wherein, the spreading factor Z =250 of the structured LDPC code of the polygon type, fig. 6 is a schematic diagram of a basic check matrix of the structured LDPC code of the polygon type in example 2 of the present invention, and the basic check matrix is as shown in fig. 6. It can be seen that D2=5 third class elements are included, each having a 2-shift value, wherein all of said third class elements satisfy: the difference of any 2 shift values in all shift values of all third-class elements of the M =4 rows and N =16 columns of the basic check matrix is an integer multiple of the parameter B =10, and the parameter B =10 is a positive integer factor of the spreading factor Z = 250. Therefore, by adopting the LDPC code basic check matrix, a receiving decoding end can adopt a decoder structure similar to that in the example 1, and the decoder has the advantages of reducing the decoding complexity, and reducing the chip area and power consumption.

According to the invention, the method for encoding the multi-edge structured LDPC comprises the following steps:

s800, acquiring an information source sequence to be coded, wherein the length of the information source sequence is 3000 bits;

s801, determining a basic check matrix of M =4 rows and N =16 columns used by the multilateral structured LDPC coding, and a spreading factor Z =250, wherein the basic check matrix includes, as described above, D0=6 first-type elements corresponding to a full zero matrix of Z × Z =250 × 250, D1=53 second-type elements corresponding to a matrix obtained by cyclically right-shifting a unit matrix of Z × Z =250 × 250 by 1 shift value corresponding to the 1 shift value, and D2=5 third-type elements having at least 2 shift values corresponding to a matrix obtained by cyclically right-shifting a unit matrix of Z × Z =250 × 250 by all matrices obtained by cyclically adding all matrices obtained by cyclically right-shifting the unit matrix by the at least 2 shift values, respectively, wherein the shift values are integers greater than or equal to 0 and less than Z = 250; replacing the first type elements, the second type elements and the third type elements of the basic check matrix into corresponding matrixes to obtain a parity check matrix of the polygonal structured LDPC code; the method is characterized in that, of all shift values of all third-class elements of the M =4 rows and N =16 columns of basic check matrix, a difference value of any 2 shift values is an integer multiple of a parameter B =10, the parameter B =10 is a positive integer factor of an expansion factor Z =250, a parallelism of the LDPC decoder may be P =25, and a product of the parameter B and a decoding parallelism P is equal to the expansion factor Z;

s802, coding a source sequence to be coded with the length of (N-M) xZ =3000 bits according to a basic check matrix and a spreading factor Z of the polygonal structured LDPC code to obtain an LDPC codeword sequence with the length of N x Z =4000 bits;

and S803, modulating the LDPC codeword sequence and transmitting.

Example 3

The difference between the example and the example 2 lies in the basic check matrix of the multi-edge structured LDPC code and the length of the encoded data, in the example, the information length is 2000 bits, the code rate is 1/2, and the length of the LDPC code word after encoding is 4000 bits. The basic check matrix may also have the following new characteristics: the M rows and N columns of basic check matrix comprise M x (N-M) matrix blocks C0 and M x M matrix blocks C1, and at least 1 third type element is arranged in the matrix blocks C1, if a sub-matrix C2 in the matrix blocks C1 is in a dual diagonal structure, the number of all shift values in the sub-matrix C2 is an odd number. The submatrix C2 is a matrix formed from 0 th to M0-1 th rows and from 0 th to M0-1 th columns in the matrix block C1, where M0 is an integer greater than 1 and less than or equal to M. In the sub-matrix C2, there are 1 odd column and M0-1 even column, wherein the odd column is only odd shift value in the column, and the even column is only even shift value in the column. In the odd columns, all the shift values except 1 are equal in pairs; in the even columns, all shift values are equal two by two.

The basic check matrix of the polygonal structured LDPC code adopted in the embodiment is 8 rows and 16 columns, the expansion factor Z =250, namely the code rate adopts 1/2, and the LDPC code word with the length of 4000 bits can be obtained by polygonal structured LDPC coding of 2000 bits. The coding parallelism assumed is consistent with example 2, P =25, then the parameter B is a positive integer factor of the spreading factor Z =250 and is equal to the spreading factor Z =250 divided by the parallelism P =25, so the parameter B =10 can be known. Fig. 7 is a schematic diagram of a basic check matrix of the structured LDPC code of the multi-edge type in example 3 of the present invention, and the basic check matrix used in this example is shown in fig. 7.

The basic check matrix of the multi-edge structured LDPC code shown in fig. 7 has M =8, n =16, an extension factor of 250, and a code rate of 1/2. It can be known that the number of systematic bits supported by the multi-edge structured LDPC code is 8 × 250=2000, and an LDPC codeword having a length of 4000 bits can be obtained after performing multi-edge structured LDPC encoding. As can be seen from the basic check matrix, D2=6 third-class elements are included. The base check matrix includes 2 partial matrix blocks C0 and C1, where the matrix block C0 corresponds to a matrix of system bit portions, a matrix of the top K = N-M =16-8=8 columns, and a dimension size of M × (N-M) =8 × 8, as 802 in fig. 7; the matrix block C1 corresponds to a matrix of the parity bit part, and has a dimension size of M × M =8 × 8 in the last M =8 columns of the basic parity check matrix, as shown in 803 in fig. 7. Also, in the matrix block C1, 1 sub-matrix C2 is further included, as shown in 800 of fig. 7, the sub-matrix C2 is a matrix formed by rows 0 to M0-1=4 and columns 0 to M0-1=4 in the matrix block C1, i.e., M0=5, and the sub-matrix C2 is a matrix of M0 × M0=5 × 5. It can be seen that the sub-matrix C2 is a dual diagonal structure, i.e. the dual diagonal structure satisfies: 1. no element value with index [ i, i ] is equal to-1,i= -0,1, \8230, (M0-1); 2. no element value with index [ i, i +1] is equal to-1, i =0,1, \ 8230, (M0-2); 3. the values of the elements with indices [ i, j ] are all equal to-1, where j > i +1, i =0,1, \8230; (M0-3). Wherein, the-1 is an all-zero matrix used for indicating the parity check matrix of the LDPC code in the basic check matrix, and can also be represented by other null values or negative numbers. It can be seen that the sub-matrix C2 with a double diagonal structure contains odd number of shift values, i.e. 11 shift values, and also contains 1 odd column and M0-1=4 even columns, where the odd column is only odd number of shift values in the columns, as in the sub-matrix 800 shown in fig. 7, only the 0 th column (in the 8 th column of the basic check matrix) contains 3 shift values, and the even column is only even number of shift values in the columns, as in all the columns from the 1 st column to the 4 th column in the sub-matrix 800 in fig. 7, contains 2 shift values. In the odd columns, all the shift values except 1 are equal in pairs; in the even columns, all shift values are equal two by two.

The beneficial effects of the operation are as follows: the matrix is convenient to encode, and the check bit can be calculated by directly adopting the characteristics of the basic check matrix. As shown in the basic check matrix of fig. 7, it can be seen that from row 0 to row M0=4, each check equation includes 2 bits of check bits because the check partial matrix (i.e., the sub-matrix 800) has a dual diagonal structure, so that the encoding cannot be performed simply in a time-varying manner, i.e., one check bit is directly calculated. However, since the sub-matrix 800 in this example has some characteristics: the elements on the columns are equal in pairs, the parity bits which are equal in pairs can be cancelled by performing an overall exclusive-or on the calculation result of the system part, the parity bits which are equal in pairs are left in the odd columns, and the 0 th parity vector can be calculated, wherein the size of the 0 th parity vector is Z =250 bits, and corresponds to all bits in the 8 th column of the basic check matrix shown in fig. 7, and when all the parity bits in the 8 th column are known, the parity vectors in the 9 th, 10 th, \8230, and 15 th columns can be sequentially solved. Therefore, the basic check matrix characteristic of the multi-edge structured LDPC code enables the LDPC coding to be simpler, more convenient and faster, the basic check matrix does not need to be expanded into a parity check matrix and then inverse operation is carried out, the coding algorithm of the method is very complex, and the time delay is large, so that the method is not beneficial to high-speed data transmission.

Example 4

The embodiment of the invention also provides a storage medium. Alternatively, in the present embodiment, the storage medium may be configured to store program codes for performing the following steps:

s1, determining a basic check matrix and an expansion factor Z, wherein the basic check matrix comprises a first type element, a second type element and a third type element, the first type element corresponds to a Z multiplied by Z all-zero matrix, the second type element corresponds to a matrix obtained by circularly right shifting a Z multiplied by Z unit matrix by corresponding 1 shift value, and the third type element corresponds to a matrix obtained by adding all matrices obtained by respectively circularly right shifting the Z multiplied by Z unit matrix by corresponding at least 2 shift values; the difference value of any 2 shift values in all the shift values of the third type element is integral multiple of a parameter B, the parameter B is a positive integer factor of an expansion factor Z, and Z is a positive integer;

and S2, performing polygonal type structured low-density parity check (LDPC) coding or polygonal type structured LDPC decoding according to the basic check matrix and the expansion factor Z.

Optionally, in this embodiment, the storage medium may include, but is not limited to: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk, and various media capable of storing program codes.

Optionally, in this embodiment, the processor performs determining a basic check matrix and a spreading factor Z according to a program code stored in the storage medium, where the basic check matrix includes a first type element, a second type element, and a third type element, where the first type element corresponds to a Z × Z all-zero matrix, the second type element corresponds to a matrix obtained by cyclically shifting a Z × Z unit matrix to the right by 1 shift value, and the third type element corresponds to a matrix obtained by adding all matrices obtained by cyclically shifting a Z × Z unit matrix to the right by at least 2 shift values; the difference value of any 2 shift values in all the shift values of the third type element is integral multiple of a parameter B, the parameter B is a positive integer factor of an expansion factor Z, and Z is a positive integer;

alternatively, in the present embodiment, the processor performs the polygonal-type structured low density parity check LDPC encoding or the polygonal-type structured LDPC decoding according to the base check matrix and the spreading factor Z, according to the program code already stored in the storage medium.

Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.

It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for processing structured LDPC with multilateral types is characterized by comprising the following steps:

determining a basic check matrix and a spreading factor Z, wherein the basic check matrix comprises at least one of a first type element and a second type element and a third type element, the first type element corresponds to a Z x Z all-zero matrix, the second type element corresponds to a matrix obtained by circularly right shifting a Z x Z unit matrix by corresponding 1 shift value, and the third type element corresponds to a matrix obtained by adding all matrixes obtained by circularly right shifting the Z x Z unit matrix by corresponding at least 2 shift values; the difference value of any 2 shift values in all the shift values of the third type elements is an integral multiple of a parameter B, wherein the parameter B is a positive integer factor of an expansion factor Z, and Z is a positive integer;

and performing polygonal type structured low-density parity check (LDPC) coding or polygonal type structured LDPC decoding according to the basic check matrix and the expansion factor Z.

2. The method according to claim 1, wherein the parameter B is equal to an integer value obtained by dividing a spreading factor Z by a parameter P, wherein the parameter P is a coding parallelism in the polygonal-type structured LDPC coding, the coding parallelism is P representing that P parity check codes in the polygonal-type structured LDPC coding are updated simultaneously, and the parameter P is a positive integer.

3. The method according to claim 2, wherein the parameter P is selected in one of the following ways:

the selection is made according to system predefined settings.

4. The method of claim 1, wherein the specific value of the first type element in the basic check matrix is represented by a null value or by-1, and the shift values of the second type element and the third type element are integers greater than or equal to 0 and less than Z.

5. The method of claim 1, wherein the basic check matrix is a basic check matrix with M rows and N columns, and comprises: the system matrix block C0 of M x (N-M) formed by (N-M) columns and the check matrix block C1 of M x M formed by M columns, wherein at least 1 third-type element exists in the check matrix block C1, the sub-matrix C2 in the check matrix block C1 is in a dual diagonal structure, and the number of all shift values in the sub-matrix C2 is an odd number.

6. The method of claim 5, wherein the sub-matrix C2 is a matrix formed by rows 0 to M0-1 and columns 0 to M0-1 in the check matrix block C1, wherein M0 is an integer greater than 1 and less than or equal to M.

7. The method of claim 5, wherein the sub-matrix C2 comprises 1 odd column and M0-1 even column, wherein the odd column is only odd shift values in the columns, and the even column is only even shift values in the columns.

8. The method of claim 7, wherein the number of any of all the shift values of the odd columns is even except for 1 shift value, and/or the number of any of all the shift values of the even columns is even.

9. The method according to any one of claims 1 to 8, wherein the basic check matrix is a M-row N-column basic check matrix, comprising: d0 elements of the first type, D1 elements of the second type and D2 elements of the third type, M being a positive integer, N being an integer greater than M, D2 being a positive integer, D0 and D1 both being non-negative integers, D0+ D1+ D2 being less than or equal to mxn.

10. The method of claim 9, wherein performing polygonal-type structured LDPC encoding or polygonal-type structured LDPC decoding based on the base check matrix and a spreading factor Z comprises:

coding a source sequence to be coded with the length of (N-M) xZ bits according to the basic check matrix and the spreading factor Z to obtain an LDPC codeword sequence with the length of N x Z bits;

and decoding the data sequence to be decoded with the length of N multiplied by Z according to the basic check matrix and the spreading factor Z to obtain a decoding bit sequence with the length of (N-M) multiplied by Z bits.

11. The method of any of claims 1 to 8, wherein the base check matrix has two code rate thresholds: r0 and R1, wherein R0 is a real number greater than 0 and less than 1, and R1 is a real number greater than R0 and less than 1; wherein the code rate is a code rate supported by a basic check matrix formed by all rows and all columns in the basic check matrix, where R0= (N-M)/N; the code rate is a code rate supported by a first basic check matrix formed by 0 th to (M2-1) th rows and 0 th to (N2-1) th columns in the basic check matrix, wherein R1= (N2-M2)/N2; wherein M2 is an integer greater than 0 and N2 is an integer greater than M2.

12. The method of claim 11, wherein performing a multi-edge type structured LDPC coding according to the base check matrix and the spreading factor Z to obtain a multi-edge type structured LDPC code sequence comprises one of:

adopting the basic check matrix to carry out multilateral type structured LDPC coding with a code rate of R0 to obtain a second multilateral type structured LDPC code bit sequence, and obtaining the multilateral type structured LDPC code sequence by an expansion method for the second multilateral type structured LDPC code bit sequence;

coding by adopting a basic check matrix composed of 0 th to (M3-1) th rows and 0 th to (N3-1) th columns in the basic check matrix to obtain the polygonal type structured LDPC code sequence, wherein M3 and N3 are integers larger than 0, and M3 is less than N3;

13. The method of claim 12, wherein the obtaining the polygonal-type structured LDPC code sequence by a spreading method on the second polygonal-type structured LDPC code bit sequence comprises one of:

14. The method of claim 12, wherein the parameters M3 and N3 satisfy (N3-M3)/N3 ≦ R, wherein R is a code rate of the polygonal-type structured LDPC code sequence, and R is a real number greater than 0 and less than 1.

15. A polygonal-type structured LDPC processing apparatus characterized by comprising:

the device comprises a determining module, a calculating module and a calculating module, wherein the determining module is used for determining a basic check matrix and an expansion factor Z, the basic check matrix comprises at least one of a first type element and a second type element and a third type element, the first type element corresponds to a Z multiplied by Z all-zero matrix, the second type element corresponds to a matrix obtained by circularly right shifting a Z multiplied by Z unit matrix by corresponding 1 shift value, and the third type element corresponds to a matrix obtained by adding all matrixes obtained by circularly right shifting the Z multiplied by Z unit matrix by corresponding at least 2 shift values; the difference value of any 2 shift values in all the shift values of the third type element is an integral multiple of a parameter B, wherein the parameter B is a positive integer factor of an expansion factor Z, and Z is a positive integer;

and the processing module is used for carrying out polygonal type structured low-density parity check (LDPC) coding or polygonal type structured LDPC decoding according to the basic check matrix and the expansion factor Z.

16. The apparatus of claim 15, wherein the parameter B is equal to an integer value obtained by dividing a spreading factor Z by a parameter P, wherein the parameter P is a coding parallelism in the polygonal-type structured LDPC coding, wherein the coding parallelism is that P indicates that P parity check codes in the polygonal-type structured LDPC coding are updated simultaneously, and wherein the parameter P is a positive integer.

17. The apparatus of claim 16, wherein the parameter P is selected by one of:

the selection is made according to system predefined settings.

18. The apparatus of claim 15, wherein the specific value of the first type element in the basic check matrix is represented by a null value or-1, and the shift values of the second type element and the third type element are integers greater than or equal to 0 and less than Z.

19. The apparatus of claim 15, wherein the basic check matrix is an M-row and N-column basic check matrix, and wherein the apparatus comprises: the system matrix block C0 is formed by M x (N-M) system matrix blocks C0 formed by (N-M) columns and the check matrix block C1 is formed by M x M columns, wherein at least 1 third type element is arranged in the check matrix block C1, a sub-matrix C2 in the check matrix block C1 is of a dual diagonal structure, and the number of all shift values in the sub-matrix C2 is an odd number.

20. The apparatus of claim 19, wherein the submatrix C2 is a matrix formed by rows 0 to M0-1 and columns 0 to M0-1 in the check matrix block C1, and wherein M0 is an integer greater than 1 and less than or equal to M.

21. The apparatus of claim 19, wherein the sub-matrix C2 comprises 1 odd column and M0-1 even column, wherein the odd column is only an odd shift value in the column, and the even column is only an even shift value in the column.

22. The apparatus of claim 21, wherein the number of any of all the shift values of the odd columns is even except 1 shift value, and/or the number of any of all the shift values of the even columns is even.

23. The apparatus of any one of claims 15 to 22, wherein the basic check matrix is an M-row N-column basic check matrix, comprising: d0 elements of the first type, D1 elements of the second type and D2 elements of the third type, M being a positive integer, N being an integer greater than M, D2 being a positive integer, D0 and D1 both being non-negative integers, D0+ D1+ D2 being less than or equal to mxn.

24. The apparatus of claim 23, wherein the processing module comprises:

the encoding unit is used for encoding the source sequence to be encoded with the length of (N-M) xZ bits according to the basic check matrix and the spreading factor Z to obtain an LDPC codeword sequence with the length of NxZ bits; and/or the presence of a gas in the gas,

and the decoding unit is used for decoding the data sequence to be decoded with the length of NxZ according to the basic check matrix and the spreading factor Z to obtain a decoding bit sequence with the length of (N-M) xZ bits.