CN107709134B

CN107709134B - Electric car control device

Info

Publication number: CN107709134B
Application number: CN201680036053.6A
Authority: CN
Inventors: 关口孝公
Original assignee: Toshiba Corp; Toshiba Infrastructure Systems and Solutions Corp
Current assignee: Toshiba Corp; Toshiba Infrastructure Systems and Solutions Corp
Priority date: 2015-07-01
Filing date: 2016-06-13
Publication date: 2020-02-11
Anticipated expiration: 2036-06-13
Also published as: JP6563716B2; WO2017002601A1; CN107709134A; JP2017013649A

Abstract

The electric train control device according to the present embodiment includes an analog signal processing unit that processes an analog reception signal received by an antenna. The analog/digital conversion section converts the analog signal from the analog signal processing section into a digital signal. The digital signal processing section processes the digital signal. The control unit controls the electric train based on the digital signal from the digital signal processing unit. The test signal generating section supplies an analog test signal different in frequency or signal content from the analog received signal to the analog signal processing section.

Description

Electric car control device

Technical Field

An embodiment of the present invention relates to an electric vehicle control device.

Background

In order to safely run and stop an electric train used for a railway, various safety devices and operation support devices have been developed. For example, an automatic Train stop system (ats) and an automatic Train control system (atc) are known as safety devices. As the operation support devices, an Automatic operation device (ato) and a fixed position Stop device (TASC) are known.

The electric train control device in these safety devices and operation support devices collectively converts an analog signal received from the ground into a digital signal, and controls the electric train based on the digital signal. The receiving unit of such an electric train control device may be configured by a parallel dual system, so that it is possible to detect a failure when the failure occurs while ensuring the soundness of the receiving unit itself.

However, in the receiving section, the analog signal processing section is constituted by an analog element, and thus there is a difference in characteristics. Therefore, when the analog signal processing sections are provided as a parallel dual system, a difference occurs between signals processed by the two analog signal processing sections. Since such a characteristic difference of the analog element is not a failure, it is necessary to set a criterion for determining the soundness of the signal processing system to a criterion that allows the characteristic difference of the analog signal processing section. Thus, it is difficult to accurately determine the soundness of the signal processing system, and it is difficult to accurately detect a failure of the on-vehicle receiving unit.

In addition, a standby dual system may be used so that the electric train does not stop running even when the signal processing system fails. However, if both the standby dual system and the parallel dual system are applied to the on-vehicle receiving unit, a total of four signal processing systems are required. In this case, the size of the on-vehicle receiving portion becomes large, and the installation area thereof becomes large.

Documents of the prior art

Patent document

Patent document 1: japanese patent No. 5204205

Disclosure of Invention

Technical problem to be solved by the invention

The invention provides an electric car control device which can accurately detect the abnormity of a signal processing system and has small size.

Means for solving the technical problem

Drawings

Fig. 1 is a block diagram showing an example of the configuration of an electric train control device 1 (hereinafter, also referred to as a control device 1) according to the present embodiment.

Fig. 2 is a schematic diagram showing an example of the comparison and collation operation in the

control units

40a and 40 b.

Fig. 3 is a diagram showing an example of the relationship between the frequency band Scnt of the analog reception signal and the frequency band Stest of the analog test signal.

Fig. 4 is a diagram showing a pattern of an analog test signal.

Fig. 5 is a diagram showing another example of the pattern of the analog test signal.

Fig. 6 is a diagram showing a relationship between the frequency band Scnt of the analog received signal and the frequency band Stest of the analog test signal in the modification.

Fig. 7 is a diagram showing a pattern of a simulated test signal according to a modification.

Fig. 8 is a block diagram showing an example of the configuration of the electric train control device 2 according to the second embodiment.

Fig. 9 is a schematic diagram illustrating an example of the operation of the electric train control device according to the third embodiment.

Detailed Description

Embodiments according to the present invention will be described below with reference to the drawings. The present embodiment is not intended to limit the present invention.

Fig. 1 is a block diagram showing an example of the configuration of an electric train control device 1 (hereinafter, also referred to as a control device 1) according to the present embodiment. The control device 1 is mounted on an electric train such as a railway, receives a signal from a ground beacon via an antenna (for example, a vehicle-mounted beacon or a power receiver) 95, and inputs the signal to the control device 1 via a transformer 90. The control device 1 processes a signal from the ground beacon and outputs a control signal CNT. The control signal CNT is used to control the trolley.

The control device 1 includes an Analog signal processing unit 10, an Analog-to-digital converter (ADC) 20, digital

signal processing units

30a and 30b,

control units

40a and 40b, a test signal generating unit 50, and an adding unit 80. Although not shown, the control device 1 may be configured as a standby dual system. The standby dual system is configured to include a plurality of signal processing systems, and to switch to another signal processing system to perform signal processing when one signal processing system fails. Therefore, when the control device 1 is configured as a standby dual system, two signal processing systems from the analog signal processing unit 10 to the

control units

40a and 40b are connected in parallel.

The analog signal processing unit 10 performs analog processing (for example, amplification processing and filtering processing) on the analog reception signal received via the antenna 95 and the analog test signal from the test signal generating unit 50, and can digitally convert the analog reception signal received via the antenna 95 and the analog test signal from the test signal generating unit 50 in the analog-to-digital converter 20.

The analog-to-digital converter 20, which is an analog-to-digital conversion section, converts the analog reception signal and the analog test signal processed by the analog signal processing section 10 into digital signals.

The digital

signal processing units

30a and 30b each receive the digital signal from the analog-to-digital converter 20 and perform digital processing on the digital signal. For example, the digital

signal processing units

30a and 30b perform fourier transform on the digital signals, and convert the digital signals into frequency domains. Further, the digital

signal processing units

30a and 30b extract a signal level (signal intensity) at a certain frequency from the digital signal, and output the frequency and the signal level to the

control units

40a and 40 b. For example, the digital

signal processing units

30a and 30b transmit the resonant frequency at which the ground beacon is electromagnetically coupled to the antenna 95 and the signal level at the resonant frequency to the

control units

40a and 40b as digital control signals. Alternatively, the digital

signal processing units

30a and 30b transmit a predetermined frequency and a signal level at the frequency to the

control units

40a and 40b as digital test signals. The digital control signal is used to generate a control signal CNT for controlling the trolley. The digital test signal is used to confirm the soundness of the analog signal processing section 10 and the analog-to-digital converter 20. Soundness means that the device does not malfunction but operates normally. In addition, the digital control signal and the digital test signal are collectively referred to as a digital signal.

The

control units

40a and 40b generate the control signal CNT based on the frequency and the signal level received from the digital

signal processing units

30a and 30b, or confirm the soundness of the control device 1. The storage units 41a and 41b store reference patterns of normal digital test signals in advance. The reference pattern of the normal digital test signal is used to confirm the soundness of the analog signal processing unit 10 and the analog-to-digital converter 20, and includes a predetermined frequency and a predetermined signal level.

In the present embodiment, a plurality of digital

signal processing units

30a and 30b and

control units

40a and 40b for performing digital signal processing are provided, respectively, to constitute a parallel dual system. The parallel dual system connects two identical signal processing systems in parallel, and compares and collates (compares) signals processed by both signal processing systems. As a result of the comparison check, when both signals are equal, it can be confirmed that both signal processing systems are sound.

When the digital signal processing unit 30a and the control unit 40a are a first system and the digital signal processing unit 30b and the control unit 40b are a second system, the first system and the second system have the same configuration. That is, the digital

signal processing units

30a and 30b have the same configuration, and the

control units

40a and 40b have the same configuration. In addition, the first system and the second system receive the same digital signal. Therefore, in the case where both the first system and the second system are normal, the first system and the second system process the digital signal in the same manner and output the same control signal CNT. Therefore, the

control unit

40a or 40b compares (compares) the frequency and the signal level of the digital signal in the control unit 40a with the frequency and the signal level of the digital signal in the control unit 40 b. Thus, when the frequency and the signal level of the digital signal in the

control units

40a and 40b are substantially the same, it is known that both the first system and the second system are normal. When there is a large difference in the frequency and/or signal level of the digital signal in the

control units

40a and 40b, it is known that there is an abnormality in the first system or the second system. This allows the

control units

40a and 40b to check the soundness of the structure of the digital

signal processing units

30a and 30b and thereafter. Hereinafter, the digital

signal processing units

30a and 30b and the

control units

40a and 40b that perform digital signal processing are collectively referred to as a digital signal processing system.

On the other hand, the analog signal processing unit 10 and the analog-to-digital converter 20 that perform analog signal processing are not parallel dual systems, but are configured by one system. This is for equalizing the digital signals input to the digital

signal processing units

30a and 30 b.

When the analog signal processing unit 10 and the analog-to-digital converter 20 are also configured by a parallel dual system, a difference occurs between the two analog reception signals due to a characteristic difference of the analog element as described above. When there is a difference in the analog reception signal, a difference occurs in the timing of change of the digital control signal output from the analog-to-digital converter 20, or the like. In this case, the digital signals input to the digital

signal processing units

30a and 30b cannot be made identical, and it is difficult to accurately confirm the soundness of the digital signal processing system.

In contrast, in the present embodiment, since the analog signal processing unit 10 and the analog-to-digital converter 20 are configured by one system, the digital signals input to the digital

signal processing units

30a and 30b can be the same signal (common signal). Thus, the

control units

40a and 40b can accurately confirm the soundness of the digital signal processing system. Hereinafter, the analog signal processing unit 10 and the analog-to-digital converter 20 that perform analog signal processing are collectively referred to as an analog signal processing system.

The test signal generating section 50 receives a command from the

control section

40a or 40b, and outputs an analog test signal to the adder 80. The analog test signal is a signal for detecting a failure of the analog signal processing system, and is processed by the analog signal processing system and the digital signal processing system together with the analog reception signal.

The test signal generating section 50 includes a Digital test signal generating section 51, a Digital to analog converter (DAC) 52, and an analog test signal output section 53. The digital test signal generating section 51 receives a command from the

control section

40a or 40b and generates a digital test signal. The digital test signal is a signal whose predetermined level (signal intensity) is represented by a digital value at a predetermined frequency. The digital-to-analog converter 52 converts the digital test signal to analog and outputs an analog test signal. The analog test signal output unit 53 receives the analog test signal from the digital-to-analog converter 52, amplifies the analog test signal, and outputs the amplified analog test signal to the adder 80. The analog test signal is a signal having a predetermined level (signal intensity) at a predetermined frequency based on the digital test signal. The frequencies and signal levels of the digital test signal and the analog test signal are set in advance and stored in the

control units

40a and 40 b.

The adder 80 is provided between the transformer 90 and the input section of the analog signal processing section 10, and between the output of the test signal generating section 50 and the input section of the analog signal processing section 10. The adder 80 adds the analog test signal from the test signal generation unit 50 to the analog reception signal from the antenna 95, and outputs the result to the analog signal processing unit 10. Hereinafter, the analog reception signal and the analog test signal are collectively referred to as an analog signal. The analog signal is processed by an analog signal processing system and converted to a digital signal. At this time, the analog test signal and the analog reception signal are simultaneously processed without distinction and converted into a digital signal by the analog-to-digital converter 20. The digital signals are output to the digital

signal processing units

30a and 30 b. The digital

signal processing units

30a and 30b perform fourier transform on the digital signal to convert the digital signal into a frequency domain, and extract a digital control signal and a digital test signal from the digital signal.

The

control units

40a and 40b output the control signal CNT based on the digital control signal, and confirm the soundness of the analog signal processing system based on the digital test signal.

Here, confirmation of the soundness of the analog signal processing system will be described.

The characteristics of the analog signal processing section 10 and the gain and the like of the analog-to-digital converter 20 are known in advance. Therefore, when the analog signal processing system and the digital processing system operate normally, the digital test signal processed by the analog signal processing system and the digital processing system should have a predetermined level (signal intensity) at a predetermined frequency. Hereinafter, the digital test signal in the normal operation is referred to as a normal digital test signal. The storage units 41a and 41b store reference patterns of normal digital test signals in advance, and compare the reference patterns with the digital test signals from the digital

signal processing units

30a and 30b, respectively. In addition, the reference pattern of the normal digital test signal can be set using a digital test signal obtained by actually inputting the analog test signal to the analog signal processing section 10, the analog-to-digital converter 20, and the like in the normal operation. Alternatively, the reference pattern of the normal digital test signal may be set in common to the plurality of control devices 1 by using an average normal digital test signal obtained by statistics.

When the level difference (signal strength difference or gain difference) between the reference pattern of the digital test signal from the digital

signal processing units

30a and 30b and the normal digital test signal is smaller than a predetermined value, the

control units

40a and 40b determine that the analog signal processing unit 10 and the analog-to-digital converter 20 are operating normally.

On the other hand, when the difference (signal intensity difference or gain difference) between the reference pattern of the digital test signal from the digital

signal processing units

30a and 30b and the normal digital test signal is equal to or larger than a predetermined value, the

control units

40a and 40b determine that the analog signal processing unit 10 or the analog-to-digital converter 20 is not operating normally and an abnormality occurs in either configuration. In this way, the control device 1 of the present embodiment can check the soundness of the analog signal processing system using the test signal without setting the analog signal processing system as a parallel dual system.

In addition, since the digital signal processing system can be confirmed for its soundness by the parallel dual system described above, the digital test signal is used to confirm the soundness of the analog signal processing system. That is, as long as the soundness of the digital signal processing system is ensured by the parallel dual system, the digital test signal can be used to confirm the soundness of the analog signal processing system.

Next, a comparison and collation operation for detecting an abnormality and a failure will be described.

Fig. 2 (a) to 2 (D) are schematic diagrams showing an example of the comparison and verification operation of the

control units

40a and 40 b.

Fig. 2 (a) shows a reference pattern of the normal digital test signal stored in the register. The reference pattern of the normal digital test signal is stored in the storage sections 41a and 41b in advance. The

control units

40a and 40b generate a predetermined analog test signal from the test signal generating unit 50 based on the reference pattern of the normal digital test signal.

The address indicates an address written to the register, and the data indicates a level of the analog test signal. The data represents the level of the analog test signal. For example, in the case where the data is 1, the level of the analog test signal is-40 dBv. In the case of data of 2, the level of the analog test signal is-35 dBv. In the case of data of 3, the level of the analog test signal is-30 dBv. Thus, the level of the analog test signal is gradually increased by 5dBv every time the value of the data is increased by 1. That is, the level of the analog test signal changes every time the value of the data changes.

In addition, the data at each address is read out in the order of the addresses. The time interval for reading is set to a predetermined time interval (for example, 50 ms). Therefore, for example, in the case where data indicated by each address is read and executed at intervals of 50ms, the level of the analog test signal becomes 3 (e.g., -30dBv), 0 (e.g., -45dBv), 3 (e.g., -30dBv), or 0 (e.g., -45dBv) every 50 ms. In this way, the

control sections

40a, 40b can generate the analog test signal from the test signal generating section 50 based on the reference pattern of the normal digital test signal.

Of course, the correspondence relationship between the address and the data, the setting of the numerical value of the address, the setting of the numerical value of the data, and the setting of the level of the analog test signal are arbitrary, and not limited.

Fig. 2 (B) to 2 (D) show the result patterns of the digital test signal obtained by inputting the analog test signal generated in accordance with the reference pattern shown in fig. 2 (a). It takes a certain amount of time (hereinafter, also referred to as a delay time) from the generation of the analog test signal to the storage of the digital test signal. In consideration of such delay time, the control units 40a and 40B compare the data of addresses 1 to 5 of the reference pattern in fig. 2 (a) and the data of addresses 2 to 6 of the result pattern in fig. 2 (B), respectively.

For example, if data ± 1 is within the address +1 of the reference pattern as the allowable range, the control units 40a and 40B determine that the analog signal processing system is normal because the resultant pattern of fig. 2 (B) is within the allowable range with respect to the reference pattern of fig. 2 (a).

On the other hand, since the result pattern of fig. 2 (C) is out of the allowable range with respect to the reference pattern of fig. 2 (a), the

control units

40a and 40b determine that the analog signal processing system is abnormal.

The resulting pattern of fig. 2 (D) is outside the allowable range with respect to the reference pattern of fig. 2 (a) because the delay time is long. In this case, the

control units

40a and 40b also determine that the analog signal processing system is abnormal.

When it is determined that the analog signal processing system is abnormal, the

control units

40a and 40b display a warning or issue an alarm on a monitor for a crew of the electric train. Alternatively, the

control units

40a and 40b may control the brakes of the electric train or transmit the brakes to the outside of the electric train (such as a ground beacon).

Next, the frequency bands of the analog reception signal and the analog test signal will be described.

Fig. 3 is a diagram showing an example of the relationship between the frequency band Scnt of the analog reception signal and the frequency band Stest of the analog test signal. In the figure, the vertical axis represents the signal level (signal strength or gain). The horizontal axis represents frequency. The digital control signal and the digital test signal are different in form from the analog reception signal and the analog test signal, but exhibit the same characteristics (frequency and signal level) as the analog reception signal and the analog test signal, respectively. Therefore, illustration of the frequency bands of the digital reception signal and the digital test signal is omitted.

The frequency band Scnt that can be used for the analog reception signal is defined by specifications and the like. In contrast, the frequency band Stest of the analog test signal is set on the high frequency side or the low frequency side of the frequency band Scnt of the analog reception signal, and the peak frequency Fp of the analog test signal is located in the vicinity of the frequency band Scnt of the analog reception signal and outside the frequency band Scnt of the analog reception signal. For example, in fig. 3, the peak frequency Fp of the analog test signal is located near the maximum value Fmax of the frequency band Scnt of the analog received signal and is greater than the maximum value Fmax (Fp > Fmax). Since the peak frequency Fp is larger than the maximum value Fmax, the

control units

40a and 40b can distinguish between the digital control signal and the digital test signal according to their frequencies after the digital signal processing. The peak frequency Fp exceeds the maximum value Fmax, but is located near the maximum value Fmax. Thus, the

control units

40a and 40b can test the analog signal processing system using the analog test signal having a frequency close to the frequency of the analog reception signal, and can accurately confirm the soundness thereof. Although not shown, when the peak frequency Fp of the analog test signal is set on the low frequency side of the frequency band Scnt of the analog reception signal, the peak frequency Fp of the analog test signal is located in the vicinity of the minimum value Fmin of the frequency band Scnt of the analog reception signal and is smaller than the minimum value Fmin (Fp < Fmin). Since the peak frequency Fp is smaller than the minimum value Fmin, the

control sections

40a, 40b can distinguish between the digital control signal and the digital test signal according to their frequencies after the digital signal processing. The peak frequency Fp is lower than the minimum value Fmin but is located near the minimum value Fmin. Thus, the

control units

40a and 40b can test the analog signal processing system using the analog test signal having a frequency close to the frequency of the analog reception signal, and can accurately confirm the soundness thereof.

Further, the intensity of the analog test signal in the frequency band Scnt of the analog reception signal is set to be equal to or lower than the noise level (thermal noise level) NL of the analog reception signal. For example, in fig. 3, the strength of the analog test signal is equal to or less than the noise level NL of the analog received signal at a frequency equal to or less than the maximum value Fmax. This can reduce the influence of the analog test signal on the analog reception signal as much as possible.

In this way, in the present embodiment, the peak frequency Fp of the analog test signal is located in the vicinity of the frequency band Scnt of the analog reception signal and outside the frequency band Scnt of the analog reception signal. Further, the strength of the analog test signal in the frequency band Scnt of the analog reception signal is equal to or lower than the noise level NL of the analog reception signal. Thus, the

control units

40a and 40b can accurately check the soundness of the analog signal processing system using the frequency close to the analog reception signal without affecting the analog reception signal.

Next, a mode of simulating the test signal will be explained.

Fig. 4 is a diagram showing a pattern of an analog test signal. The vertical axis of the graph represents the signal level (signal strength or gain) of the analog test signal. The horizontal axis represents time. The analog test signal in the figure is obtained by extracting an analog test signal from signals input to the analog-to-digital converter 20 through the analog signal processing unit 10. Therefore, the analog test signal added by the adder 80 may contain noise N. The test signal generating unit 50 generates a pattern of analog test signals in response to a command from the

control unit

40b or 40 a.

As shown in fig. 4, the analog test signal is periodically output in a pattern of a predetermined signal level. Before t1, t2 to t3 and t4 to t5 are periods when the signal level of the analog test signal is zero (i.e., the analog test signal is not output). Therefore, when the analog signal processing section 10 is normal and has no noise N, the signal level before t1, in t2 to t3, and t4 to t5 is equal to or less than the threshold Sth. The threshold Sth indicates the lowest signal level detected as a signal by the

control units

40a and 40 b. The signal level that can be used for the analog reception signal is defined by specifications and the like. Therefore, the threshold Sth can be said to be the lower limit of the specification of the signal level that can be used for the analog reception signal.

First, in time t1 to t2, the analog test signal has a signal level (first signal strength) that is greater than but close to the lower limit of the specification of the signal level (threshold Sth). Next, in t2 to t3, the signal level of the analog test signal is zero. Next, in t3 to t4, the analog test signal has a signal level (second signal strength) that is less than but close to the upper limit of the specification of the signal level. Next, in t4 to t5, the signal level of the analog test signal is zero. In this way, the analog test signal periodically repeats the signal having the first signal intensity near the lower limit and the signal having the second signal intensity near the upper limit within the range of the specification of the signal level. Thus, the

control unit

40a or 40b can check the soundness of the analog signal processing system over almost the entire range of the specification of the received signal level. In other words, the soundness of the dynamic range covering a wide range of the analog signal processing system can be confirmed.

Further, noise N is generated in t2 to t 3. Since the noise N is different from the failure of the analog signal processing system, the

control units

40a and 40b need to remove and determine the noise N. For example, noise is generally transiently generated only for a short time, and a malfunction of an analog signal processing system continuously generates an abnormal signal. Therefore, the

control units

40a and 40b can determine the noise based on the noise generation period (the period in which the level of the noise exceeds the threshold Sth). For example, a noise allowable period (for example, about 10ms) is set in advance, and when the generation period of the abnormal signal is equal to or less than the noise allowable period, the

control units

40a and 40b determine the abnormal signal as noise. The

control units

40a and 40b do not use the abnormal signal determined as noise for determining the soundness of the analog signal processing system. Thus, even if noise is included in the analog test signal, the

controllers

40a and 40b can accurately determine the soundness of the analog signal processing system.

Fig. 5 is a diagram showing another example of the pattern of the analog test signal. The analog test signal shown in fig. 5 has any (intermediate) signal level between the upper limit and the lower limit of the specification of the analog received signal (hereinafter, also referred to as a standard signal level). The analog test signal periodically repeats the standard signal strength. For example, in time t 11-t 12, the analog test signal has a standard signal strength. Next, in t12 to t13, the signal level of the analog test signal is zero. Thereafter, the analog test signal repeats the signal pattern from t11 to t 13. In this way, the analog test signal may also periodically repeat the standard signal strength between the upper and lower limits of the range of the specification of the received signal level. Even in such a mode of the analog test signal, the soundness of the analog signal processing system can be confirmed.

Further, before t11, noise N1 is generated, and noise N2 is generated in t11 to t 12. The determination of the noise N1 and N2 may be the same as the determination of the noise N described with reference to fig. 4. Therefore, when the generation period of the noise N1 or N2 (the period during which the signal level of the noise exceeds the threshold Sth) is equal to or less than the noise allowable period, the

control units

40a and 40b do not use the noise N1 or N2 for the determination of the soundness of the analog signal processing system. Thus, even if the analog test signal includes the noises N1 and N2, the

controllers

(modification example)

Fig. 6 is a diagram showing a relationship between the frequency band Scnt of the analog received signal and the frequency band Stest of the analog test signal in the modification. In the figure, the vertical axis represents the signal level (signal strength or gain). The horizontal axis represents frequency. The digital control signal and the digital test signal are different in form from the analog reception signal and the analog test signal, but exhibit the same characteristics (frequency and signal level) as the analog reception signal and the analog test signal, respectively.

In fig. 6, the analog test signal is transmitted using two frequency bands. The frequency band Stest _ H of the analog test signal is set on the high frequency side of the frequency band Scnt of the analog received signal, similarly to the analog test signal shown in fig. 3, and the peak frequency (first frequency) Fp _ H of the analog test signal is located in the vicinity of the frequency band Scnt of the analog received signal and outside the frequency band Scnt of the analog received signal. For example, the peak frequency Fp _ H of the analog test signal is located near the maximum value Fmax of the frequency band Scnt of the analog received signal and is greater than the maximum value Fmax (Fp _ H > Fmax). Since the peak frequency Fp is larger than the maximum value Fmax, the

control units

40a and 40b can distinguish between the digital control signal and the digital test signal according to their frequencies after the digital signal processing. Although the peak frequency Fp _ H exceeds the maximum value Fmax, it is located near the maximum value Fmax. Thus, the

control units

40a and 40b can test the analog signal processing system using a frequency close to the frequency of the analog reception signal, and accurately confirm the soundness thereof.

On the other hand, the frequency band Stest _ L of the analog test signal is set on the low frequency side of the frequency band Scnt of the analog received signal, and the peak frequency Fp _ L of the analog test signal is located in the vicinity of the frequency band Scnt of the analog received signal and outside the frequency band Scnt of the analog received signal. For example, the peak frequency (second frequency) Fp _ L of the analog test signal is located near the minimum value Fmin of the frequency band Scnt of the analog received signal and is smaller than the minimum value Fmin (Fp _ L < Fmin). Since the peak frequency Fp _ L is smaller than the minimum value Fmin, the

control sections

40a, 40b can distinguish between the digital control signal and the digital test signal according to their frequencies after the digital signal processing. Although the peak frequency Fp _ L is lower than the minimum value Fmin, it is located near the minimum value Fmin. Thus, the

control units

Further, the intensity of the analog test signal in the frequency band Scnt of the analog reception signal is set to be equal to or lower than the noise level (thermal noise level) NL of the analog reception signal. For example, in fig. 6, the intensity of the analog test signal in the frequency band of the minimum value Fmin to the maximum value Fmax is equal to or less than the noise level NL of the analog received signal. This can reduce the influence of the analog test signal on the analog reception signal as much as possible.

In this way, the frequencies of the analog test signal are set in the two frequency bands Stest _ L, Stest _ H located on both sides of the frequency band Scnt of the analog received signal. This makes it possible to confirm the soundness of the analog signal processing system on the high frequency band side of the analog reception signal and also the soundness of the analog signal processing system on the low frequency band side of the analog reception signal. When the soundness of the analog signal processing system is confirmed in band Stest _ L and band Stest _ H,

control units

40a and 40b can estimate that the analog signal processing system is soundly present in the entire band Scnt between band Stest _ L and band Stest _ H.

Fig. 7 is a diagram showing a pattern of a simulated test signal according to a modification. In the present modification, the analog test signal periodically repeats a certain signal intensity (for example, a standard signal intensity) in each of the frequency band (first frequency) Stest _ H and the frequency band (second frequency) Stest _ L. However, the analog test signal alternately rises at different times in the frequency band Stest _ L and the frequency band Stest _ H. For example, the analog test signal of the band Stest _ L has the standard signal strength at times t23 to t24, t27 to t28, and the period of becoming the standard signal strength is t23 to t 27. On the other hand, the analog test signal of the band Stest _ H has the standard signal strength at times t21 to t22, t25 to t26, and the period of becoming the standard signal strength is t21 to t 25. That is, the generation cycle of the analog test signal of frequency band Stest _ L and the generation cycle of the analog test signal of frequency band Stest _ H are shifted from each other by half a cycle. This can suppress the amplifier saturation of the analog-to-digital converter 20.

Further,

control units

40a and 40b can check the soundness of the analog signal processing system in both frequency band Stest _ H and frequency band Stest _ L. Since the analog test signal of frequency band Stest _ L and the analog test signal of frequency band Stest _ H are shifted from each other by half a cycle,

control units

40a and 40b can frequently detect a failure of the analog signal processing system in a relatively short cycle. That is, the duty ratio of the failure detection can be improved. Further, in the present modification, the cycle of failure detection of the analog signal processing system by the

control units

40a and 40b can be made shorter than the failure detection cycle specified in the specifications of the safety device or the operation support device. Accordingly, the

control units

40a and 40b can detect a failure of the analog signal processing system in a failure detection period defined by a specification, and accordingly display a warning to a monitor (not shown) of the electric train or control the brake.

(second embodiment)

Fig. 8 is a block diagram showing an example of the configuration of the electric train control device 2 according to the second embodiment. The second embodiment is different from the first embodiment in that the digital signal processing section 30a includes a bit monitor (bit monitor) 32. Other structures of the second embodiment may be the same as the corresponding structures of the first embodiment. The digital signal processing unit 30a is constituted by, for example, a monolithic FPGA (Field Programmable Gate Array), and includes an input unit 31, a filter processing unit 33, and an output unit 34. The control unit 40a is communicably connected to the output unit 34 via the VME bus. The control unit 40a may be constituted by a single CPU, for example. In fig. 8, for convenience of explanation, the digital signal processing unit 30a and the control unit 40a are illustrated, and the digital signal processing unit 30b and the control unit 40b are not illustrated. The digital signal processing unit 30b may be constituted by a single FPGA, as in the case of the digital signal processing unit 30 a. The control unit 40b may be constituted by a single CPU, as in the control unit 40 a.

A bit monitor 32 is provided in the input section 31, which monitors the bits of the digital test signal from the analog-to-digital converter 20. The test signal generating unit 50 repeatedly outputs the analog test signal periodically during the running and the stopping of the electric train. Therefore, the bit monitor 32 monitors the bit variation of the digital control signal at the same period as or longer than the input period of the analog test signal.

Under normal operation of the analog signal processing system, the bits of the digital control signal will change with the periodic variation of the analog test signal. However, when the bit of the digital control signal is fixed without changing over a predetermined period (cycle of the analog test signal) or more, the analog signal processing system is highly likely to malfunction. In this case, the digital

signal processing units

30a and 30b output error signals to the

control units

40a and 40 b. The

control units

40a and 40b may determine that the analog signal processing system is abnormal when receiving the error signal.

In addition, during the running of the electric train, the bit monitor 32 may monitor the bit of the digital control signal instead of or together with the monitoring digital test signal. This is because the bit of the digital control signal may be fixed during the stop of the electric train, but frequently fluctuates during the running of the electric train. Therefore, the bit monitor 32 can determine an abnormality of the analog signal processing system by monitoring the bits of the digital control signal during the trolley running.

In this way, the bit monitor 32 may monitor the bit of the digital test signal or the digital control signal, and the

control units

40a and 40b may determine an abnormality of the analog signal processing system based on the fixed time of the bit of the digital test signal or the digital control signal. Thus, the second embodiment can easily confirm the soundness of the analog-to-digital converter 20.

The second embodiment can also obtain the effects of the first embodiment as long as the bit monitor 32 monitors bits and performs the comparison and collation operation of the

control units

40a and 40 b.

(third embodiment)

For example, in the response-type ATS, a Frequency Shift Keying (FSK) method is used, and therefore, a band pass filter may be used to limit the Frequency bandwidth of a control signal. In this case, it is difficult to set the frequency of the analog test signal outside the frequency band of the analog received signal.

Therefore, in the third embodiment, the frequency of the analog test signal is set within the frequency band of the analog reception signal, and the content (text) of the signal is distinguished. For example, the text of the analog test signal is set to a text that is impossible to use (meaningless) in the analog reception signal, making it necessarily different from the text of the analog reception signal. More specifically, as the text for simulating the test signal, the same text can be considered. The configuration of the control device of the third embodiment may be the same as that of any one of the control devices of the first and second embodiments.

For example, the test signal generating section 50 intermittently outputs the analog test signal at a fixed cycle during a period when the analog reception signal is not received. As in the first or second embodiment, the

control units

40a and 40b can confirm the soundness of the analog signal processing system by the digital test signal corresponding to the analog test signal.

On the other hand, when the analog test signal is added to the analog reception signal during the period of receiving the analog reception signalWhen the signal is high, the message simulating the received signal may not be demodulated. However, in general, when an analog reception signal is transmitted, text messages of the same contents are transmitted four in succession. The

control units

40a and 40b adopt two messages among four consecutive messages when the messages can be demodulated accurately. This is called as ₄C ₂And (6) checking.

Thus, utilize ₄C ₂Checking that the test signal generating section 50 immediately stops generating the analog test signal when receiving one message of the analog reception signal different from the analog test signal. This enables the

control units

40a and 40b to demodulate at least two consecutive messages among the four messages accurately. In the case where the analog test signal is superimposed on the initial message of the analog reception signal, there is a possibility that the initial message cannot be demodulated, but the second to fourth messages thereafter can be demodulated. When the analog test signal is not superimposed on the initial message of the analog reception signal, the test signal generating unit 50 stops generating the analog test signal immediately after receiving the initial message. In this case, the first to fourth messages can be demodulated.

As described above, in the third embodiment, although the frequency of the analog test signal overlaps the frequency band of the analog received signal, the analog test signal and the analog received signal are distinguished from each other in terms of the content (text) of data. Further, when the analog reception signal is received, generation of the analog test signal is immediately stopped, and the analog reception signal can be demodulated. In this way, according to the third embodiment, the

control units

40a and 40b can demodulate both the analog reception signal and the analog test signal and can recognize them. This makes it possible to confirm the soundness of the analog signal processing system.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the present invention. These embodiments and modifications are included in the scope and spirit of the invention, and are also included in the scope of the invention described in the claims and equivalents thereof.

Claims

1. An electric car control device is provided with:

an analog signal processing unit for processing an analog reception signal received via an antenna;

an analog/digital conversion unit that converts the analog signal from the analog signal processing unit into a digital signal;

a digital signal processing unit that processes the digital signal;

a control unit that controls the electric train based on the digital signal from the digital signal processing unit; and

a test signal generating section that supplies an analog test signal different in frequency or signal content from the analog reception signal to the analog signal processing section,

the peak frequency of the analog test signal is located near and outside the frequency band of the analog receive signal,

the strength of the analog test signal within the frequency band of the analog receive signal is less than or equal to the noise level of the analog receive signal.

2. The trolley control device according to claim 1, wherein,

the analog signal processing unit may further include a storage unit that stores in advance a normal digital test signal obtained from the digital signal processing unit by inputting the analog test signal when the analog signal processing unit and the analog/digital conversion unit are normal.

3. The trolley control device according to claim 2, wherein,

the control unit compares the digital test signal output from the digital signal processing unit by inputting the analog test signal with the normal digital test signal, and detects an abnormality in the analog signal processing unit and the analog/digital conversion unit based on a result of the comparison.

4. The trolley control device according to any one of claims 1 to 3, wherein,

further comprising an addition unit provided between the test signal generation unit and the input of the analog signal processing unit,

the addition unit adds the analog test signal to the analog reception signal.

5. The trolley control device according to claim 1, wherein,

the peak frequency of the analog test signal is either one or both of a first frequency exceeding a maximum value of a frequency band of the analog reception signal and a second frequency lower than a minimum value of the frequency band of the analog reception signal.

6. The trolley control device according to claim 5, wherein,

the test signal generating section alternately supplies the analog test signal of which the peak frequency is the first frequency and the analog test signal of which the peak frequency is the second frequency to the analog signal processing section.

7. The trolley control device according to any one of claims 1 to 3, wherein,

the signal strength of the analog test signal includes a first signal strength near a lower limit of a specification of the analog received signal and a second signal strength near an upper limit of the specification of the analog received signal.

8. The trolley control device according to any one of claims 1 to 3, wherein,

the digital signal processing unit outputs an error signal to the control unit when the digital signal does not change for a predetermined period or more,

the control unit determines that the analog signal processing unit and the analog/digital conversion unit are abnormal when the error signal is received.

9. The trolley control device according to any one of claims 1 to 3, wherein,

the test signal generating section sets a frequency of an analog test signal different from the analog reception signal in the signal content within a frequency band of the analog reception signal,

the test signal generation section stops generating the analog test signal when it is detected that the analog reception signal is input based on the signal content.