CN107707208B - Signal power control method and control circuit for communication system equipment - Google Patents
Signal power control method and control circuit for communication system equipment Download PDFInfo
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- H—ELECTRICITY
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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- H—ELECTRICITY
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
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- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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Abstract
The invention provides a signal power control method and circuit of communication system equipment, which can control the output power of the communication system equipment, coupling and sampling the output radio frequency signal after the power amplification of the communication system equipment, extracting the maximum voltage envelope value from the converted direct current voltage sequence, integral comparison is carried out on the maximum voltage envelope value after sampling and holding processing and a preset reference voltage to obtain a control voltage, attenuation control is carried out on the output voltage of the communication system equipment according to the control voltage, namely, before the output radio frequency signal of the communication system equipment is subjected to power amplification, the attenuation control operation is carried out, the output power of the output radio frequency signal after power amplification is also controlled, and the device such as a power amplifier and the like cannot be burnt due to overlarge output power, so that the whole communication system is broken down.
Description
Technical Field
The present invention relates to the field of signal power control of communication systems, and in particular, to a signal power control method and a control circuit for communication system devices.
Background
The communication system equipment is used for outputting radio frequency signals for communication in different systems such as time slot signals, continuous signals and the like, in order to realize uplink and download better and faster in the message transmission process, the radio frequency signals output by the communication system equipment are usually subjected to power amplification, and because the output power of the radio frequency signals output by the communication system equipment is generally uncontrollable and amplified by a power amplifier under the condition of larger output power, the equipment such as the power amplifier is possibly burnt, so that the whole communication system is paralyzed.
Disclosure of Invention
Based on this, the invention provides a signal power control method and a control circuit of communication system equipment, which can control the output power of the communication system equipment.
A signal power control method of a communication system apparatus, comprising the steps of:
coupling and sampling an output radio frequency signal of the communication system equipment after power amplification;
performing power detection on the output radio frequency signal obtained by coupling sampling to obtain direct current voltage;
extracting a maximum voltage envelope value from the direct-current voltage, and performing sampling holding processing on the maximum voltage envelope value to obtain a smooth direct-current voltage;
performing integral comparison on the smooth direct current voltage and a preset reference voltage to obtain a control voltage;
and carrying out attenuation control on the output voltage of the communication system equipment according to the control voltage.
The signal power control method of the communication system equipment comprises the steps of coupling and sampling an output radio frequency signal of the communication system equipment after power amplification, extracting a maximum voltage envelope value from a converted direct current voltage sequence, performing integral comparison on the maximum voltage envelope value after sampling and holding processing and a preset reference voltage to obtain a control voltage, and performing attenuation control on the output voltage of the communication system equipment according to the control voltage, namely executing attenuation control operation before the power amplification of the output radio frequency signal of the communication system equipment so that the output power of the output radio frequency signal after power amplification is also controlled, and the equipment such as a power amplifier and the like cannot be burnt due to overlarge output power to cause the paralysis of the whole communication system.
A signal power control circuit for a communication system device, comprising: the device comprises a power detector, a sampling holder, an integral comparator, a coupler for connecting a power amplifier and an attenuator for connecting the power amplifier;
the coupler is used for coupling and sampling an output radio frequency signal of the communication system equipment after being power amplified by the power amplifier;
the power detector is used for performing power detection on the output radio-frequency signal obtained by coupling sampling to obtain direct-current voltage;
the sampling holder is used for extracting a maximum voltage envelope value from the direct-current voltage and carrying out sampling holding processing on the maximum voltage envelope value so as to obtain smooth direct-current voltage;
the integral comparator is used for carrying out integral comparison on the smooth direct-current voltage and a preset reference voltage to obtain a control voltage;
the attenuator is used for carrying out attenuation control on the output voltage of the communication system equipment by utilizing the control voltage.
The signal power control circuit of the communication system equipment comprises an analog circuit consisting of a coupler used for connecting a power amplifier, a power detector, a sampling holder, an integral comparator and an attenuator used for connecting the power amplifier, realizes automatic level control of the communication system equipment, and has the advantages of simple circuit structure, easy integration, low cost and small hardware construction difficulty. The coupler couples and samples the output radio frequency signal of the communication system equipment after power amplification, the sampling holder extracts the maximum voltage envelope value from the converted direct current voltage sequence, the integral comparator performs integral comparison on the maximum voltage envelope value after sampling and holding processing and a preset reference voltage to obtain a control voltage, and the attenuator performs attenuation control on the output voltage of the communication system equipment according to the control voltage, namely before the output radio frequency signal of the communication system equipment is subjected to power amplification through the power amplifier, attenuation control operation is performed, so that the output power of the output radio frequency signal of the power amplifier is also controlled, and the breakdown of the whole communication system is avoided because devices such as a power amplifier and the like are burnt due to overlarge output power of the power amplifier.
Drawings
Fig. 1 is a flow chart illustrating a signal power control method of a communication system apparatus according to the present invention;
fig. 2 is a flow diagram of a signal power control method of a communication system device in one embodiment;
fig. 3 is a diagram illustrating power control comparison of signal systems of different standards implemented by the method according to this embodiment in an embodiment;
fig. 4 is a schematic diagram of a signal power control circuit of a communication system apparatus according to the present invention;
fig. 5 is a schematic configuration diagram of a signal power control circuit of a communication system device in one embodiment;
FIG. 6 is a schematic diagram of the amplifier in one embodiment;
FIG. 7 is a schematic diagram of the construction of the reducer in one embodiment;
FIG. 8 is a schematic diagram of the sample holder in one example embodiment;
FIG. 9 is a schematic diagram of the sample holder in another exemplary embodiment;
fig. 10 is a schematic structural diagram of the integration comparator in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating a signal power control method of a communication system device according to the present invention.
The signal power control method of the communication system device according to this embodiment may include:
s11: coupling and sampling an output radio frequency signal of the communication system equipment after power amplification;
s12: performing power detection on the output radio frequency signal obtained by coupling sampling to obtain direct current voltage;
s13: extracting a maximum voltage envelope value from the direct-current voltage, and performing sampling holding processing on the maximum voltage envelope value to obtain a smooth direct-current voltage;
s14: performing integral comparison on the smooth direct current voltage and a preset reference voltage to obtain a control voltage;
s15: and carrying out attenuation control on the output voltage of the communication system equipment according to the control voltage.
In the method for controlling signal power of communication system equipment according to this embodiment, after coupling and sampling an output radio frequency signal of the communication system equipment after power amplification, a maximum voltage envelope value is extracted from a dc voltage sequence obtained by power detection and conversion, integral comparison is performed on a smooth dc voltage obtained after sample and hold processing of the dc voltage and a preset reference voltage to obtain a control voltage, and attenuation control is performed on the output voltage of the communication system equipment according to the control voltage, that is, before power amplification is performed on the output radio frequency signal of the communication system equipment, attenuation control operation is performed so that the output power of the output radio frequency signal after power amplification is also controlled, and it is not possible to burn devices such as a power amplifier device due to excessive output power, thereby causing paralysis of the entire communication system.
The communication system equipment can be time slot signal system equipment or continuous signal system equipment; the time slot signal system device can be a communication system device which outputs time slot signals with different proportions. The time slot signal belongs to one of discrete signals, namely a discontinuous radio frequency signal in time, such as GSM, TD-SCDMA, TDD-LTE and other standard signals; the continuous signal is a radio frequency signal continuously transmitted in time, such as a spread spectrum signal of CDMA, WCDMA, FDD-LTE, etc. The dc voltage after power detection may be a time domain signal.
If the radio frequency signal output by the communication system equipment is a time slot signal, the time slot signal is subjected to detection processing to obtain a voltage waveform similar to a pulse, and the voltage waveform similar to the pulse is not a converged control voltage obtained after passing through the integral comparison circuit, so that the purpose of controlling the output level of the communication system equipment cannot be achieved, the output power after power amplification is very large in jitter, a smooth direct current voltage can be obtained by extracting a maximum voltage envelope value from the converted direct current voltage and performing sampling and holding processing on the maximum voltage envelope value, and the purpose of controlling the output level of the communication system equipment is achieved by obtaining a converged control voltage after being processed by the integral comparison circuit. Therefore, the present embodiment is compatible with the attenuation control of the output rf signal of the timeslot signal system device or the continuous signal system device.
For steps S12, S13, and S14, in an embodiment, after performing power detection on the coupled and sampled output rf signal to obtain a dc voltage, the following steps are included before extracting a maximum voltage envelope value from the dc voltage and performing sample-and-hold processing on the maximum voltage envelope value to obtain a smoothed dc voltage:
s131: amplifying the direct current voltage by a first preset multiple;
and after extracting the maximum voltage envelope value from the direct current voltage and performing sample-hold processing on the maximum voltage envelope value to obtain a smooth direct current voltage, performing integral comparison on the smooth direct current voltage and a preset reference voltage to obtain a control voltage, the method comprises the following steps:
s132: and reducing the maximum voltage envelope value subjected to the sampling and holding processing by a second preset multiple.
In this embodiment, if the timeslot signal system device outputs timeslot signals of different ratios within a period of time, for example, the timeslot signal 10000000 and the timeslot signal 11111111, an output power deviation after power amplification is relatively large, before a maximum voltage envelope value is extracted from the converted dc voltage, the dc voltage is amplified by a first preset multiple, then the maximum voltage envelope value is extracted, and after sampling and holding processing is performed on the maximum voltage envelope value, the preset multiple is reduced, and finally, the control voltage obtained through integral comparison enables the output powers of the timeslot signals of different ratios to be smaller than the preset deviation, for example, smaller than 0.3 dB. As shown in fig. 3, fig. 3 is a power control comparison diagram of different system signal systems implemented by the method according to this embodiment in a specific example, including a power control comparison diagram of a WADMA signal system, a CDMA signal system, a GSM single-slot signal system, a GSM full-slot signal system, an EDGE full-slot signal system, a TD-SCDMA signal system, and a TDD-LTE signal system, where a deviation of an output power value of an attenuated radio frequency signal of the different signal systems is less than 0.3 dB.
The invention also provides a signal power control circuit of the communication system equipment.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a signal power control circuit of a communication system device according to the present invention, which can implement the signal power control method of the communication system device as described above.
The signal power control circuit of the communication system device according to this embodiment may include: a coupler 10 for connecting a power amplifier, a power detector 20, a sample holder 30, an integral comparator 40 and an attenuator 50 for connecting the power amplifier; specifically, the input end of the coupler 10 is connected with the output end of the power amplifier, and the output end of the coupler 10 is connected with the input end of the power detector 20; the input of the sample holder 30 is connected to the output of the power detector 20, the output of the sample holder is connected to the input of the integrating comparator 40, the first input of the attenuator 50 is connected to the output of the integrating comparator 40, the second input of the attenuator 50 is connected to the output of the communication system device, and the output of the attenuator 50 is connected to the input of the power amplifier.
The coupler 10 is used for coupling and sampling an output radio frequency signal of the communication system equipment after being power-amplified by the power amplifier;
the power detector 20 is configured to perform power detection on the output radio frequency signal obtained by coupling sampling to obtain a direct current voltage;
the sample holder 30 is configured to extract a maximum voltage envelope value from the dc voltage, and perform sample-and-hold processing on the maximum voltage envelope value to obtain a smooth dc voltage;
the integral comparator 40 is configured to perform integral comparison on the smoothed direct-current voltage and a preset reference voltage to obtain a control voltage;
the attenuator 50 is used for controlling the attenuation of the output voltage of the communication system equipment by using the control voltage.
The signal power control circuit of the communication system device according to this embodiment is an analog circuit including a coupler for connecting a power amplifier, a power detector, a sample holder, an integral comparator, and an attenuator for connecting the communication system device and the power amplifier, and realizes automatic level control of the communication system device. The coupler couples and samples the output radio frequency signal of the communication system equipment after power amplification, the sampling holder extracts the maximum voltage envelope value from the direct current voltage sequence, the integral comparator performs integral comparison on the smooth direct current voltage after sampling and holding processing and a preset reference voltage to obtain a control voltage, and the attenuator performs attenuation control on the output voltage of the communication system equipment according to the control voltage, namely before the output radio frequency signal of the communication system equipment is subjected to power amplification through the power amplifier, attenuation control operation is performed to control the output power of the output radio frequency signal of the power amplifier, so that the output power of the output radio frequency signal of the power amplifier is controlled, and the equipment such as a power amplifier device and the like is not burnt due to overlarge output power of the power amplifier, and the whole communication system is prevented from being broken down.
Wherein the attenuator may be an ATT attenuator. The coupler 10 can select couplers with different coupling degrees such as 10dB, 20dB and 30dB according to the requirements of the power of a radio frequency amplification link and the like; the direct resistance coupler, the microstrip coupler or the patch type directional coupler can be selected according to the form of the coupler.
The power detector 20 can be selected from a PIN detector, an envelope detector, an RMS square-law detector, a logarithmic detector, or the like. In laying out the power detector 20, a peripheral circuit for ensuring the integrity of the output dc voltage may be designed.
The communication system equipment can be time slot signal system equipment or continuous signal system equipment; the time slot signal system device can be a communication system device which outputs time slot signals with different proportions. The time slot signal belongs to one of discrete signals, namely a discontinuous radio frequency signal in time, such as GSM, TD-SCDMA, TDD-LTE and other standard signals; the continuous signal is a radio frequency signal continuously transmitted in time, such as a spread spectrum signal of CDMA, WCDMA, FDD-LTE, etc. The dc voltage after power detection may be a time domain signal.
If the radio frequency signal output by the communication system device is a time slot signal, the time slot signal is a voltage waveform similar to a pulse obtained by the detection processing of the power detector, and the voltage waveform similar to the pulse is not a converged control voltage obtained by the voltage waveform after passing through the integral comparison circuit, so that the purpose of controlling the output level of the communication system device cannot be achieved, and the output power jitter after power amplification is very large. Therefore, the present embodiment is compatible with the attenuation control of the output rf signal of the timeslot signal system device or the continuous signal system device.
In an embodiment, referring to fig. 5, the signal power control circuit of the communication system device further includes: an amplifier 60 and a reducer 70; the amplifier 60 is connected to the sample holder 30 and the power detector 20, respectively, and the reducer 70 is connected to the sample holder 30 and the integration comparator 40, respectively;
the amplifier 60 is configured to extract a maximum voltage envelope value from the dc voltage after performing power detection on the output radio frequency signal obtained by coupling sampling to obtain the dc voltage, and amplify the dc voltage obtained from the power detector by a first preset factor before performing sample hold processing on the maximum voltage envelope value to obtain a smooth dc voltage;
the reducer 70 is configured to extract a maximum voltage envelope value from the dc voltage, perform sample-and-hold processing on the maximum voltage envelope value to obtain a smoothed dc voltage, perform integral comparison on the smoothed dc voltage and a preset reference voltage, and reduce the smoothed dc voltage subjected to sample-and-hold processing by the sample-and-hold unit by a second preset multiple before obtaining a control voltage.
In this embodiment, if the timeslot signal system device outputs timeslot signals of different ratios within a period of time, for example, the single timeslot signal 10000000 and the full timeslot signal 11111111111, an output power deviation of the power amplifier is relatively large, before the sample holder 20 extracts a maximum voltage envelope value from the dc voltage converted by the power detector 20, the amplifier 60 amplifies the dc voltage by a first preset multiple, then the sample holder 20 extracts the maximum voltage envelope value, and then the sample holder performs sample holding processing on the maximum voltage envelope value, and then the reducer 70 reduces the preset multiple, and finally the control voltage obtained by integral comparison by the integral comparator 40 is integrated, and after attenuation control by the attenuator 50, the output powers of the timeslot signals of different ratios can be smaller than the preset deviation, for example, smaller than 0.3 dB. As shown in fig. 3, fig. 3 is a power control comparison diagram of signal systems of different standards implemented by the signal power control circuit of the communication system device according to this embodiment in a specific example, where the power control comparison diagram includes power control comparison diagrams of a WADMA signal system, a CDMA signal system, a GSM single timeslot signal system, a GSM full timeslot signal system, an EDGE full timeslot signal system, a TD-SCDMA signal system, and a TDD-LTE signal system, and a deviation of an output power value of an attenuated radio frequency signal of the different signal systems is less than 0.3 dB.
The amplifier 60 may be an N-fold amplifier, and as shown in fig. 6, the amplifier 60 includes a first operational amplifier U1, a first resistor R1, a second resistor R2, and an inverse integrator circuit for maintaining a dc voltage;
the output end of the first operational amplifier U1 is connected to the inverting input end of the first operational amplifier U1 through a second resistor R2, the output end of the first operational amplifier U1 is connected to the input end of the sample holder 30, the output end of the first operational amplifier U1 is grounded through a second resistor R2 and a first resistor R1 in sequence, and the non-inverting input end of the first operational amplifier U1 is connected to the output end of the power detector 20 through an inverting integration circuit. Specifically, the inverse integrator circuit may be composed of a resistor R0 and a capacitor C0, the non-inverting input terminal of the operational amplifier U1 is connected to the output terminal of the power detector 20 through the capacitor C0, and the output terminal of the power detector 20 is grounded through the resistor R0. The first predetermined multiple of the amplifier amplification is determined by the ratio between the first resistor R1 and the second resistor R2.
The reducer 70 may be an N-fold reducer, and in a specific embodiment, as shown in fig. 7, the reducer 70 includes a voltage follower U2, a third resistor R3, and a fourth resistor R4, a non-inverting input terminal of the voltage follower U2 is connected to an output terminal of the sample holder through the fourth resistor R4, a non-inverting input terminal of the voltage follower U2 is connected to ground through the third resistor R3, an inverting input terminal of the voltage follower U2 is connected to an output terminal of the voltage follower, and an output terminal of the voltage follower U2 is connected to an input terminal of the integral comparator 40.
The second predetermined reduction factor N of the reducer 70 is determined by the third resistor R3 and the fourth resistor R4, and the reduction factor of the reducer is the same as the amplification factor of the amplifier.
In one embodiment, as shown in fig. 8, the sample holder may include a transistor K1, a first integrating capacitor C2, and a fifth resistor R5; the base of the transistor K1 is connected to the output terminal of the amplifier 60, the emitter of the transistor K1 is grounded through the first integrating capacitor C2, the emitter of the transistor K1 is also grounded through a fifth resistor R5, and the emitter of the transistor K1 is connected to the input terminal of the reducer.
In another embodiment, as shown in fig. 9, the sample holder may include a diode D1, a second integrating capacitor C3, and a sixth resistor R6; the anode of the diode D1 is connected to the output terminal of the amplifier 60, the cathode of the diode D1 is grounded through the second integrating capacitor C3, the cathode of the diode D2 is grounded through the sixth resistor R6, and the cathode of the diode D1 is connected to the input terminal of the reducer 70.
In one embodiment, as shown in fig. 10, the integrating comparator 40 includes a second operational amplifier U3 and a capacitor C4, an inverting input terminal of the second operational amplifier U3 is used for connecting to a preset reference level, a non-inverting input terminal of the second operational amplifier U3 is connected to an output terminal of the second operational amplifier U3 through the capacitor C4, and an output terminal of the second operational amplifier is connected to an input terminal of the attenuator.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express a few embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (8)
1. A signal power control method for a communication system device, comprising the steps of:
coupling and sampling an output radio frequency signal of the communication system equipment after power amplification;
performing power detection on the output radio frequency signal obtained by coupling sampling to obtain direct current voltage;
amplifying the direct current voltage by a first preset multiple;
extracting a maximum voltage envelope value from the direct-current voltage, and performing sampling holding processing on the maximum voltage envelope value to obtain a smooth direct-current voltage;
reducing the smooth direct current voltage by a second preset multiple; the first preset multiple is the same as the second preset multiple;
performing integral comparison on the smooth direct current voltage and a preset reference voltage to obtain a control voltage;
and carrying out attenuation control on the output voltage of the communication system equipment according to the control voltage.
2. The signal power control method of a communication system apparatus according to claim 1, characterized in that said communication system apparatus is a time slot signal system apparatus or a continuous signal system apparatus.
3. A signal power control circuit for a communication system device, comprising: the device comprises a power detector, an amplifier, a sampling holder, a reducer, an integral comparator, a coupler for connecting a power amplifier and an attenuator for connecting the power amplifier;
the coupler is used for coupling and sampling an output radio frequency signal of the communication system equipment after being power amplified by the power amplifier;
the power detector is used for performing power detection on the output radio-frequency signal obtained by coupling sampling to obtain direct-current voltage;
the amplifier is respectively connected with the sampling holder and the power detector and is used for amplifying the direct-current voltage acquired from the power detector by a first preset multiple;
the sampling holder is used for extracting a maximum voltage envelope value from the direct-current voltage and carrying out sampling holding processing on the maximum voltage envelope value so as to obtain smooth direct-current voltage;
the reducer is respectively connected with the sampling holder and the integral comparator and is used for reducing the smooth direct-current voltage subjected to sampling and holding processing by the sampling holder by a second preset multiple; the first preset multiple is the same as the second preset multiple;
the integral comparator is used for carrying out integral comparison on the smooth direct-current voltage and a preset reference voltage to obtain a control voltage;
the attenuator is used for carrying out attenuation control on the output voltage of the communication system equipment by utilizing the control voltage.
4. Signal power control circuit of a communication system device according to claim 3,
the amplifier comprises a first operational amplifier, a first resistor, a second resistor and an inverse integration circuit for keeping direct-current voltage;
the output end of the first operational amplifier is connected with the reverse input end of the first operational amplifier through a second resistor, the output end of the first operational amplifier is connected with the input end of the sampling holder, the output end of the first operational amplifier is grounded through the second resistor and the first resistor sequentially, and the non-inverting input end of the first operational amplifier is connected with the output end of the power detector through a reverse integration circuit.
5. Signal power control circuit of a communication system device according to claim 4,
the reducer comprises a voltage follower, a third resistor and a fourth resistor;
the non inverting input end of the voltage follower is connected with the output end of the sampling retainer through a fourth resistor, the non inverting input end of the voltage follower is grounded through a third resistor, the output end of the voltage follower is connected with the inverting input end of the voltage follower, and the output end of the voltage follower is connected with the input end of the integral comparator.
6. Signal power control circuit of a communication system device according to any of claims 3-5,
the sampling retainer comprises a triode, a first integrating capacitor and a fifth resistor; the base electrode of the triode is connected with the output end of the amplifier, the emitter electrode of the triode is grounded through the first integrating capacitor, the emitter electrode of the triode is also grounded through a fifth resistor, and the emitter electrode of the triode is connected with the input end of the reducer;
or the like, or, alternatively,
the sample holder comprises a diode, a second integrating capacitor and a sixth resistor; the anode of the cathode of the diode is connected with the output end of the amplifier, the cathode of the diode is grounded through the second integrating capacitor, the cathode of the diode is grounded through the sixth resistor, and the cathode of the diode is connected with the input end of the reducer.
7. Signal power control circuit of a communication system device according to any of claims 3-5,
the integral comparator comprises a second operational amplifier and a capacitor, wherein the inverting input end of the second operational amplifier is used for being connected with a preset reference level, the non-inverting input end of the second operational amplifier is connected with the output end of the second operational amplifier through the capacitor, and the output end of the second operational amplifier is connected with the input end of the attenuator.
8. The signal power control circuit of the communication system device according to any of claims 3-5, further comprising a radio frequency diode switch;
the coupler is connected with the power detector through the radio frequency diode switch; the coupler is connected with the anode of the radio frequency diode switch, and the power detector is connected with the cathode of the radio frequency diode.
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| CN110768684B (en) * | 2019-10-31 | 2021-08-06 | 中电科思仪科技股份有限公司 | Amplitude control device and method for time slot signal |
| CN111294910A (en) * | 2020-02-06 | 2020-06-16 | 青岛合启立智能科技有限公司 | LoRa power detection method, device and transmitting circuit |
| CN111669134B (en) * | 2020-06-02 | 2023-10-20 | 京信网络系统股份有限公司 | Method, system, equipment and storage medium for controlling power of power amplifier under TDD system |
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