CN107689324B

CN107689324B - Semiconductor device and preparation method thereof

Info

Publication number: CN107689324B
Application number: CN201610633438.2A
Authority: CN
Inventors: 赵猛
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-08-04
Filing date: 2016-08-04
Publication date: 2020-04-10
Anticipated expiration: 2036-08-04
Also published as: CN107689324A

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The method comprises the steps of providing a semiconductor substrate, and forming a mask layer with a window on the semiconductor substrate, wherein the window corresponds to a groove to be formed in the semiconductor substrate. And performing pre-ion implantation, wherein the implantation direction of the pre-ion implantation forms an included angle with the normal direction of the semiconductor substrate so as to form an ion implantation area on the top of the semiconductor substrate. And etching the semiconductor substrate by taking the mask layer as a mask to form the groove. And filling an isolation material in the groove to form a shallow groove isolation structure. And removing the mask layer. Performing a subsequent ion implantation on the semiconductor substrate. The semiconductor device formed according to the method has stable performance.

Description

Semiconductor device and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.

Background

In a semiconductor device such as a MOS transistor, the threshold voltage of a channel has a great influence on the electrical performance of the semiconductor device. In the existing semiconductor device, the phenomenon that the threshold voltage of the corner part of the channel close to the shallow trench isolation structure is inconsistent with the threshold voltage in the channel exists, so that the performance of the semiconductor device is unstable and even fails.

Therefore, it is necessary to provide a semiconductor device and a method for manufacturing the same to solve the problems of the prior art.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In order to overcome the problems existing at present, the invention provides a preparation method of a semiconductor device. The method comprises the steps of providing a semiconductor substrate, and forming a mask layer with a window on the semiconductor substrate, wherein the window corresponds to a groove to be formed in the semiconductor substrate. And performing pre-ion implantation, wherein the implantation direction of the pre-ion implantation forms an included angle with the normal direction of the semiconductor substrate so as to form an ion implantation area on the top of the semiconductor substrate. And etching the semiconductor substrate by taking the mask layer as a mask to form the groove. And filling an isolation material in the groove to form a shallow groove isolation structure. And removing the mask layer. Performing a subsequent ion implantation on the semiconductor substrate.

According to the preparation method of the semiconductor device, the ion implantation area can be formed through ion implantation in advance, and the ion implantation area can make up for the loss of implantation dosage of ions at the corner part of the channel close to the shallow trench isolation structure due to the isolation effect, the annealing effect and the like, so that the finally formed semiconductor device is stable in performance.

Preferably, the implantation source of the preliminary ion implantation is BF2 or B.

Preferably, the implantation energy of the preliminary ion implantation is 2K-40KeV, and the implantation dose of the preliminary ion implantation is 5 × 10¹²-5×10¹³Ions per square centimeter.

Preferably, the preliminary ion implantation is oblique ion implantation, and the included angle is 15-45 °.

Preferably, the implantation source of the preliminary ion implantation includes one or more of carbon ions, fluorine ions, and nitrogen ions.

Preferably, the implantation energy of the preliminary ion implantation is 4K-20KeV, and the implantation dose of the preliminary ion implantation is 1 × 10¹³-1×10¹⁴Ions per square centimeter.

Preferably, the preliminary ion implantation is oblique ion implantation, and the included angle is 0-40 °.

Preferably, the preliminary ion implantation is plasma implantation.

Preferably, the subsequent ion implantation is one or more of well region implantation, channel implantation and threshold voltage adjustment implantation.

According to another aspect of the present invention, a semiconductor device is provided. The semiconductor device is manufactured by any one of the methods described above.

According to the ion implantation region of the semiconductor device, the loss of implantation dosage of ions at the corner part of the channel close to the shallow trench isolation structure due to the isolation effect, the annealing effect and the like can be made up, so that the threshold voltages of the channels of the semiconductor device can be consistent, and the performance of the semiconductor device is stable.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

FIG. 1 shows a flow chart of a method of fabricating a semiconductor device according to a preferred embodiment of the present invention; and

fig. 2A to 2H show schematic cross-sectional views of structures obtained by sequentially carrying out the manufacturing method illustrated in fig. 1.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

In the manufacturing process of the existing MOS tube, annealing treatment is often needed to be carried out on the shallow trench isolation structure. The applicant finds that due to an annealing effect, an isolation effect and the like, the ion implantation dose at the corner of the channel close to the shallow trench isolation structure is lost, so that the threshold voltages of the channel are inconsistent, and the performance of the semiconductor device is unstable or even fails.

In order to solve the above problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, and an exemplary embodiment of the present invention will be described in detail with reference to fig. 1 and fig. 2A to 2H. Wherein fig. 1 shows a flow chart of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention; fig. 2A to 2H show schematic cross-sectional views of structures obtained by sequentially carrying out the manufacturing method illustrated in fig. 1.

Step S1 is first executed: providing a semiconductor substrate, and forming a mask layer with a window on the semiconductor substrate, wherein the window corresponds to a groove to be formed in the semiconductor substrate.

Specifically, in this step, as shown in fig. 2A, the semiconductor substrate 110 is first provided. The semiconductor substrate 110 may be at least one of the following materials: undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-stacked germanium (S-SiGeOI), silicon-on-insulator germanium (SiGeOI), germanium-on-insulator (GeOI), and the like. In this embodiment, a single crystal silicon is used as a constituent material of the semiconductor substrate 110.

Next, as shown in FIG. 2B, on the semiconductor substrate 110A layer of masking material 140' is formed thereover. In particular, in the present embodiment, the mask material layer 140' may be a hard mask material layer such as a SiN layer. It should be noted that a buffer material layer 130 'may also be formed between the mask material layer 140' and the semiconductor substrate 110 to release the stress between the mask material layer 140 'and the semiconductor substrate 110 and increase the bonding force between the mask material layer 140' and the semiconductor substrate 110. As an example, the buffer material layer 130' may be SiO₂The layer, which may be 100-400 angstroms thick.

The mask material layer 140 'and the buffer material layer 130' may be formed using any conventional technique familiar to those skilled in the art. Preferably, the mask material layer 140 'and the buffer material layer 130' can be formed by Chemical Vapor Deposition (CVD). Such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and the like.

Then, as shown in fig. 2C, the mask material layer 140 'and the buffer material layer 130' are etched to form the mask layer 140 having the window 120 and the buffer layer 130 on the semiconductor substrate 110.

In this embodiment, the window 120 may be formed by a photolithography method. Specifically, the process may include: a photoresist layer is coated on the mask material layer 140 ' by spin coating, then processes such as exposure and development are sequentially performed to form a photoresist layer having a pattern corresponding to the window 120, then the mask material layer 140 ' and the buffer material layer 130 ' are etched using the photoresist layer having the pattern corresponding to the window 120 as a mask until the semiconductor substrate 110 is exposed, and then the photoresist layer is removed by an ashing process.

To this end, a mask layer 140 having a window 120 is formed on the semiconductor substrate 110, and a buffer layer 130 that can be used to relieve stress is also formed between the mask layer 140 and the semiconductor substrate 110.

It should be noted that the width and shape of the window 120 can be determined according to actual needs. Specifically, in the present embodiment, the window 120 corresponds to the trench 160' to be formed in the semiconductor substrate 110 (fig. 2E). This will be described in detail below.

Next, step S2 is executed: and performing pre-ion implantation, wherein the implantation direction of the pre-ion implantation forms an included angle with the normal direction of the semiconductor substrate so as to form an ion implantation area on the top of the semiconductor substrate.

As shown in fig. 2D, an angled ion implantation is performed on the semiconductor substrate 110, i.e., the implantation direction has an angle α with the normal direction of the semiconductor substrate 110. for example, the implantation source of the angled ion implantation may be boron ions, such as BF2 or b¹²-5×10¹³Ions per square centimeter, e.g. 1X 10¹³The included angle α may preferably be 15 ° -45 °, e.g., 30 °. the implantation source for the angled ion implantation may also be one or more of carbon, fluorine, and nitrogen ions the implantation energy may preferably be 4K-20KeV, e.g., 10KeV implant dose may preferably be 1 x 10KeV¹³-1×10¹⁴Ions per square centimeter, e.g. 5X 10¹³Ion/cm included angle α may preferably be 0 ° to 40 °, for example 15 °.

After the tilted ion implantation, an ion implantation region 150 is formed on top of the semiconductor substrate 110. since the implantation direction of the tilted implantation has an angle α with the normal direction of the semiconductor substrate 110, the ion implantation region is also formed under the mask layer 140 and the buffer layer 130, i.e., the ion implantation region is also formed near the trench 160' (fig. 2E) to be formed of the channel.

In this embodiment, the ion implantation region is formed by oblique ion implantation, but the ion implantation region may be formed by another method. For example, the plasma implantation may be performed in a direction having an angle with the normal direction of the semiconductor substrate 110.

Step S3 is executed: and etching the semiconductor substrate by taking the mask layer as a mask to form the groove.

As shown in fig. 2E, the semiconductor substrate 110 is etched using the mask layer 140 having the window 120 as a mask to form a trench 160'. The trench 160' is used to form a subsequent shallow trench isolation structure 160 (fig. 2F). As an example, the trench 160' shown in fig. 2E may be formed using dry etching, and the etching gas may be a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), or the like. The depth of the trench 160' may be determined according to the actual required size of the required shallow trench isolation structure. For example, the depth of the trench 160' may be 50nm to 100 nm.

Step S4 is executed: and filling an isolation material in the groove to form a shallow groove isolation structure.

As shown in fig. 2F, the trench 160' is filled with an isolation material to form a shallow trench isolation structure 160. The isolation material may be an oxide (e.g., HARP), a material with a high dielectric constant (e.g., greater than 3.9), or a combination of the two.

As an example, the isolation material may first be deposited over the entire semiconductor substrate 110. The isolation material may be formed using any of the existing techniques known to those skilled in the art. As an example, the isolation material may be formed by the above-described method of Chemical Vapor Deposition (CVD). Note that the mask layer 140 is also deposited with an isolation material. Then, a chemical mechanical polishing process is performed until the mask layer 140 is exposed.

It should be noted that before filling the isolation material, a liner oxide layer (not shown) may be formed on the sidewalls and the bottom wall of the trench 160 'to improve the adhesion between the isolation material subsequently filled in the trench 160' and the semiconductor substrate 110 and reduce the leakage current. As an example, a thermal oxidation process may be used to form the liner oxide layer.

Step S5 is executed: and removing the mask layer.

As shown in fig. 2G, various etching methods may be used to remove the mask layer 140. Such as dry etching, wet etching, and a combination of dry etching and wet etching. By way of example, the dry etch may be performed with a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBR3), an oxygen-containing gas, an iodine-containing gas, other suitable gases, and/or a plasma to remove the mask layer 140.

Step S6 is executed: performing a subsequent ion implantation on the semiconductor substrate.

As shown in fig. 2H, a subsequent ion implantation is performed on the semiconductor substrate 110 as needed. For example, a well region implant may be performed on the semiconductor substrate 110 to form a well region in the semiconductor substrate. In addition, channel implantation, threshold voltage adjustment implantation, and the like may also be performed on the semiconductor substrate 110 to adjust the threshold voltage of the finally formed semiconductor device.

In summary, according to the manufacturing method of the semiconductor device of the present invention, the ion implantation region can be formed by ion implantation in advance, and the ion implantation region can compensate for the ion implantation dose loss caused by the isolation effect, the annealing effect, and the like at the corner of the channel close to the shallow trench isolation structure, so that the finally formed semiconductor device has stable performance.

In addition, as shown in fig. 2G, the present invention also provides a semiconductor device 100. The semiconductor device 100 is manufactured by a method as illustrated in fig. 1. The semiconductor device 100 mainly includes a semiconductor substrate 110, a shallow trench isolation structure 160, and an ion implantation region 150. The specific structure of the semiconductor device 100 can refer to the description of the corresponding parts above, and is not repeated here for brevity.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate, and forming a mask layer with a window on the semiconductor substrate, wherein the window corresponds to a groove to be formed in the semiconductor substrate;

performing pre-ion implantation, wherein the implantation direction of the pre-ion implantation forms an included angle with the normal direction of the semiconductor substrate so as to form an ion implantation area on the top of the semiconductor substrate; and the implantation source of the previous ion implantation is BF2 or B; the pre-ion implantation is inclined ion implantation, and the included angle is 15-45 degrees;

etching the semiconductor substrate by taking the mask layer as a mask to form the groove;

filling an isolation material in the groove to form a shallow groove isolation structure;

removing the mask layer; and

performing a subsequent ion implantation on the semiconductor substrate.

2. The method of claim 1, wherein the pre-ion implantation has an implantation energy of 2K-40KeV and an implantation dose of 5 x 10¹²-5×10¹³Ions per square centimeter.

3. The method of claim 1, wherein the implantation source of the pre-ion implantation comprises one or more of carbon ions, fluorine ions, and nitrogen ions.

4. The method of claim 3,the implantation energy of the preliminary ion implantation is 4K-20KeV, and the implantation dosage of the preliminary ion implantation is 1 x 10¹³-1×10¹⁴Ions per square centimeter.

5. The method of claim 3, wherein the pre-ion implantation is a tilted ion implantation, and the included angle is 0 ° to 40 °.

6. The method of claim 1, wherein the pre-ion implantation is a plasma implantation.

7. The method of claim 1, wherein the subsequent ion implantation is one or more of a well region implantation, a channel implantation, and a threshold voltage adjustment implantation.

8. A semiconductor device, characterized in that it is manufactured using the method of any of claims 1-7.