CN104465384A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- CN104465384A CN104465384A CN201310438701.9A CN201310438701A CN104465384A CN 104465384 A CN104465384 A CN 104465384A CN 201310438701 A CN201310438701 A CN 201310438701A CN 104465384 A CN104465384 A CN 104465384A
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- preparation
- shallow trench
- doped region
- mask pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a method for manufacturing a semiconductor device. Injection elements with the atomic weights being larger than 100 are injected into the top corner of a shallow trench of a semiconductor substrate. According to the method, the weights of the injection elements at the top corner of the shallow trench are large, escape is not likely to happen, and elements in a shallowly-doped region can be compensated. Moreover, the injection elements are located at the top corner of the shallow trench, the elements in the shallowly-doped region can be stopped from escaping, hence, electric leakage happening for the reason that a device close to the top corner of the shallow trench is started in advance under the condition of being lower than the threshold voltage due to the double-hump effect of the device is reduced or avoided, and the electrical performance of the device is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of preparation method of semiconductor device.
Background technology
The fast development of integrated circuit manufacture process, makes semiconductor device productive set and microminiaturization day by day.And along with the productive set of semiconductor device, the size of the size of semiconductor subassembly and the isolation structure of isolation of semiconductor assembly is also reduced thereupon.Therefore, in manufacture of semiconductor, form good isolation structure and seem very crucial.A kind of common method forming isolation structure forms field oxide (Local Oxidation ofSilicon by selective oxidation, be called for short LOCOS), but, the method is for the high semiconductor device of integration and be not suitable for, problem that same generation beak corrodes (Bird ' s beak encroachment).Therefore, become main flow with shallow trench isolation from (shallow trench isolation is called for short STI) processing procedure at present, be specially adapted to the integrated circuit manufacture process of below time micron.
In the shallow trench isolation technology of prior art, due to shallow trench top corners (corner, the Semiconductor substrate 100 of shallow doped region 110 and trench isolations 120 adjacent region, as border circular areas in Fig. 1) there is no good mellow and full metallization processes process, often appear at the generation of opening caused leaky lower than the device near shallow trench top corners under threshold voltage condition in advance, i.e. the double-hump effect of so-called device.As shown in Figure 1, there is in Semiconductor substrate 100 shallow trench 101, in shallow trench 101, be formed with trench isolations 120.In the Semiconductor substrate 100 of trench isolations 120 both sides, there is shallow doped region 110.For NMOS, adulterate in shallow doped region 110 mainly boron element (B) and compound (BF thereof
2).But, the boron element being arranged in the top corners of described shallow trench 101 can occur to move escape at the shallow plough groove isolation area of subsequent heat treatment technique to low concentration, make the concentration of the boron element of top corners lower than the concentration of boron element in the shallow doped region 110 of other channel part, thus cause easily opening in advance lower than the device near shallow trench top corners under threshold voltage condition and produce electric leakage.
Due to, the concentration being positioned at the doped chemical of the top corners of described shallow trench 101 is lower, cause easily opening in advance lower than the device near shallow trench top corners under threshold voltage condition and produce electric leakage, thus causing the double-hump effect of device serious, affecting the electrical property of device.Therefore, how to provide a kind of preparation method of semiconductor device, can reduce or avoid this electric leakage, improve the electrical property of device, become the problem that those skilled in the art need to solve.
Summary of the invention
The object of the invention is to, a kind of preparation method of semiconductor device is provided, can reduce or avoid the double-hump effect of device, improve the electrical property of device.
For solving the problems of the technologies described above, the invention provides a kind of preparation method of semiconductor device, comprising: the injection element being greater than 100 at the top corners injection atomic weight of the shallow trench of Semiconductor substrate.
Further, the preparation method of described semiconductor device comprises:
Described Semiconductor substrate is provided;
Prepare mask pattern on the semiconductor substrate;
With described mask pattern for mask, carry out ion implantation technology to described Semiconductor substrate, to form heavy element doped region, wherein, the atomic weight of described injection element is greater than 100;
Etching technics is carried out to described Semiconductor substrate, to form described shallow trench in described Semiconductor substrate, and retains the described heavy element doped region of the top corners of described shallow trench.
Further, the material of described mask pattern is oxide or nitride.
Further, the thickness of described mask pattern is 50nm ~ 500nm.
Further, described with described mask pattern for mask, ion implantation technology is carried out to described Semiconductor substrate, to form the step of heavy element doped region, comprising:
With described mask pattern for mask, vertical ion injection technology is carried out to described Semiconductor substrate, form pre-heavy element doped region;
Annealing process is carried out to described pre-heavy element doped region, to form described heavy element doped region;
A side wall is formed at the sidewall of described mask pattern.
Further, the temperature of described annealing process is 800 DEG C ~ 1200 DEG C, and the time of described annealing process is 1h ~ 4h.
Further, the material of described side wall is oxide or nitride.
Further, low-pressure chemical vapour deposition technique is adopted to form a side wall at the sidewall of described mask pattern.
Further, the thickness of described side wall is 5nm ~ 50nm.
Further, the preparation method of described semiconductor device also comprises: in described shallow trench, grow a liner oxide.
Further, the thickness of described liner oxide is 5nm ~ 50nm.
Further, described semiconductor device is NMOS, and described injection element is phosphide element; Or described semiconductor device is PMOS, described injection element is antimony element.
Compared with prior art, the preparation method of semiconductor device provided by the invention has the following advantages:
The preparation method of semiconductor device provided by the invention, at the injection element that the top corners injection atomic weight of the shallow trench of Semiconductor substrate is greater than 100, compared with prior art, the quality of the injection element of the top corners of described shallow trench is larger, not easily escape, can compensate the element of shallow doped region; And, described injection element is positioned at the top corners of described shallow trench, the escape of the element of described shallow doped region can be stopped, thus reduce or avoid, opening caused electric leakage in advance lower than the device near shallow trench top corners incidental under threshold voltage condition, improving the electrical property of device.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of semiconductor device in prior art;
Fig. 2 is the flow chart of the preparation method of semiconductor device in one embodiment of the invention;
Fig. 3-Fig. 9 is the schematic diagram of device architecture in the preparation method of semiconductor device in one embodiment of the invention;
Figure 10 is the schematic diagram of device architecture in the preparation method of semiconductor device in another embodiment of the present invention.
Embodiment
Below in conjunction with schematic diagram, the preparation method to semiconductor device of the present invention is described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, provides a kind of preparation method of semiconductor device, at the injection element that the top corners injection atomic weight of the shallow trench of Semiconductor substrate is greater than 100.In the preparation method of semiconductor device of the present invention, the quality of the injection element of the top corners of described shallow trench is comparatively large, not easily escapes, can compensate the element of shallow doped region; And, described injection element is positioned at the top corners of described shallow trench, the escape of the element of described shallow doped region can be stopped, thus reduce or avoid the double-hump effect of device to cause opening caused electric leakage in advance lower than the device near shallow trench top corners incidental under threshold voltage condition, improve the electrical property of device.
Further, according to above-mentioned core concept, the invention provides a kind of preparation method of semiconductor device, comprising:
Step S11, provides described Semiconductor substrate;
Step S12, prepares mask pattern on the semiconductor substrate;
Step S13, with described mask pattern for mask, carries out ion implantation technology to described Semiconductor substrate, and to form heavy element doped region, wherein, the atomic weight of described injection element is greater than 100;
Step S14, carries out etching technics to described Semiconductor substrate, to form described shallow trench in described Semiconductor substrate, and retains the described heavy element doped region of the top corners of described shallow trench.
Below please refer to the preparation method that Fig. 2 and Fig. 3-Fig. 9 illustrates described semiconductor device, wherein, Fig. 2 is the flow chart of the preparation method of semiconductor device in one embodiment of the invention, and Fig. 3-Fig. 9 is the schematic diagram of device architecture in the preparation method of semiconductor device in one embodiment of the invention.In the present embodiment, described semiconductor device is NMOS.
First, as shown in Figure 2, carry out step S11, step S11, provide described Semiconductor substrate 200, as shown in Figure 3.Wherein, described substrate 200 can be unadulterated monocrystalline substrate, monocrystalline substrate, silicon-on-insulator (SOI) substrate or SiGe (SiGe) substrate etc. doped with impurity, in the present embodiment, described substrate 200 is made up of single crystal silicon material.Described substrate 200 also includes the necessary devices such as source region, and this is the common practise of this area, and therefore not to repeat here.
Then, carry out step S12, described Semiconductor substrate 200 prepares mask pattern.Preferably, first can prepare a sacrificial oxide layer 210 in described Semiconductor substrate 200, prepare a mask layer 220 at described sacrificial oxide layer 210, as shown in Figure 3.Then adopt photoetching process, prepare pattern at described mask layer 220, form mask pattern 220A, as shown in Figure 4.Wherein, the material of described mask pattern 220A is preferably oxide or nitride, and as hardmask (hardmask), but the material of described mask pattern 220A and preparation process are not limited to foregoing description.Wherein, the thickness of described mask pattern 220A is preferably 50nm ~ 500nm, preferably 100nm, 200nm, 300nm etc., but the thickness of described mask pattern 220A is not limited to as 50nm ~ 500nm, as long as the thickness of described mask pattern 220A can blocks ions inject in step s 13, and can in step S14 as etching stop, also within thought range of the present invention.
Then, carry out step S13, with described mask pattern 220A for mask, carry out ion implantation technology to described Semiconductor substrate 200, to form heavy element doped region, wherein, the atomic weight of described injection element is greater than 100.Due in the present embodiment, described semiconductor device is NMOS, so described injection element is preferably phosphide element, but described injection element is not limited to as phosphide element, can also be gallium element, thallium element etc.In the present embodiment, step S13 specifically comprises:
First sub-step: with described mask pattern 220A for mask, carries out vertical ion injection technology to described Semiconductor substrate 200, forms pre-heavy element doped region 230, as shown in Figure 5.Wherein, the degree of depth of ion implantation does not do concrete restriction, is specifically determined by technological parameter, preferably can be suitable with the degree of depth of follow-up shallow doping, such as, when the degree of depth of shallow doping is 50nm, then the degree of depth of the ion implantation of the first sub-step can be 40nm ~ 60nm, preferred 50nm;
Second sub-step: annealing process is carried out to described pre-heavy element doped region 230, to form described heavy element doped region 230A, with make described injection Elemental redistribution ground evenly, as shown in Figure 6.Wherein, the temperature of described annealing process is 800 DEG C ~ 1200 DEG C, and be preferably 100 DEG C, the time of described annealing process is 1h ~ 4h, is preferably 2h.But the temperature and time of described annealing process is not limited to above-mentioned scope;
3rd sub-step: form a side wall 240 at the sidewall of described mask pattern 220A, as shown in Figure 7.Preferably, material be oxide or nitride, well can stop in step S14 etching damage.Low-pressure chemical vapour deposition technique can be adopted to form described side wall 240 at the sidewall of described mask pattern 220A, the uniform described side wall 240 of thickness can be formed.Wherein, the thickness of described side wall 240 is preferably 5nm ~ 50nm, be preferably 10nm, 20nm, 30nm etc., but the thickness of described side wall 240 is not limited to as 5nm ~ 50nm, is specifically determined by the width of shallow trench.In step S14, the existence of described side wall 240 can make the described heavy element doped region 230 of the top corners of described shallow trench 201 well be retained.
In the present embodiment, the order of described second sub-step and the 3rd sub-step does not limit, and can first carry out the 3rd sub-step, then carry out the second sub-step, also within thought range of the present invention.
Step S14, carries out etching technics to described Semiconductor substrate 200, to form described shallow trench 201 in described Semiconductor substrate 200, and retains the described heavy element doped region 230 of the top corners of described shallow trench 201, as shown in Figure 8.The quality of the injection element of the top corners of described shallow trench 201 is comparatively large, not easily escapes, in subsequent technique, can compensate the element of shallow doped region; Further, described injection element is positioned at the top corners of described shallow trench 201, can stop the escape of the element of described shallow doped region, thus the electric leakage reducing or avoid the double-hump effect of device to cause, improve the electrical property of device.
In the present embodiment, after step s 14, also comprise: in described shallow trench 201, grow a liner oxide 250, as shown in Figure 9.Preferably, the thickness of described liner oxide 250 is 5nm ~ 50nm, is preferably 10nm, 20nm, 30nm etc.Described liner oxide 250 can be carried out mellow and fullization process to shallow trench top corners further thus reduce or avoid above-mentioned electric leakage, improves the electrical property of device.
Preferred embodiment of the present invention is described above, but the present invention is not limited to above-described embodiment.Such as, described semiconductor device is not limited to as NMOS, and described semiconductor device can also be PMOS, and when described semiconductor device is PMOS, described injection element can be antimony element; In addition, step S13 is not limited to three sub-steps, step S13 can also be: with described mask pattern 220A for mask, rotation ion implantation technology is carried out to described Semiconductor substrate 200, form pre-heavy element doped region, again after annealed technique, form heavy element doped region 230A, as shown in Figure 10.In Fig. 10, in identical label list diagram 3-Fig. 9 just as region.Adopt the method rotating ion implantation technology, described heavy element doped region 230 can also be formed, also within thought range of the present invention in the top corners of described shallow trench 201.
In sum, the invention provides a kind of preparation method of semiconductor device, the top corners that the preparation method of semiconductor device is included in the shallow trench of Semiconductor substrate injects the injection element that atomic weight is greater than 100.Compared with prior art, the present invention has the following advantages:
The preparation method of semiconductor device provided by the invention, the quality of the injection element of the top corners of described shallow trench is comparatively large, not easily escapes, can compensate the element of shallow doped region; And, described injection element is positioned at the top corners of described shallow trench, the escape of the element of described shallow doped region can be stopped, thus reduce or avoid the double-hump effect of device to cause opening caused electric leakage in advance lower than the device near shallow trench top corners incidental under threshold voltage condition, improve the electrical property of device.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (12)
1. a preparation method for semiconductor device, comprising: the injection element being greater than 100 at the top corners injection atomic weight of the shallow trench of Semiconductor substrate.
2. the preparation method of semiconductor device as claimed in claim 1, it is characterized in that, the preparation method of described semiconductor device comprises:
Described Semiconductor substrate is provided;
Prepare mask pattern on the semiconductor substrate;
With described mask pattern for mask, carry out ion implantation technology to described Semiconductor substrate, to form heavy element doped region, wherein, the atomic weight of described injection element is greater than 100;
Etching technics is carried out to described Semiconductor substrate, to form described shallow trench in described Semiconductor substrate, and retains the described heavy element doped region of the top corners of described shallow trench.
3. the preparation method of semiconductor device as claimed in claim 2, it is characterized in that, the material of described mask pattern is oxide or nitride.
4. the preparation method of semiconductor device as claimed in claim 2, it is characterized in that, the thickness of described mask pattern is 50nm ~ 500nm.
5. the preparation method of semiconductor device as claimed in claim 2, is characterized in that, described with described mask pattern for mask, ion implantation technology is carried out to described Semiconductor substrate, to form the step of heavy element doped region, comprising:
With described mask pattern for mask, vertical ion injection technology is carried out to described Semiconductor substrate, form pre-heavy element doped region;
Annealing process is carried out to described pre-heavy element doped region, to form described heavy element doped region;
A side wall is formed at the sidewall of described mask pattern.
6. the preparation method of semiconductor device as claimed in claim 5, it is characterized in that, the temperature of described annealing process is 800 DEG C ~ 1200 DEG C, and the time of described annealing process is 1h ~ 4h.
7. the preparation method of semiconductor device as claimed in claim 5, it is characterized in that, the material of described side wall is oxide or nitride.
8. the preparation method of semiconductor device as claimed in claim 5, is characterized in that, adopts low-pressure chemical vapour deposition technique to form a side wall at the sidewall of described mask pattern.
9. the preparation method of semiconductor device as claimed in claim 8, it is characterized in that, the thickness of described side wall is 5nm ~ 50nm.
10. as the preparation method of the semiconductor device in claim 1-9 as described in any one, it is characterized in that, the preparation method of described semiconductor device also comprises: in described shallow trench, grow a liner oxide.
The preparation method of 11. semiconductor device as claimed in claim 10, is characterized in that, the thickness of described liner oxide is 5nm ~ 50nm.
The preparation method of 12. semiconductor device as claimed in claim 1, it is characterized in that, described semiconductor device is NMOS, and described injection element is phosphide element; Or described semiconductor device is PMOS, described injection element is antimony element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310438701.9A CN104465384A (en) | 2013-09-23 | 2013-09-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310438701.9A CN104465384A (en) | 2013-09-23 | 2013-09-23 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104465384A true CN104465384A (en) | 2015-03-25 |
Family
ID=52911248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310438701.9A Pending CN104465384A (en) | 2013-09-23 | 2013-09-23 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104465384A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106257672A (en) * | 2015-06-18 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device, semiconductor device and electronic installation |
| CN107689324A (en) * | 2016-08-04 | 2018-02-13 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295663A (en) * | 2007-04-28 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench isolation production method for small size device |
| CN101593681A (en) * | 2008-05-26 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Reduce the method for nmos device gate induced drain leakage current |
| CN101621029A (en) * | 2008-07-03 | 2010-01-06 | 中芯国际集成电路制造(上海)有限公司 | DRAM cell structure with selective anti-narrow width effect and generation method thereof |
| CN101877316A (en) * | 2009-02-05 | 2010-11-03 | 台湾积体电路制造股份有限公司 | Area of isolation injects and structure |
-
2013
- 2013-09-23 CN CN201310438701.9A patent/CN104465384A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101295663A (en) * | 2007-04-28 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench isolation production method for small size device |
| CN101593681A (en) * | 2008-05-26 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Reduce the method for nmos device gate induced drain leakage current |
| CN101621029A (en) * | 2008-07-03 | 2010-01-06 | 中芯国际集成电路制造(上海)有限公司 | DRAM cell structure with selective anti-narrow width effect and generation method thereof |
| CN101877316A (en) * | 2009-02-05 | 2010-11-03 | 台湾积体电路制造股份有限公司 | Area of isolation injects and structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106257672A (en) * | 2015-06-18 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device, semiconductor device and electronic installation |
| CN106257672B (en) * | 2015-06-18 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method, semiconductor device and electronic device |
| CN107689324A (en) * | 2016-08-04 | 2018-02-13 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN107689324B (en) * | 2016-08-04 | 2020-04-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8716090B2 (en) | Semiconductor device manufacturing method | |
| US10573730B2 (en) | Bipolar transistor | |
| CN103545213A (en) | Semiconductor device and method for manufacturing the same | |
| CN102194697A (en) | Method of forming a semiconductor structure | |
| US20100025743A1 (en) | Transistor with embedded si/ge material having enhanced boron confinement | |
| US10134902B2 (en) | PMOS FinFET | |
| CN103426769A (en) | Semiconductor device manufacturing method | |
| US20190067419A1 (en) | Semiconductor devices and fabrication methods thereof | |
| CN106816464B (en) | Method for manufacturing semiconductor device | |
| CN102122643B (en) | Method for manufacturing bipolar junction transistor | |
| US9647086B2 (en) | Early PTS with buffer for channel doping control | |
| US9231079B1 (en) | Stress memorization techniques for transistor devices | |
| CN104465384A (en) | Method for manufacturing semiconductor device | |
| US8377781B2 (en) | Transistor with asymmetric silicon germanium source region | |
| US6323073B1 (en) | Method for forming doped regions on an SOI device | |
| CN106328505B (en) | The forming method of semiconductor structure | |
| CN103794501B (en) | Transistor and forming method thereof | |
| CN103985635B (en) | A kind of preparation method of MOS transistor | |
| CN102446700B (en) | Method for improving silicon substrate | |
| WO2012048624A1 (en) | Method for fabricating small-scale mos device | |
| CN108630535B (en) | Semiconductor structure and forming method thereof | |
| CN108010881B (en) | Method for manufacturing semiconductor device | |
| CN104347471A (en) | Preparation method of semiconductor device | |
| KR100848242B1 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| US8669616B2 (en) | Method for forming N-shaped bottom stress liner |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150325 |
|
| RJ01 | Rejection of invention patent application after publication |