CN107919387A - A kind of semiconductor devices and its manufacture method - Google Patents
A kind of semiconductor devices and its manufacture method Download PDFInfo
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- CN107919387A CN107919387A CN201610884207.9A CN201610884207A CN107919387A CN 107919387 A CN107919387 A CN 107919387A CN 201610884207 A CN201610884207 A CN 201610884207A CN 107919387 A CN107919387 A CN 107919387A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 100
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000002347 injection Methods 0.000 claims abstract description 31
- 239000007924 injection Substances 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims abstract description 31
- 238000002955 isolation Methods 0.000 claims abstract description 26
- 150000002500 ions Chemical class 0.000 claims description 89
- 238000002513 implantation Methods 0.000 claims description 19
- -1 carbon ion Chemical class 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 description 12
- 239000007789 gas Substances 0.000 description 8
- 238000000137 annealing Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- HEDRZPFGACZZDS-UHFFFAOYSA-N Chloroform Chemical compound ClC(Cl)Cl HEDRZPFGACZZDS-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- DIKBFYAXUHHXCS-UHFFFAOYSA-N bromoform Chemical compound BrC(Br)Br DIKBFYAXUHHXCS-UHFFFAOYSA-N 0.000 description 1
- VZGDMQKNWNREIO-UHFFFAOYSA-N carbon tetrachloride Substances ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000021615 conjugation Effects 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- PNDPGZBMCMUPRI-UHFFFAOYSA-N iodine Chemical compound II PNDPGZBMCMUPRI-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229930002839 ionone Natural products 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacture method, the described method includes：Semiconductor substrate is provided；The mask layer with window is formed on the semiconductor substrate, and the window corresponds to groove to be formed in the Semiconductor substrate；Using the mask layer as mask, the Semiconductor substrate is etched to form groove；Isolated material is filled in the trench to form fleet plough groove isolation structure；Remove the mask layer；Advance ion implanting is performed, to form ion implanted regions at fleet plough groove isolation structure at the top of the Semiconductor substrate, the ion implanting in advance is injected for angle-tilt ion；Subsequent ion injection is performed to the Semiconductor substrate to form well region.The performance of semiconductor device that the method provided according to the present invention is formed is stablized.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and manufacture method.
Background technology
In the semiconductor devices of such as metal-oxide-semiconductor, the threshold voltage of raceway groove has the electric property of semiconductor devices very big
Influence.Existing semiconductor devices, in the threshold voltage and raceway groove of the corner portion of the close fleet plough groove isolation structure of raceway groove
Threshold voltage in turn results in that performance of semiconductor device is unstable or even failure there are inconsistent phenomenon.
Therefore, it is necessary to a kind of semiconductor devices and its manufacture method are proposed, to solve existing technical problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features, do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problem of presently, there are, the present invention provides a kind of manufacture method of semiconductor devices.The method
Including：
Semiconductor substrate is provided；
The mask layer with window is formed on the semiconductor substrate, and the window corresponds in the Semiconductor substrate
Groove to be formed；
Using the mask layer as mask, the Semiconductor substrate is etched to form groove；
Isolated material is filled in the trench to form fleet plough groove isolation structure；
Remove the mask layer；
Advance ion implanting is performed, to form ion at fleet plough groove isolation structure at the top of the Semiconductor substrate
Injection zone, the ion implanting in advance are injected for angle-tilt ion；
Subsequent ion injection is performed to the Semiconductor substrate to form well region.
Exemplarily, the injection source of the ion implanting in advance is BF2Or B.
Exemplarily, the Implantation Energy of the ion implanting in advance is 2K-40KeV, the injection of the ion implanting in advance
Dosage is 5 × 1012-5×1013Ion/square centimeter.
Exemplarily, the ion implanting in advance is injected for angle-tilt ion, and direction and the semiconductor of the ion implanting serve as a contrast
The angle of bottom normal direction is 30 ° -50 °.
Exemplarily, the injection source of the ion implanting in advance includes carbon ion, fluorine ion, one kind in Nitrogen ion or more
Kind.
Exemplarily, the Implantation Energy of the ion implanting in advance is 4K-20KeV, the injection of the ion implanting in advance
Dosage is 1 × 1013-1×1014Ion/square centimeter.
Exemplarily, the ion implanting in advance is injected for angle-tilt ion, and direction and the semiconductor of the ion implanting serve as a contrast
The angle of bottom normal direction is 30 ° -50 °.
Exemplarily, the ion implanting in advance is injected for plasma.
Exemplarily, it is p-well that the subsequent ion, which injects formed well region, and the semiconductor devices formed is NMOS devices
Part.
The present invention also provides a kind of semiconductor devices, it is characterised in that the semiconductor devices is using any of the above-described kind of side
Method is made.
The ion implanted regions of semiconductor device according to the invention can make up the close fleet plough groove isolation structure of raceway groove
Corner portion ion due to caused by blanketing effect, annealing effect etc. implantation dosage lose, can cause semiconductor device
The threshold voltage of the raceway groove of part is consistent so that performance of semiconductor device is stablized.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 shows the manufacture method flow chart of semiconductor devices according to the preferred embodiment of the present invention；And
Fig. 2 a-2f show that the manufacture method illustrated in Fig. 1 implements the diagrammatic cross-section of obtained structure successively.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then there is no element or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part are described with term first, second, third, etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to further include to make
With the different orientation with the device in operation.For example, if the device upset in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Existing metal-oxide-semiconductor in the fabrication process, generally requires to make annealing treatment fleet plough groove isolation structure.Apply for human hair
It is existing, due to annealing effect, blanketing effect etc., the ion implantation dosage damage of the corner portion of the close fleet plough groove isolation structure of raceway groove
Lose, so that the threshold voltage of raceway groove is inconsistent, in turn result in that performance of semiconductor device is unstable or even failure.
In order to solve the above problem present in current technique, the present invention provides a kind of manufacturer of semiconductor devices
Method, including：
Semiconductor substrate is provided；
The mask layer with window is formed on the semiconductor substrate, and the window corresponds in the Semiconductor substrate
Groove to be formed；
Using the mask layer as mask, the Semiconductor substrate is etched to form groove；
Isolated material is filled in the trench to form fleet plough groove isolation structure；
Remove the mask layer；
Advance ion implanting is performed, to form ion at fleet plough groove isolation structure at the top of the Semiconductor substrate
Injection zone, the ion implanting in advance are injected for angle-tilt ion；
Subsequent ion injection is performed to the Semiconductor substrate to form well region.
The injection source of the ion implanting in advance is BF2Or B.The Implantation Energy of the ion implanting in advance is 2K-
40KeV, the implantation dosage of the ion implanting in advance is 5 × 1012-5×1013Ion/square centimeter.The ion note in advance
Enter and injected for angle-tilt ion, the direction of the ion implanting and the angle of Semiconductor substrate normal direction are 30 ° -50 °.
The injection source of the ion implanting in advance includes the one or more in carbon ion, fluorine ion, Nitrogen ion.It is described pre-
The Implantation Energy of first ion implanting is 4K-20KeV, and the implantation dosage of the ion implanting in advance is 1 × 1013-1×1014From
Son/square centimeter.The ion implanting in advance is injected for angle-tilt ion, direction and the Semiconductor substrate normal of the ion implanting
The angle in direction is 30 ° -50 °.
The ion implanting in advance is injected for plasma.
It is p-well that the subsequent ion, which injects formed well region, and the semiconductor devices formed is nmos device.
Compared with the prior art, the ion implanted regions of semiconductor device according to the invention can make up the close of raceway groove
The ion of the corner portion of fleet plough groove isolation structure, can since implantation dosage caused by blanketing effect, annealing effect etc. loses
So that the threshold voltage of the raceway groove of semiconductor devices is consistent so that performance of semiconductor device is stablized.
In order to thoroughly understand the present invention, detailed structure and/or step will be proposed in following description, to explain this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this hair
It is bright to have other embodiment.[exemplary embodiment one]
The manufacture method of the semiconductor devices of an embodiment of the present invention is done in detail below with reference to Fig. 1 and Fig. 2 a-2f
Thin description.
First, step 101 is performed：Semiconductor substrate is provided, forms the mask with window on the semiconductor substrate
Layer, the window correspond to groove to be formed in the Semiconductor substrate.
Specifically, in this step, as shown in Figure 2 a, Semiconductor substrate 201 is provided first.The Semiconductor substrate 201
It can be at least one of following material being previously mentioned：Undoped monocrystalline silicon, doped with the monocrystalline silicon of impurity, insulator
Silicon (SSOI) is laminated on silicon (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the composition material of Semiconductor substrate 201
Material selects monocrystalline silicon.
Next, mask layer 203 is formed in Semiconductor substrate 201.Specifically, in the present embodiment, mask
Material layer 203 can be the layer of hard mask material of such as SiN layer.It should be noted that layer of mask material 203 and Semiconductor substrate
Cushioned material layer 202 can also be formed between 201, to discharge the stress between layer of mask material 203 and Semiconductor substrate 201 simultaneously
Increase the combination power between layer of mask material 203 and Semiconductor substrate 201.As an example, cushioned material layer 202 can be SiO2
Layer, thickness can be 100 angstroms -400 angstroms.
Layer of mask material 203 and cushioned material layer 202 can use any existing skill that those skilled in the art are familiar with
Art is formed.Preferably, layer of mask material 203 and cushioned material layer 202 can select the method shape of chemical vapor deposition (CVD)
Into.Such as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition
(RTCVD), plasma enhanced chemical vapor deposition (PECVD) etc..
Then, layer of mask material 203 and cushioned material layer 202 are performed etching, with Semiconductor substrate 201 formed with
Mask layer 203 and cushion 202 with window.The window can be formed by the method for photoetching.Specifically, which can
With including：Photoresist layer is coated by way of spin coating in layer of mask material 203, then implements the works such as exposure, development successively
Skill forms the photoresist layer with pattern of windows, and the window corresponds to groove to be formed in Semiconductor substrate 201.Then
Mask layer 203 and cushioned material layer 202 are performed etching using the photoresist layer with pattern of windows as mask until exposing
Semiconductor substrate 201, removes photoresist layer using cineration technics afterwards.
So far, the mask layer 203 with window is formd in Semiconductor substrate 201, and is led in mask layer 203 and partly
It is also formed with can be used for the cushion 202 for discharging stress between body substrate 201.
Then, step 102 is performed：Using the mask layer as mask, etch semiconductor substrates are to form the groove.
As shown in Figure 2 b, it is mask with above-mentioned patterned mask layer 203, Semiconductor substrate 201 is performed etching, with shape
Into groove 204.Groove 204 is used to form follow-up fleet plough groove isolation structure 204 ' (Fig. 2 c).As an example, dry method can be used
Etching forms groove 204 as shown in Figure 2 b, and etching gas can be fluoro-gas (such as CF4、SF6、CH2F2、CHF3And/or
C2F6) etc..The depth of groove 204 can be determined according to the actual needs size of required fleet plough groove isolation structure.It is exemplary
Ground, the depth of groove 204 can be 50nm-100nm.
Then, step 103 is performed：Isolated material is filled in the trench to form fleet plough groove isolation structure.
As shown in Figure 2 c, isolated material is filled in groove 204, to form fleet plough groove isolation structure 204 '.Isolated material
Can be oxide (such as HARP), the material with high-k (being greater than 3.9) or the combination of the two.
As an example, can the first depositing isolation material in whole Semiconductor substrate 201.Isolated material can use ability
Any prior art that field technique personnel are familiar with is formed.As an example, isolated material can pass through above-mentioned chemical vapor deposition
(CVD) method is formed.It should be noted that similarly deposition has isolated material on mask layer 203.Then chemical machine is performed again
Tool is ground, until exposing the top of mask layer 203.
It should be noted that before isolated material is filled, liner oxidation can be formed in the side wall and bottom wall of groove 204
Layer (not shown), to improve the follow-up conjugation being filled between the isolated material of groove 204 and Semiconductor substrate 201, and drops
Low-leakage current.As an example, thermal oxidation technology can be used to form liner oxide layer.
Then, step 104 is performed：Remove the mask layer.
As shown in Figure 2 d, various lithographic methods can be used to remove mask layer 203.For example, dry etching, wet etching with
And the combination of dry etching and wet etching.As an example, fluoro-gas (such as CF can be passed through4、SF6、CH2F2、CHF3With/
Or C2F6), chlorine-containing gas (such as Cl2、CHCl3、CCl4And/or BCl3), bromine-containing gas (such as HBr and/or CHBr3), it is oxygen-containing
Gas, gas containing iodine, other suitable gases and/or plasma carry out dry etching, to remove mask layer 203.
Then, step 105 is performed：Perform advance ion implanting, with the top of the Semiconductor substrate close to shallow trench
Ion implanted regions are formed at isolation structure, the ion implanting in advance is injected for angle-tilt ion.
As shown in Figure 2 e, angle-tilt ion injection is performed to Semiconductor substrate 201.That is, injection direction and Semiconductor substrate 201
Normal direction between there is angle α.Specifically, can be using part of the fleet plough groove isolation structure of raceway groove side higher than substrate to cover
Film, angle-tilt ion injection is carried out to the region at the fleet plough groove isolation structure of raceway groove opposite side.The angle-tilt ion injection
Injection source can be boron ion, such as BF2Or B.Implantation Energy can preferably be 2K-40KeV, for example, 20KeV.Injection
Dosage can preferably be 5 × 1012-5×1013Ion/square centimeter, for example, 1 × 1013Ion/square centimeter.Angle α is excellent
Selection of land can be 30 ° -50 °, such as 40 °.The injection source of angle-tilt ion injection can also be in carbon ion, fluorine ion, Nitrogen ion
One or more.Implantation Energy can preferably be 4K-20KeV, for example, 10KeV.Implantation dosage can preferably be 1 ×
1013-1×1014Ion/square centimeter, for example, 5 × 1013Ion/square centimeter.Angle α can preferably be 30 ° -50 °, example
Such as 40 °.Exemplarily, mask is formed in PMOS area, ion implanting is performed to NMOS area.
After being injected by angle-tilt ion, ion implanted regions 205 are formd at the top of Semiconductor substrate 201.Due to
Tilting between the injection direction of injection and the normal direction of Semiconductor substrate 201 has angle α, therefore, in shallow trench isolation junction
Structure 204 ' nearby can also form ion implanted regions.Ion implanted regions 205 can make up the close shallow trench isolation junction of raceway groove
The ion of the corner portion of structure 204 ' is lost due to implantation dosage caused by blanketing effect, annealing effect etc..
It should be noted that, although in the present embodiment, inject to form ion implanted regions by angle-tilt ion, but
It is that other methods can also be used to form the ion implanted regions.For example, plasma injects, as long as its injection direction
There is angle with the normal direction of Semiconductor substrate 201.
Then, step 106 is performed：Subsequent ion injection is performed to the Semiconductor substrate.
As shown in figure 2f, according to actual needs, subsequent ion injection is performed to Semiconductor substrate 201.For example, can be half-and-half
Conductor substrate 201 performs well region injection, to form well region 206 in the semiconductor substrate.Exemplarily, the well region is p-well.This
Outside, Channeling implantation, threshold voltage adjustment injection etc. can also be performed to Semiconductor substrate 201, finally formed is partly led with adjusting
The threshold voltage of body device.
So far, the processing step that according to an exemplary embodiment of the present one method is implemented is completed.It is understood that
The present embodiment method, semi-conductor device manufacturing method not only includes above-mentioned steps, before above-mentioned steps, among or may also include afterwards
Other desired step, it is included in the range of this implementation manufacture method.
Compared with the prior art, the manufacture method of semiconductor device according to the invention can be with shape by advance ion implanting
Into ion implanted regions, the ion implanted regions can make up the ion of the corner portion of the close fleet plough groove isolation structure of raceway groove by
The implantation dosage caused by blanketing effect, annealing effect etc. loses, so that finally formed performance of semiconductor device is stablized.
[exemplary embodiment two]
As shown in figure 2f, the present invention also provides a kind of semiconductor devices.Institute's semiconductor devices passes through side as shown in Figure 1
Method manufactures.The semiconductor devices mainly includes Semiconductor substrate 201, fleet plough groove isolation structure 204 ', ion implanted regions 205
And well region 206.The concrete structure of the semiconductor devices is referred to the description of above appropriate section, here for letter
It is clean, repeat no more.
Compared with the prior art, the manufacture method of semiconductor device according to the invention can be with shape by advance ion implanting
Into ion implanted regions, the ion implanted regions can make up the ion of the corner portion of the close fleet plough groove isolation structure of raceway groove by
The implantation dosage caused by blanketing effect, annealing effect etc. loses, so that finally formed performance of semiconductor device is stablized.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
- A kind of 1. manufacture method of semiconductor devices, it is characterised in that the described method includes：Semiconductor substrate is provided；The mask layer with window is formed on the semiconductor substrate, and the window, which corresponds in the Semiconductor substrate, treats shape Into groove；Using the mask layer as mask, the Semiconductor substrate is etched to form groove；Isolated material is filled in the trench to form fleet plough groove isolation structure；Remove the mask layer；Advance ion implanting is performed, to form ion implanting at fleet plough groove isolation structure at the top of the Semiconductor substrate Region, the ion implanting in advance are injected for angle-tilt ion；Subsequent ion injection is performed to the Semiconductor substrate to form well region.
- 2. according to the method described in claim 1, it is characterized in that, the injection source of the ion implanting in advance is BF2Or B.
- 3. according to the method described in claim 2, it is characterized in that, the Implantation Energy of the ion implanting in advance is 2K- 40KeV, the implantation dosage of the ion implanting in advance is 5 × 1012-5×1013Ion/square centimeter.
- 4. according to the method described in claim 2, it is characterized in that, it is described in advance ion implanting for angle-tilt ion injection, it is described The direction of ion implanting and the angle of Semiconductor substrate normal direction are 30 ° -50 °.
- 5. according to the method described in claim 1, it is characterized in that, it is described in advance ion implanting injection source include carbon ion, One or more in fluorine ion, Nitrogen ion.
- 6. according to the method described in claim 5, it is characterized in that, the Implantation Energy of the ion implanting in advance is 4K- 20KeV, the implantation dosage of the ion implanting in advance is 1 × 1013-1×1014Ion/square centimeter.
- 7. according to the method described in claim 5, it is characterized in that, it is described in advance ion implanting for angle-tilt ion injection, it is described The direction of ion implanting and the angle of Semiconductor substrate normal direction are 30 ° -50 °.
- 8. according to the method described in claim 1, it is characterized in that, the ion implanting in advance is injected for plasma.
- 9. according to the method described in claim 1, it is characterized in that, it is p-well that the subsequent ion, which injects formed well region, institute The semiconductor devices of formation is nmos device.
- 10. a kind of semiconductor devices, it is characterised in that the semiconductor devices is using any one of claim 1-9 Method is made.
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| CN111192849A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Method for forming semiconductor structure |
| CN111415936A (en) * | 2020-04-27 | 2020-07-14 | 上海华力微电子有限公司 | Manufacturing method of NAND flash memory |
| WO2022028163A1 (en) * | 2020-08-06 | 2022-02-10 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US12002707B2 (en) | 2020-08-06 | 2024-06-04 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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| WO2022028163A1 (en) * | 2020-08-06 | 2022-02-10 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
| US12002707B2 (en) | 2020-08-06 | 2024-06-04 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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Application publication date: 20180417 |