CN107658260A - The method and semiconductor devices of insulated trench are formed on substrate - Google Patents
The method and semiconductor devices of insulated trench are formed on substrate Download PDFInfo
- Publication number
- CN107658260A CN107658260A CN201710674475.2A CN201710674475A CN107658260A CN 107658260 A CN107658260 A CN 107658260A CN 201710674475 A CN201710674475 A CN 201710674475A CN 107658260 A CN107658260 A CN 107658260A
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- substrate
- insulated trench
- insulating barrier
- region
- trench
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
Abstract
The invention provides one kind to form insulated trench method and semiconductor devices on substrate, wherein, method includes：Insulating barrier is formed in the region of the substrate surface insulated trench to be formed, can be as the bottom of insulated trench, specific thickness can be adjusted correspondingly according to type of device and requirement, it is easier to realize into insulating barrier in substrate surface row, and thickness and regional extent are easier to control, again epitaxial layer is formed in substrate, the structure of epitaxial layer can determine according to semiconductor device type, opening is formed on epitaxial layer again and exposes insulating barrier, it is possible thereby to form insulated trench, compared to prior art, the insulating barrier bottom thickness of control channel bottom can not only be realized, improve Electric Field Distribution, it is implemented without extra equipment and technique, implementation process and realize that technique is simple.
Description
Technical field
The present invention relates to field of chip manufacture technology, and in particular to it is a kind of on substrate formed insulated trench method and
Semiconductor devices.
Background technology
The importance of power semiconductor increasingly highlights under the maintaining sustained and rapid growth of energy demand, is widely applied to
Switching Power Supply, automotive electronics, new energy, power transmission and transformation, track traffic, metallurgy and chemical field.
Power semiconductor uses usually as switch, two key parameters when its conducting resistance and breakdown voltage.Drop
Low on-resistance can reduce the sound state waste lifting switch speed of device, therefore, generally, be reduced using trench gate structure
The conducting resistance of device, wherein Fig. 1 it is exemplary show a kind of structure chart of trench-gate semiconductor, form trench gate structure
Processing step generally comprises：On the first highly doped type substrate 1, the Second-Type drift region 2 of epitaxial growth low-resistivity, pass through
Ion implanting and high-temperature diffusion process form the 3rd type base 3, etching groove, oxide layer 4 are more uniformly grown in groove, are formed
Groove.Although groove is present, larger reduces conducting resistance, in the bar state, corner's (figure of channel bottom
A and A ' places in 1) electric field spike occurs.Trench gate bottom may be caused to puncture.
In the prior art, generally use thickeies bottom oxidization layer or injects III major elements in bottom, due to groove
During growth inside oxide layer, the oxide layer of possible whole groove is thickened, and reduces peak effect unobvious, and only thicken bottom
Or it is complex to bottom injection III major element techniques in groove, it is not easy to realize.More to effectively reduce trench corner
The peak electric field at place, a kind of groove manufacturing method for having buries oxide layer is disclosed in Chinese patent application CN106409898A and is had
The manufacture craft used of body forms N-type region to note phosphorus in N-type silicon substrate, P bases is formed in N-type region note boron, in N-type region bottom
Note energetic oxygen ions and form oxygen buried layer (including the first oxygen buried layer and second oxygen buried layer), form oxide layer through high temperature, make again afterwards
Make trench gate and peripheral structure.In technical scheme used by Chinese patent application CN106409898A, although after
Inject energetic oxygen ions and thicken bottom oxidization layer, the peak electric field at trench corner can be more effectively reduced, still, to N
Type area bottom note energetic oxygen ions need special equipment (energetic oxygen ions injection device) to be injected, and increase tape insulation groove
Semiconductor devices cost of manufacture, make its technique increasingly complex, cost of manufacture is high.
Therefore, how in the semiconductor device the relatively simple formation less groove of peak electric field turns into skill urgently to be resolved hurrily
Art problem.
The content of the invention
The technical problem to be solved in the present invention is the relatively simple formation less ditch of peak electric field in the semiconductor device
Groove.
According in a first aspect, the embodiments of the invention provide a kind of method that insulated trench is formed on substrate, in substrate
Insulating barrier is formed in the region of upper insulated trench to be formed；Epitaxial layer is formed on substrate；Opening is formed on epitaxial layer with sudden and violent
Reveal insulating barrier.
Alternatively, insulating barrier is formed in the region of insulated trench to be formed on substrate, including：It is to be formed exhausted on substrate
Oxide layer is formed in the region of edge groove.
Alternatively, insulating barrier is formed in the region of insulated trench to be formed on substrate, including：It is to be formed exhausted on substrate
The semiconductor layer opposite with the conduction type of substrate is formed in the region of edge groove.
Alternatively, the semiconductor opposite with the conduction type of substrate is formed in the region of insulated trench to be formed on substrate
Layer includes：The region injection of insulated trench to be formed and the element ion of the type opposite types of substrate on to substrate.
Alternatively, after opening is formed on epitaxial layer to expose insulating barrier, in addition to：Opening is aoxidized.
Alternatively, carrying out oxidation to opening includes：Aoxidized under the atmosphere of oxygen with 1100 DEG C of -1150 DEG C of temperature.
According to second aspect, the embodiments of the invention provide a kind of manufacture method of semiconductor devices, including：According to above-mentioned
The method of first aspect any one description forms insulated trench；Make semiconductor device surface structure.
Alternatively, making Semiconductor Surface Structures by Slab includes：The filled media in groove.
Alternatively, filled media includes in groove：The accumulation polysilicon in groove.
Optionally, making Semiconductor Surface Structures by Slab includes：Make front electrode；Make backplate.
The method and semiconductor devices provided in an embodiment of the present invention that insulated trench is formed on substrate, is treated in substrate surface
Formed insulated trench region in form insulating barrier, can as the bottom of insulated trench,
Specific thickness can be adjusted correspondingly according to type of device and requirement, in substrate surface row into insulation
Layer is easier to realize, and thickness and regional extent are easier to control, then forms epitaxial layer, the structure of epitaxial layer in substrate
It can be determined according to semiconductor device type, then form opening on epitaxial layer and expose insulating barrier, it is possible thereby to form insulation
Groove, compared to prior art, the insulating barrier bottom thickness of control channel bottom can be not only realized, improves Electric Field Distribution, it is real
Do not need extra equipment and technique now, implementation process and realize that technique is simple.
Brief description of the drawings
Fig. 1 shows the semiconductor structure in the prior art with insulated trench；
Fig. 2 is shown in the prior art to the semiconductor structure with oxygen buried layer；
Fig. 3 shows insulated trench forming method schematic flow sheet in the embodiment of the present invention；
Fig. 4 shows the intermediate products schematic diagram formed in the embodiment of the present invention on substrate after insulating barrier
Fig. 5 shows the intermediate products schematic diagram after substrate forms epitaxial layer in the embodiment of the present invention；
Fig. 6 shows the intermediate products schematic diagram formed on epitaxial layers of the embodiment of the present invention 30 after opening；
Fig. 7 shows the signal for forming insulated trench in the embodiment of the present invention after opening sidewalls form side wall insulating layer
Figure；
Fig. 8 shows the diagrammatic cross-section of semiconductor devices in the embodiment of the present invention；
Fig. 9 shows the diagrammatic cross-section of FRD in the embodiment of the present invention.
Embodiment
Technical scheme is clearly and completely described below in conjunction with accompanying drawing, it is clear that described implementation
Example is part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, ordinary skill
The every other embodiment that personnel are obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
In addition, term " first ", " second " etc. are only used for describing purpose, and it is not intended that instruction or hint relative importance.
The embodiments of the invention provide a kind of method that insulated trench is formed on substrate, as shown in figure 3, this method bag
Include：
S10. insulating barrier 20 is formed in the region of insulated trench 40 to be formed on the substrate 10.In the particular embodiment,
Alleged substrate 10 can be silicon substrate, or silicon carbide substrates.Wherein the conduction type of substrate 10 can be that N-type can also
For p-type.In the present embodiment, being illustrated by taking N-type silicon substrate as an example, N-type substrate surface carries out V major element ion implantings,
Such as phosphonium ion can be injected, thermal diffusion is then carried out, N- drift regions are formed, specifically, in N-type silicon substrate isolation trench to be formed
The region of groove 40 forms insulating barrier 20, for convenience of preparing, can the insulating barrier 20 of N-type silicon substrate surface formation now, then by region
Outer oxide etch, expose the material of substrate 10.Fig. 4 shows the schematic diagram for forming insulating barrier 20 on the substrate 10.
S20. epitaxial layer 30 is formed on the substrate 10.In the particular embodiment, illustrate, have by taking N-type substrate as an example
Body, in N-type lining surface injection boron ion, the different conductive layer of N-type substrate is formed at, the doping concentration scope of the conductive layer is
1*1017cm-3To 3*1017cm-3.It can also be prepared in the present embodiment with P type substrate, specifically, can be in P type substrate
Phosphonium ion is injected on surface, is formed at the different conductive layer of P type substrate.Fig. 5 shows the signal that epitaxial layer 30 is formed in substrate 10
Figure.
S30. opening 41 is formed on epitaxial layer 30 to expose insulating barrier 20.In specific volume embodiment, on epitaxial layer
Be open the top that 41 positions are insulating barrier 20, wherein, epitaxial layer gluing can be exposed, develop and be etched to by opening mode
Expose insulating barrier 20.Fig. 6 shows the schematic diagram that opening 41 is formed on epitaxial layer 30.
Insulating barrier is formed in the region of substrate surface insulated trench to be formed, can be had as the bottom of insulated trench
The thickness of body can be adjusted correspondingly according to type of device and requirement, be easier in substrate surface row into insulating barrier
Realize, and thickness and regional extent are easier to control, then epitaxial layer is formed in substrate, the structure of epitaxial layer can be according to half
Conductor device type determines, then forms opening on epitaxial layer and expose insulating barrier, it is possible thereby to insulated trench is formed, compared to
Prior art, the insulating barrier bottom thickness of control channel bottom can be not only realized, improve Electric Field Distribution, be implemented without extra
Equipment and technique, implementation process and realize that technique is simple.
In alternatively embodiment, step S10 can also include：The region for forming insulated trench 40 on the substrate 10 is formed
Oxide layer, the thickness of specific oxide layer can be according to the type of device or the purposes decision of device, the oxidation of different thickness
The formation condition of layer is different.In the present embodiment, temperature, time, atmosphere, growth pattern and thickness that oxide layer is formed etc. is no
Limit, it can be adjusted according to type of device and process requirements；Thermal oxide mode can be used in the present embodiment, can also use chemical gas
Mutually the mode of deposition carries out deposition growing into the oxide layer for needing thickness, specifically, can be under oxygen atmosphere with 1100-1200
DEG C condition aoxidized.Or region formation and the conduction type phase of substrate 10 of insulated trench 40 are formed on the substrate 10
Anti- semiconductor layer, specifically, region injection that can be to insulated trench to be formed on substrate and the type opposite types of substrate
Element ion.The condition (element, energy, dosage and angle etc.) of ion implanting is unlimited, and the element type of injection should be with substrate
Type on the contrary, if substrate is N-type, then the element injected should be p-type, and vice versa, and ion implantation dosage can be 1*
1014cm-2Magnitude, depth can be 5-6 μm.In the present embodiment, by taking N-type substrate as an example, can be formed in N-type substrate absolutely
The region implanting p-type element ion of edge groove 40, specifically, can be the III main group ions such as boron.Its doping concentration and doping are thick
Degree can determine according to the type of device or the purposes of device.The region shape of insulated trench 40 can also be being formed on the substrate 10
Into other insulating barriers 20.
The side wall of insulated trench 40 is side wall insulating layer 42, and Fig. 7 is shown forms side wall insulating layer 42 in opening sidewalls
Schematic diagram.In an alternate embodiment of the invention, can also include in step S20：Opening is aoxidized, in the particular embodiment,
The oxidizing condition temperature aoxidized that is open is preferably 1100-1150 DEG C, and oxidizing atmosphere is preferably oxygen, and thickness is preferablyOpening sidewalls can also grow other insulating barriers.In the present embodiment, first to the insulating barrier of insulated trench 40
20 are prepared, then carry out outer layer growth, form a buried structure, then carry out groove preparation, can improve isolation trench
During 40 bottom Electric Field Distribution of groove, other performances of groove are not influenceed, and technique is simple, it is easy to accomplish.
The embodiment of the present invention additionally provides the manufacture method of semiconductor devices, the section of semiconductor devices as shown in Figure 8
Schematic diagram, the method for now implementing to prepare insulated trench 40 in above-described embodiment on the substrate 10, forms insulated trench 40, in shape again
Surface texture is made on into the epitaxial layer and substrate 10 of insulated trench 40.In the particular embodiment, alleged semiconductor devices can
Think IGBT, can be any one in DMOS, LDMOS and FRD (rapidly switching off diode).By taking IGBT as an example, IGBT
Manufacture method includes：Insulating barrier 20 is formed in the region of insulated trench 40 to be formed on the substrate 10, is N-type substrate with substrate 10
Exemplified by；Epitaxial layer 30 is formed on the substrate 10, and accumulation can be included in N-type substrate doped with three major elements by forming epitaxial layer
The semi-conducting material of ion, III major element ions can also be injected on surface, such as inject boron ion, form P- bases 31,
Opening is formed on epitaxial layer to expose insulating barrier 20, opening is aoxidized, insulated trench 40 is formed, by insulated trench 40
Side carries out N+ injections, forms source electrode 32.The depositing polysilicon 43 in insulated trench 40, in positive accumulation front metal 40, front
Metal can include but is not limited to aluminium, overleaf carry out ion implanting and anneal to form colelctor electrode 60, the ion of injection can be
The III major element ions such as boron, P+ colelctor electrodes are formed, in P+ colelctor electrode surface depositions back metal 70, back metal 70 can be with
Including but not limited to aluminium.In IGBT preparation method, N-type substrate can be replaced by P type substrate, other corresponding conductive layers
The conduction type of other conductive layers of conduction type with N-type substrate is opposite.Wherein, DMOS and LDMOS preparation method and IGBT systems
Preparation Method is similar, repeats no more in the present embodiment.
FRD preparation method, Fig. 9 shows FRD profile, and by taking N-type substrate as an example, it makes the side of insulated trench 40
Method is identical with the method that insulated trench 40 is made in IGBT, and the method for forming insulated trench 40 may be referred to retouch in above-described embodiment
The method for the formation insulated trench 40 stated.In FRD, alleged insulated trench 40 can include termination environment groove 44 and active area ditch
Groove 45, in the present embodiment, the insulated trench 40 of making can be active area groove 45, and in the present embodiment, epitaxial layer 30 can
Including p-type doped region 33, the accumulation oxide 34 on p-type doped region, the oxide etching above by active groove 45, to protect
The oxide 34 above the groove of termination environment is stayed, front metal 50 is deposited above active groove, overleaf deposits back metal 70.
Although being described in conjunction with the accompanying embodiments of the present invention, those skilled in the art can not depart from this hair
Various modification can be adapted in the case of bright spirit and scope and modification, and such modifications and variations are each fallen within by appended claims
Within limited range.
Claims (10)
- A kind of 1. method that insulated trench is formed on substrate, it is characterised in that including：Insulating barrier is formed on the region of the insulated trench to be formed of the substrate；Epitaxial layer is formed on the substrate；Opening is formed on said epitaxial layer there with the exposure insulating barrier.
- 2. the method for insulated trench is formed on substrate as claimed in claim 1, it is characterised in that described in the substrate Insulating barrier is formed on the region of the insulated trench to be formed, including：Ion implanting is carried out to the region of the insulated trench to be formed, wherein the conduction type of the ion injected and institute The conduction type for stating substrate is opposite.
- 3. the method for insulated trench is formed on substrate as claimed in claim 2, it is characterised in that the ion of the injection Implantation dosage is 1*1014cm-2-3*1014cm-2。
- 4. the method for insulated trench is formed on substrate as claimed in claim 1, it is characterised in that described in the substrate Insulating barrier is formed on the region of the insulated trench to be formed, including：In the area deposition or painting insulating layer coating of the insulated trench to be formed.
- 5. the method for insulated trench is formed on substrate as claimed in claim 1, it is characterised in that described in the substrate Insulating barrier is formed on the region of the insulated trench to be formed, including：The substrate is aoxidized to form oxide layer；Remove the oxide layer outside the region of the insulated trench to be formed.
- 6. the method that insulated trench is formed on substrate as any one of claim 1-5, it is characterised in that described After opening is formed on epitaxial layer with the exposure insulating barrier, in addition to：The opening is aoxidized.
- 7. the method that insulated trench is formed on substrate as described in claim 4 or 5, it is characterised in that the oxidation exists Carried out at a temperature of 1100 DEG C -1150 DEG C.
- 8. the method for insulated trench is formed on substrate as claimed in claim 7, it is characterised in that the thickness of the oxide layer For
- A kind of 9. semiconductor devices with insulated trench, it is characterised in that：Method of the insulated trench according to claim 1-8 any one is formed.
- 10. having the semiconductor devices of insulated trench as claimed in claim 9, the semiconductor devices includes：IGBT、MOS Manage or rapidly switch off any one in diode or any combination.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710674475.2A CN107658260A (en) | 2017-08-08 | 2017-08-08 | The method and semiconductor devices of insulated trench are formed on substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710674475.2A CN107658260A (en) | 2017-08-08 | 2017-08-08 | The method and semiconductor devices of insulated trench are formed on substrate |
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| Publication Number | Publication Date |
|---|---|
| CN107658260A true CN107658260A (en) | 2018-02-02 |
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|---|---|---|---|
| CN201710674475.2A Pending CN107658260A (en) | 2017-08-08 | 2017-08-08 | The method and semiconductor devices of insulated trench are formed on substrate |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6391699B1 (en) * | 2000-06-05 | 2002-05-21 | Fairchild Semiconductor Corporation | Method of manufacturing a trench MOSFET using selective growth epitaxy |
| CN104247026A (en) * | 2012-04-19 | 2014-12-24 | 株式会社电装 | Silicon carbide semiconductor device and method for manufacturing same |
| WO2017064949A1 (en) * | 2015-10-16 | 2017-04-20 | 富士電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
-
2017
- 2017-08-08 CN CN201710674475.2A patent/CN107658260A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6391699B1 (en) * | 2000-06-05 | 2002-05-21 | Fairchild Semiconductor Corporation | Method of manufacturing a trench MOSFET using selective growth epitaxy |
| CN104247026A (en) * | 2012-04-19 | 2014-12-24 | 株式会社电装 | Silicon carbide semiconductor device and method for manufacturing same |
| WO2017064949A1 (en) * | 2015-10-16 | 2017-04-20 | 富士電機株式会社 | Semiconductor device and method for manufacturing semiconductor device |
Non-Patent Citations (1)
| Title |
|---|
| 谈永胜、方泽波: "《集成电路工艺实验》", 30 April 2015, 电子科技大学出版社 * |
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Address after: 102209 18 Riverside Avenue, Changping District science and Technology City, Beijing Applicant after: Global energy Internet Institute, Inc. Applicant after: State Grid Corporation of China Applicant after: Electric Power Research Institute of State Grid Shandong Electric Power Company Address before: 102209 18 Riverside Avenue, Changping District science and Technology City, Beijing Applicant before: Global energy Internet Institute, Inc. Applicant before: State Grid Corporation of China Applicant before: Electric Power Research Institute of State Grid Shandong Electric Power Company |
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Application publication date: 20180202 |