CN107643991B

CN107643991B - Data processing chip and system, and data storing and forwarding processing method

Info

Publication number: CN107643991B
Application number: CN201710869045.6A
Authority: CN
Inventors: 桂文明
Original assignee: Beijing Suneng Technology Co ltd
Current assignee: Beijing Suneng Technology Co ltd
Priority date: 2017-09-22
Filing date: 2017-09-22
Publication date: 2023-09-19
Anticipated expiration: 2037-09-22
Also published as: CN107643991A

Abstract

The embodiment of the invention discloses a data processing chip, a system and a data storage forwarding processing method, wherein the data processing chip comprises a data processing unit and at least one interconnection storage controller, the at least one interconnection storage controller comprises a first interconnection storage controller and a second interconnection storage controller, the data processing unit is respectively connected with each interconnection storage controller in the at least one interconnection storage controller, each interconnection storage controller is respectively correspondingly connected to a memory, and the data processing chip reads and writes data to the memory through the interconnection storage controller and realizes data exchange with other data processing chips. The embodiment of the invention reduces the cost of the data processing chip, the realization difficulty and cost of the data processing system and the complexity and time of data processing.

Description

Data processing chip and system, and data storing and forwarding processing method

Technical Field

The invention relates to a data processing technology, in particular to a data processing chip and system and a data storing and forwarding processing method.

Background

Typical data processing systems require a large memory, and in particular, data processing systems in deep learning require a larger memory. The cost of the external memory such as DDR (double rate synchronous dynamic random access memory) 3, DDR4, GDDR (graphic double rate synchronous dynamic random access memory), HBM (high bandwidth memory) is much lower than that of the on-chip high speed memory such as SRAM (static random access memory), so the data processing chip generally has an external high speed memory which is exclusive, a memory controller is disposed in the corresponding data processing chip, and the data processing chip reads and writes data in the external memory through the memory controller.

Along with the increasing complexity of data processing tasks, the data volume to be processed is increased, the time required for completing the data processing tasks is shortened, and a plurality of data processing chips are required to jointly process massive data. Each data processing chip is required to be internally provided with an interconnection controller, the data processing chips exchange data with other data processing chips through the built-in interconnection controllers, and the interconnection controllers in the two data processing chips are connected together through a communication medium to exchange data.

In carrying out the invention, the inventors have found through research that existing data processing systems have at least the following problems:

in the existing data processing system with multiple interconnected data processing chips, the storage controller and the interconnection controller are independently arranged, and the storage controller and the interconnection controller are arranged in the data processing chip, so that the cost of the data processing chip is increased;

because the IO (input/output) pins of the external memory and the IO pins of the interconnection controller are independently arranged, the data processing system has high IO pin density, so that the complexity of a PCB (printed circuit board) is high, the realization difficulty and cost of the data processing system are increased, and the reliability of the data processing system is reduced;

The external memories are exclusive and private of the data processing chips, and each data processing chip stores data in the corresponding external memory, so that the utilization rate of the storage space of the memory is reduced; in addition, when one data processing chip needs to use the data of other data processing chips, the other data processing chip needs to read the data from the private external memory, and then the data is transferred to the current data processing chip through the interconnection controller of the two data processing chips, so that the complexity and time of data processing are increased.

Disclosure of Invention

The embodiment of the invention provides a data processing system implementation scheme for interconnecting multiple data processing chips.

According to one aspect of the embodiment of the invention, a data storage forwarding processing method in a data processing system is provided, wherein the data processing system comprises at least one memory and at least two data processing chips, and the memory and the data processing chips are sequentially connected at intervals to form one-dimensional connection; each data processing chip comprises at least one interconnection memory controller, and is connected with a memory through the interconnection memory controller; the at least one memory includes a first memory;

When a first data processing chip in the at least two data processing chips needs to store data to a target memory or needs to send data to a second data processing chip in the at least two data processing chips, the first data processing chip sends a request message to a first memory connected with a first interconnection memory controller through the first interconnection memory controller in the first data processing chip, wherein the request message comprises data to be processed, a receiver identifier and a sender identifier, the receiver identifier uniquely identifies one receiver in the data processing system, the receiver comprises the data processing chip and the memory, and the sender identifier uniquely identifies one data processing chip in the data processing system;

the first memory identifies whether the receiver identification is an identification of the first memory;

if the receiver identifier is the identifier of the first memory, the first memory stores the data to be processed;

otherwise, if the receiver identifier is not the identifier of the first memory, forwarding the request message forward by the first memory to a second interconnection memory controller in a second data processing chip connected to the first memory at the same time;

The second data processing chip identifies whether the receiver identifies the identity of the second data processing chip;

if the receiver identifier is the identifier of the second data processing chip, the second data processing chip reads the data to be processed so as to process the data;

otherwise, if the receiver identifier is not the identifier of the second data processing chip, the second data processing chip forwards the request message to a second memory connected to a third interconnection memory controller in the second data processing chip at the same time;

and taking the second memory as the new first memory, executing the operation that the first memory recognizes whether the receiver identifier is the identifier of the first memory or not until the receiver identifier is the identifier of the current receiver, and storing the data to be processed by the memory serving as the current receiver or reading the data to be processed by the data processing chip serving as the current receiver for processing.

Optionally, in each of the above method embodiments of the present invention, the method further includes:

the first data processing chip records and stores the identification of the receiving party of the data to be stored.

Optionally, in the foregoing method embodiments of the present invention, in response to a first data processing chip of the at least two data processing chips needing to store data into a target memory, the first data processing chip sends, through a first interconnection memory controller in the first data processing chip, a request message to a first memory connected to the first interconnection memory controller, including: when a first data processing chip in the at least two data processing chips needs to store data to a target memory, the first data processing chip sets the working state of the first interconnection memory controller to be a data writing state through a data processing unit in the first data processing chip, and sends the request message to the first interconnection memory controller; the first interconnection storage controller sends the request message to the connected first storage;

the first memory stores the data to be processed, including: the first memory stores the data to be processed in a storage unit in the first memory.

Optionally, in the above embodiments of the present invention, before sending a request message to the first interconnect storage controller, the method further includes:

The data processing unit in the first data processing chip determines that the data type of the data to be processed is shared data or private data, and the request message also comprises a data type identifier, wherein the data type identifier is used for identifying that the data type is shared data or private data;

the first memory stores the data to be processed in a storage unit in the first memory, including:

and the first memory stores the data to be processed in a corresponding storage area in the storage unit according to the data type identifier in the request message.

Optionally, in the foregoing method embodiments of the present invention, the storing, by the first memory, the data to be processed in a corresponding storage area in the storage unit according to the data type identifier in the request message includes:

according to the data type identifier in the request message, if the data type of the data to be processed is private data, the first memory stores the data to be processed in the storage unit and is pre-allocated to a first storage area of the first data processing chip;

and if the data type of the data to be processed is shared data, the first memory stores the data to be processed in a shared memory area in the memory unit.

Optionally, in the above embodiments of the present invention, when a first data processing chip of the at least two data processing chips needs to store data into a target memory, the method further includes: the data processing unit in the first data processing chip determines a target memory of the data to be processed and a target storage area in the target memory according to the pre-configuration, acquires the identification of the target memory and the identification of the target storage area, and takes the identification of the target memory as the identification of the receiver; the request message also comprises an identifier of the target storage area;

the first memory stores the data to be processed in a storage unit in the first memory, including: and the first memory stores the data to be processed in the target storage area in the first memory according to the identification of the target storage area.

in response to the first data processing chip needing to read data from a receiver, a data processing unit in the first data processing chip sets a working state of a first interconnection storage controller connected to the receiver to be a data reading state, and sends a data reading request message to the first memory through the first interconnection storage controller, wherein the reading request message comprises a sender identifier and a receiver identifier, and the sender identifier is an identifier of the first data processing chip;

if the receiver identifier is the identifier of the first memory, the first memory acquires the data requested by the data reading request message from the first memory, and returns the data requested by the data reading request message to the first interconnection storage controller; the first interconnection storage controller forwards the data requested by the data reading request message to a data processing unit in the first data processing chip;

otherwise, if the receiver identifier is not the identifier of the first memory, forwarding the data reading request message forward to a second data processing chip connected to the first memory at the same time by the first memory;

if the receiver identifier is the identifier of the second data processing chip, the second data processing chip acquires the data requested by the data reading request message and transmits the data to the first memory along the reverse direction of the data reading request message; the first memory returns the data requested by the data reading request message to the first interconnection memory controller; the first interconnection storage controller forwards the data requested by the data reading request message to a data processing unit in the first data processing chip;

Otherwise, if the receiver identifier is not the identifier of the second data processing chip, forwarding the data reading request message forward to a second memory connected to the second data processing chip at the same time by the second data processing chip;

taking the second memory as the new first memory, executing the operation that the first memory identifies whether the receiver identifier is the identifier of the first memory or not until the current receiver identifier is the identifier of the current receiver, acquiring the data requested by the data reading request message by the current receiver, and transmitting the data requested by the data reading request message to the first memory along the reverse transmission path of the data reading request message; the first memory returns the data requested by the data reading request message to the first interconnection memory controller; the first interconnect memory controller forwards the data requested by the data read request message to a data processing unit in the first data processing chip.

Optionally, in the above embodiments of the present invention, the receiving party is a memory, and the data reading request message further includes a data type identifier, where the data type identifier is used to identify that the data type is shared data or private data;

The first memory obtaining the data requested by the data read request message from the first memory, including:

if the data type identified by the identifier in the data reading request message is private data, the first memory reads the storage data requested by the data reading request message from a first storage area pre-allocated to the first data processing chip in a storage unit in the first memory;

and if the data type identified by the identification in the data reading request message is shared data, the first memory reads the storage data requested by the request from the shared storage area in the storage unit in the first memory.

Optionally, in the above method embodiments of the present invention, the first data processing chip needs to read data from a receiving side, including:

the first data processing chip determines a memory in which data to be read are located and a memory area in the memory as a target memory and a target memory area respectively, and acquires an identifier of the target memory and an identifier of the target memory area, wherein the identifier of the receiver is an identifier of the target memory; the data reading request message also comprises an identifier of the target storage area;

and the first memory reads the data requested by the data reading request message from the target storage area in the first memory according to the identification of the target storage area.

Optionally, in the above embodiments of the present invention, in response to a first data processing chip of the at least two data processing chips needing to send data to a second data processing chip of the at least two data processing chips, the first data processing chip sends, through a first interconnection memory controller in the first data processing chip, a request message to a first memory connected to the first interconnection memory controller, including:

and when a first data processing chip in the at least two data processing chips needs to send data to a second data processing chip in the at least two data processing chips, the data processing unit in the first data processing chip sets the working state of the first interconnection memory controller to be a data exchange state, and sends the request message to the first memory through the first interconnection memory controller.

Optionally, in the foregoing embodiments of the present invention, the memory includes a plurality of storage interfaces, each storage interface is correspondingly connected to an interconnection storage controller in a different data processing chip, a request message sent by the connected interconnection storage controller is received through one storage interface in the plurality of storage interfaces, and the request message is sent to the interconnection storage controller in the data processing chip connected to the other storage interface through the other storage interface in the plurality of storage interfaces.

According to another aspect of the embodiment of the present invention, there is provided a data processing chip, where the data processing chip includes a data processing unit and at least one interconnection memory controller, one of the data processing units is connected to each interconnection memory controller in the at least one interconnection memory controller, and each interconnection memory controller is correspondingly connected to a memory; wherein:

the data processing unit is used for sending a request message to a memory connected with one interconnection memory controller through one interconnection memory controller when data is required to be stored in a target memory or data is required to be sent to another data processing chip, wherein the request message comprises data to be processed, a receiver identifier and a sender identifier, the receiver identifier uniquely identifies a receiver chip in the data processing system, the receiver chip comprises the data processing chip and the memory, and the sender identifier uniquely identifies a data processing chip in the data processing system; and in response to receiving a request message via the interconnect memory controller, identifying whether a recipient identification in the request message is an identification of the data processing chip; if the identification of the receiving party in the request message is the identification of the data processing chip, reading the data to be processed for processing; otherwise, if the identification of the receiving party in the request message is not the identification of the data processing chip, forwarding the request message to another memory connected to the data processing chip at the same time through another interconnection memory controller;

And the interconnection storage controller is connected to one memory and used for forwarding the request message sent by the data processing unit to the connected memory.

Optionally, in the above-mentioned chip embodiments of the present invention, the data processing unit is further configured to determine, before sending the request message to the one interconnection storage controller, that the data to be processed is shared data or private data, where the request message further includes a data type identifier, where the data type identifier is used to identify that the data type is shared data or private data; and setting the working state of the interconnected storage controllers to be a data writing state.

Optionally, in the above-mentioned chip embodiments of the present invention, the data processing unit is specifically configured to determine, according to a preset configuration, a target memory for storing the data to be processed and a target storage area in the target memory, and obtain an identifier of the target memory and an identifier of the target storage area, where the identifier of the target memory is used as the identifier of the receiver; the request message also comprises an identifier of the target storage area; and setting the working state of the interconnected storage controllers to be a data writing state.

Optionally, in the above embodiments of the present invention, the data processing unit is specifically configured to set a working state of the one interconnection storage controller to a data exchange state when data needs to be sent to the other data processing chip, and send the exchange data to the one memory through the one interconnection storage controller.

Optionally, in the above-mentioned chip embodiments of the present invention, the data processing unit is further configured to set a working state of an interconnection storage controller connected to a receiver to be a data reading state when data is required to be read from the receiver, and send a data reading request message to the memory through the interconnection storage controller, where the reading request message includes a sender identifier and a receiver identifier, and the sender identifier is an identifier of the data processing chip;

the interconnection storage controller is further configured to receive the storage data requested by the data read request message returned by the memory, and forward the storage data requested by the data read request message to the data processing unit.

Optionally, in the above chip embodiments of the present invention, the data read request message further includes a data type identifier, where the data type identifier is used to identify that the data type is shared data or private data.

Optionally, in the above-mentioned chip embodiments of the present invention, the data processing unit is specifically configured to determine, when data needs to be read from the receiving side, a memory in which the data needs to be read is located and a storage area in the memory are respectively used as a target memory and a target storage area, and obtain an identifier of the target memory and an identifier of the target storage area, where the receiving side identifier is specifically an identifier of the target memory; the request message also includes an identification of the target storage area.

According to a further aspect of an embodiment of the present invention, there is provided a data processing system comprising: the memory and the data processing chips are sequentially connected at intervals to form one-dimensional connection; each data processing chip comprises at least one interconnection memory controller, and is connected with a memory through the interconnection memory controller; the at least one memory includes a first memory; the at least two data processing chips comprise a first data processing chip and a second data processing chip; at least one interconnection memory controller in the first data processing chip comprises a first interconnection memory controller, and is connected with the first memory through the first interconnection memory controller; at least one interconnection memory controller in the second data processing chip comprises the second interconnection memory controller, and is connected with the first memory through the second interconnection memory controller;

The first data processing chip is used for sending a request message to the first memory through the first interconnection storage controller when data is required to be stored in the target memory or data is required to be sent to a second data processing chip in the at least two data processing chips, the request message comprises data to be processed, a receiver identifier and a sender identifier, the receiver identifier uniquely identifies a receiver in the data processing system, the receiver comprises the data processing chip and a memory, and the sender identifier uniquely identifies the data processing chip in the data processing system;

the first memory is used for identifying whether the receiver identification is the identification of the first memory; if the identification of the receiver is the identification of the first memory, storing the data to be processed; if the receiver identifier is not the identifier of the first memory, forwarding the request message forward to a second interconnection memory controller in a second data processing chip connected to the first memory at the same time;

the second data processing chip is used for identifying whether the receiver identification is the identification of the second data processing chip; if the identification of the receiving party is the identification of the second data processing chip, reading the data to be processed for processing; otherwise, if the receiver identifier is not the identifier of the second data processing chip, forwarding the request message to a second memory connected to the third interconnection memory controller at the same time through the third interconnection memory controller in the second data processing chip.

Optionally, in the above system embodiments of the present invention, the data processing chip includes a data processing chip according to any one of the above embodiments of the present invention.

Optionally, in the above system embodiments of the present invention, the first memory includes: the system comprises a switching center unit, a storage unit and more than two storage interfaces, wherein each storage interface is respectively connected with an interconnection storage controller in a data processing chip;

the switching center unit is configured to receive the request message through a first storage interface connected to the first interconnection storage controller among the two or more storage interfaces, and identify whether the receiver identifier is an identifier of the first storage; if the receiver identifier is the identifier of the first memory, storing the data to be processed in the request message in the storage unit; if the receiver identifier is not the identifier of the first memory, forwarding the request message to the second interconnection memory controller in the second data processing chip connected to the first memory through a second memory interface connected with the second interconnection memory controller in the more than two memory interfaces; receiving the data reading request message through a first storage interface connected with the first interconnection storage controller in the more than two storage interfaces, and identifying whether a receiver identifier in the data reading request message is an identifier of the first storage; if the identification of the receiving party in the data reading request message is the identification of the first memory, acquiring the data requested by the data reading request message from the storage unit, and returning the data requested by the data reading request message to the first interconnection storage controller; otherwise, if the identifier of the receiving party in the data reading request message is not the identifier of the first memory, forwarding the request message to the second interconnection memory controller through the second memory interface; the storage unit is used for storing data.

Optionally, in the above system embodiments of the present invention, the storage unit includes: a private storage area and a shared storage area;

the private storage area comprises a plurality of storage areas which are respectively allocated to each data processing chip in advance;

the request message also comprises a data type identifier of the data to be processed, wherein the data type identifier is used for identifying whether the data type is shared data or private data;

the switching center unit is specifically configured to store the data to be processed in a first storage area pre-allocated to the first data processing chip, if the data type of the data to be processed is private data according to the data type identifier; and if the data type of the data to be processed is shared data, storing the data to be processed in the shared storage area.

Optionally, in the above embodiments of the present invention, the data read request message further includes a data type identifier, where the data type identifier is used to identify that the data type is shared data or private data;

the switching center unit is specifically configured to, when acquiring the data requested by the data read request message from the storage unit according to the read request message, read the storage data requested by the data read request message from a storage area pre-allocated to the first data processing chip if the data type of the data is private data according to the data type identifier; and if the data type of the data is shared data, reading the storage data requested by the request from the shared storage area.

Optionally, in the above system embodiments of the present invention, the memory includes: the system comprises a switching center unit, a storage unit and more than two storage interfaces, wherein each storage interface is respectively connected with an interconnection storage controller in a data processing chip;

the memory cell includes: the private storage area and the shared storage area are used for storing data; the private storage area comprises a plurality of storage areas which are respectively allocated to each data processing chip in advance, and each storage area is uniquely identified through the identification of the storage area;

the request message also comprises an identifier of the target storage area;

the switching center unit is configured to receive the request message through a first storage interface connected to the first interconnection storage controller among the two or more storage interfaces, and identify whether the receiver identifier is an identifier of the first storage; if the receiver identifier is the identifier of the first memory, storing the storage data in the target storage area in the storage unit according to the identifier of the target storage area; if the receiver identifier is not the identifier of the first memory, forwarding the request message to a second interconnection memory controller connected to the memory at the same time through a second memory interface connected to the second interconnection memory controller in the second data processing chip in the more than two memory interfaces; receiving the data reading request message through a first storage interface connected with the first interconnection storage controller in the more than two storage interfaces, and identifying whether the receiver identifier is an identifier of the first storage; if the receiver identifier is the identifier of the first memory, acquiring the data requested by the data reading request message from the storage unit, and returning the data requested by the data reading request message to the first interconnection storage controller; otherwise, if the receiver identifier is not the identifier of the first memory, forwarding the request message to the second interconnection memory controller through the second memory interface.

Optionally, in the above system embodiments of the present invention, the memory includes: hybrid memory cube dynamic random access memory HMC DRAM, static random access memory SRAM, field programmable gate array FPGA, application specific integrated circuit ASIC, or multi-port hard disk.

Optionally, in the above system embodiments of the present invention, the interconnect memory controller is connected to the memory through a serializer/deserializer SERDES, ethernet, or bus and interface standard PCIE.

Based on the data processing chip, the system and the data storage forwarding processing method provided by the embodiment of the invention, an interconnection storage controller is arranged in the data processing chip, the data processing chip is connected with a memory through the interconnection storage controller, the data in the memory is read and written through the interconnection storage controller, and the data exchange with other data processing chips is realized through the interconnection storage controller and the memory. Compared with the corresponding technology, the embodiment of the invention has the following beneficial technical effects:

the memory controller and the interconnection controller are not required to be independently arranged, so that the cost of the data processing chip is reduced, the IO pin density is reduced, the complexity of a PCB (printed circuit board) is reduced, the implementation difficulty and the cost of a data processing system are reduced, and the reliability of the data processing system is improved;

All the data processing chips can share the storage space of the memory, when one data processing chip reads the data stored by other data processing chips from one memory, the data can be directly read from the memory without the need of reading the data from the memory by the other data processing chips storing the data and then forwarding the data to the current data processing chip, thereby improving the utilization rate of the storage space and reducing the complexity and time of data processing.

The technical scheme of the invention is further described in detail through the drawings and the embodiments.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

The invention may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a data processing system according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a data processing chip according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of an embodiment of a memory cell according to an embodiment of the present invention.

Fig. 4 is a flowchart of an embodiment of a data store-and-forward processing method according to the present invention.

Fig. 5 is a flowchart of another embodiment of the data store-and-forward processing method of the present invention.

FIG. 6 is a flowchart of one embodiment of reading data from a receiving side by a first data processing chip according to an embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.

Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description.

The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

Embodiments of the invention are operational with numerous other general purpose or special purpose computing system environments or configurations with electronic devices, such as terminal devices, computer systems/servers, etc. Examples of well known terminal devices, computing systems, environments, and/or configurations that may be suitable for use with the terminal device, computer system/server, or other electronic device include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, mainframe computer systems, and distributed cloud computing technology environments that include any of the foregoing, and the like.

An electronic device such as a terminal device, computer system/server, etc., may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform particular tasks or implement particular abstract data types. The computer system/server may be implemented in a distributed cloud computing environment in which tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computing system storage media including memory storage devices.

In the embodiments of the present invention, the words "first", "second", and the like are used only to distinguish whether or not they are the same object, and are not used to distinguish structures inside the object. In each embodiment of the invention, the data processing chip adopts the same structure, and the memory also adopts the same structure.

FIG. 1 is a schematic diagram of a data processing system according to an embodiment of the present invention. As shown in fig. 1, the data processing system of this embodiment includes: the memory and the data processing chips are sequentially connected at intervals to form one-dimensional connection. Each data processing chip comprises at least one interconnection memory controller, and the interconnection memory controllers are connected with the memories. The at least one memory may include a first memory or further include a second memory, each of which may be simultaneously coupled to an interconnect memory controller in one or more data processing chips. The at least two data processing chips include a first data processing chip and a second data processing chip. At least one interconnection memory controller in the first data processing chip comprises a first interconnection memory controller, and is connected with a first memory through the first interconnection memory controller; at least one of the interconnect memory controllers in the second data processing chip includes a second interconnect memory controller through which the first memory is connected. In fig. 1, a number of data processing chips and memories are exemplarily shown, and in various embodiments of the present invention, the number of data processing chips and memories may be more or less than that shown in fig. 1, and those skilled in the art may implement corresponding embodiments based on descriptions of embodiments of the present invention. Wherein:

The first data processing chip is used for sending a request message to the first memory through the first interconnection memory controller when data is required to be stored in the target memory or data is required to be sent to the second data processing chip, the request message comprises data to be processed, a receiver identifier and a sender identifier, wherein the receiver identifier uniquely identifies a receiver in the data processing system, the receiver comprises the data processing chip and the memory, and the sender identifier uniquely identifies one data processing chip in the data processing system. In each embodiment of the present invention, if the request message is a data storage request message, the data to be processed therein is data to be stored; if the request message is a data exchange request message or a data transmission request message, the data to be processed is the data to be exchanged or the data to be transmitted.

A first memory for identifying whether a recipient identification in the request message is an identification of the first memory; if the identification of the receiver is the identification of the first memory, storing the data to be processed; otherwise, if the receiver identifier is not the identifier of the first memory, forwarding the request message forward to a second interconnection memory controller in a second data processing chip connected to the first memory at the same time.

In the embodiments of the present invention, forward forwarding refers to forwarding a message in a one-dimensional connection along a transmission direction of the message when the message is received, so that the message is transmitted in the same direction in the one-dimensional connection.

In embodiments of the present invention, the memory may be, for example: hybrid memory cube dynamic random access memory (HMC DRAM), static Random Access Memory (SRAM), field Programmable Gate Array (FPGA), application Specific Integrated Circuit (ASIC), or multi-port hard disk, etc., optionally multiple memory interfaces may be provided. Wherein, the HMC DRAM can be provided with four or more interconnected memory controllers which are respectively and correspondingly connected to four or more memories; two or more interconnected memory controllers can be arranged in the SRAM and respectively and correspondingly connected to the two or more memories; two or more interconnected storage controllers can be arranged in the FPGA and respectively and correspondingly connected to the two or more memories; two or more interconnected memory controllers may be provided in the ASIC, each correspondingly connected to two or more memories.

In embodiments of the present invention, the interconnect memory controller may be coupled to the memory via any wired or wireless communication, such as serializer/deserializer (SERDES), ethernet, or bus and interface standard (PCIE).

The second data processing chip is used for identifying whether the identification of the second data processing chip is the identification of the receiver in the request message; if the identification of the receiving party is the identification of the second data processing chip, reading the data to be processed for processing, such as calculation, storage and the like; otherwise, if the receiver identifier is not the identifier of the second data processing chip, forwarding the request message to a second memory connected to the third interconnection memory controller at the same time through the third interconnection memory controller in the second data processing chip. Wherein the second data processing chip further comprises a third interconnect memory controller.

Based on the data processing system provided by the embodiment of the invention, the interconnection memory controller is arranged in the data processing chip, the data processing chip is connected with the memory through the interconnection memory controller, the data in the memory is read and written through the interconnection memory controller, and the data exchange with other data processing chips is realized through the interconnection memory controller and the memory. The embodiment of the invention comprises the following steps: the memory controller and the interconnection controller are not required to be independently arranged, so that the cost of the data processing chip is reduced, the IO pin density is reduced, the complexity of a PCB (printed circuit board) is reduced, the implementation difficulty and the cost of a data processing system are reduced, and the reliability of the data processing system is improved; all the data processing chips can share the storage space of the memory, when one data processing chip reads the data stored by other data processing chips from one memory, the data can be directly read from the memory without reading the data from the memory through the other data processing chips storing the data and forwarding the data to the current data processing chip, thereby improving the utilization rate of the storage space and reducing the complexity and time of data processing.

Alternatively, in the data processing system according to the embodiments of the present invention, the first data processing chip in a one-dimensional connection may be connected to the last memory in the one-dimensional connection, so as to form a link connection. And/or each data processing chip stores the relation between the identification of the receiver and the interconnection storage controller, so that when a request message or a data reading request message needs to be sent to the receiver, the data processing chip selects the corresponding interconnection storage controller in the data processing chip to send the request message or the data reading request message.

FIG. 2 is a schematic diagram of a data processing chip according to an embodiment of the present invention. As shown in fig. 2, the data processing chip of this embodiment includes a data processing unit and at least one interconnection memory controller, where the at least one interconnection memory controller includes an interconnection memory controller and another interconnection memory controller, and the data processing unit is respectively connected to each interconnection memory controller in the at least one interconnection memory controller, and each interconnection memory controller is respectively connected to one memory correspondingly. Wherein:

the data processing unit is used for sending a request message to a memory connected with the interconnection memory controller through the interconnection memory controller when data is required to be stored in the target memory or data is required to be sent to another data processing chip, wherein the request message comprises data to be processed, a receiver identifier and a sender identifier, the receiver identifier uniquely identifies one receiver chip in a data processing system, the receiver chip comprises the data processing chip and the memory, and the sender identifier uniquely identifies one data processing chip in the data processing system; and in response to receiving the request message via the one interconnection storage controller, identifying whether the recipient identification in the request message is the identification of the data processing chip; if the identification of the receiving party in the request message is the identification of the data processing chip, reading the data to be processed in the request message for processing; otherwise, if the identification of the receiving party in the request message is not the identification of the data processing chip, forwarding the request message to another memory connected to the data processing chips at the same time through another interconnection memory controller. In the embodiment of the invention, the forward forwarding, namely the direction of forwarding the request message, leads the transmission direction of the request message to be along the same direction of one-dimensional connection.

And the interconnection storage controller is connected to one of the memories and is used for forwarding the request message sent by the data processing unit to the connected memory.

Based on the data processing chip provided by the embodiment of the invention, the interconnection memory controller is arranged, the data processing chip is connected with the memory through the interconnection memory controller, the data read-write in the memory is realized through the interconnection memory controller, and the data exchange with other data processing chips is realized through the interconnection memory controller and the memory. The data processing chip of the embodiment of the invention comprises: the memory controller and the interconnection controller are not required to be independently arranged, so that the cost of the data processing chip is reduced, the IO pin density is reduced, the complexity of a PCB (printed circuit board) is reduced, the implementation difficulty and the cost of a data processing system are reduced, and the reliability of the data processing system is improved; all the data processing chips can share the storage space of the memory, when one data processing chip reads the data stored by other data processing chips from one memory, the data can be directly read from the memory without reading the data from the memory through the other data processing chips storing the data and forwarding the data to the current data processing chip, thereby improving the utilization rate of the storage space and reducing the complexity and time of data processing.

In another embodiment of the data processing chip of the present invention, the data processing unit may be further configured to determine, before sending a request message to the above-mentioned one interconnection storage controller, that the data to be processed is shared data or private data, where the request message further includes a data type identifier for identifying that the data type is shared data or private data; and setting the working state of the interconnection memory controller to be a data writing state. The data type of the current data is shared data or private data, and can be determined through the configuration of the data processing chip in advance, for example, the pre-configured service type, links in a service processing process, and the like.

Or in yet another embodiment of the data processing chip of the present invention, the data processing unit is specifically configured to, when the data to be processed in the request message needs to be stored, determine, according to a preset configuration, a target memory for storing the data to be processed and a target storage area in the target memory, and obtain an identifier of the target memory and an identifier of the target storage area (for example, a chip identifier, a storage area number, etc.), and use the identifier of the target memory as the identifier of the receiver; correspondingly, the request message also comprises an identifier of the target storage area; and setting the working state of the interconnection memory controller to be a data writing state.

In an optional example of each data processing chip embodiment of the present invention, the data processing unit is specifically configured to set a working state of the one interconnection memory controller to a data exchange state when data needs to be sent to the other data processing chip except the data processing chip where at least two data processing chips are located, and send the exchanged data to the one memory through the one interconnection memory controller.

In the embodiment of the invention, the interconnection storage controller can comprise the following three working states: a data write state, a data read state, a data exchange state. The interconnection memory controller is used for respectively storing data into the memory, reading data from the memory and exchanging data with the other data processing chip when the interconnection memory controller is in the three states.

In addition, in still another embodiment of the data processing chip of the present invention, the data processing unit may be further configured to set an operating state of the one interconnection storage controller directly or indirectly connected to the receiver to a data reading state when data is required to be read from the receiver, and send a data reading request message to the one memory through the one interconnection storage controller, where the reading request message includes a sender identifier and a receiver identifier, and the sender identifier is an identifier of the one data processing chip. Correspondingly, in this embodiment, the interconnection storage controller may be further configured to receive data requested by the data read request message returned by the memory, and forward the stored data requested by the data read request message to the data processing unit.

Optionally, the data read request message may further include a data type identifier, where the data type identifier is used to identify that the data type of the data requested by the data read request message is shared data or private data.

Or optionally, the data processing unit is specifically configured to determine, when data needs to be read from the receiver, that a memory in which the data needs to be read is located and a memory area in the memory are respectively used as a target memory and a target memory area, and acquire an identifier of the target memory and an identifier of the target memory area, where the receiver identifier in the embodiment is specifically the identifier of the target memory, and the request message may further include the identifier of the target memory area.

In the data processing system according to the embodiments of the present invention, the data processing chip may be exemplarily implemented by any of the data processing chip embodiments described above.

FIG. 3 is a schematic diagram of an embodiment of a memory cell according to an embodiment of the present invention. As a specific example, and not by way of limitation, of embodiments of the data processing system of the present invention, as illustrated in fig. 3, the memory of an embodiment of the present invention comprises: the system comprises a switching center unit, a storage unit and more than two storage interfaces, wherein each storage interface is respectively connected with an interconnection storage controller in one data processing chip. Wherein:

The switching center unit is used for receiving the request message through a first storage interface connected with the first interconnection storage controller in more than two storage interfaces and identifying whether the identification of a receiver in the request message is the identification of the first storage; if the identification of the receiver in the request message is the identification of the first memory, storing the data to be processed in the request message in a storage unit; if the receiver identifier in the request message is not the identifier of the first memory, forwarding the request message to a second interconnection memory controller in a second data processing chip connected to the first memory through a second memory interface connected with the second interconnection memory controller in more than two memory interfaces; receiving a data reading request message through a first storage interface connected with a first interconnection storage controller in more than two storage interfaces, and identifying whether a receiver identifier in the data reading request message is an identifier of the first storage; if the receiver identifier in the data reading request message is the identifier of the first memory, acquiring the data requested by the data reading request message from the memory unit, and returning the data requested by the data reading request message to the first interconnection memory controller; otherwise, if the identification of the receiving party in the data reading request message is not the identification of the first memory, forwarding the request message to the second interconnection memory controller through the second memory interface.

And the storage unit is used for storing data.

In one example of embodiments of the memory of the present invention, the memory unit includes: the data processing system comprises a private storage area and a shared storage area, wherein the private storage area comprises a plurality of storage areas which are respectively allocated to each data processing chip in advance. In the above embodiment, the request message may further include a data type identifier of the data to be processed, where the data type identifier is used to identify that the data type of the data to be processed is shared data or private data. Correspondingly, the switching center unit is specifically configured to store the data to be processed in a first storage area pre-allocated to the first data processing chip, if the data type of the data to be processed is private data, according to the data type identifier in the request message; and if the data type of the data to be processed is shared data, storing the data to be processed in a shared storage area in the storage unit.

In addition, in another example of the embodiments of the memory of the present invention, a data type identifier may be further included in the data read request message, where the data type identifier is used to identify that the data requested by the data read request message is shared data or private data. Correspondingly, when the switching center unit acquires the data requested by the data reading request message from the storage unit according to the data reading request message, the switching center unit is specifically configured to read the storage data requested by the data reading request message from the storage area pre-allocated to the first data processing chip if the data type of the requested data is private data according to the data type identifier in the data reading request message; and if the data type of the request data is shared data, reading the storage data requested by the data reading request message from the shared storage area.

In addition, referring back to fig. 3, in another embodiment of the memory cell structure shown in fig. 3, the memory cell includes: the private storage area and the shared storage area are used for storing data. The private storage area comprises a plurality of storage areas which are respectively allocated to the data processing chips in advance and are respectively used for storing private data of the data processing chips, and the shared storage area is used for storing shared data of the data processing chips in the data processing system. Each storage area is uniquely identified by the identification of the storage area.

In this embodiment, the request message further includes an identification of the target storage area. In response to this, the control unit,

the switching center unit is used for receiving the request message through a first storage interface connected with the first interconnection storage controller in more than two storage interfaces and identifying whether the identification of a receiver in the request message is the identification of the first storage; if the identification of the receiver in the request message is the identification of the first memory, storing the data to be processed in the request message in a target memory area in a memory unit according to the identification of the target memory area; if the receiver identifier in the request message is not the identifier of the first memory, forwarding the request message to a second interconnection memory controller connected to the memory at the same time through a second memory interface connected to the second interconnection memory controller in the second data processing chip in more than two memory interfaces; receiving a data reading request message through a first storage interface connected with a first interconnection storage controller in more than two storage interfaces, and identifying whether a receiver identifier in the data reading request message is an identifier of the first storage; if the receiver identifier in the data reading request message is the identifier of the first memory, acquiring the data requested by the data reading request message from the memory unit, and returning the data requested by the data reading request message to the first interconnection memory controller; otherwise, if the identification of the receiving party in the data reading request message is not the identification of the first memory, forwarding the request message to a second interconnection memory controller through a second memory interface.

FIG. 4 is a flow chart of one embodiment of a data store-and-forward processing method in a data processing system according to the present invention. The data processing system comprises at least one memory and at least two data processing chips, wherein the memory and the data processing chips are sequentially connected at intervals to form one-dimensional connection; each data processing chip comprises at least one interconnection memory controller, and is connected with the memory through the interconnection memory controller; the at least one memory includes a first memory. The data processing system in each data storing and forwarding processing method embodiment of the present invention may be implemented by using the data processing system in each embodiment of the present invention. As shown in fig. 4, the data store-and-forward processing method of this embodiment includes:

102, in response to a first data processing chip of the at least two data processing chips needing to store data to a target memory or needing to send data to a second data processing chip of the at least two data processing chips, the first data processing chip sends a request message to a first memory connected with a first interconnection memory controller of the first data processing chip.

The request message includes data to be processed, a receiver identifier and a sender identifier, wherein the receiver identifier uniquely identifies a receiver in the data processing system, and the receiver includes a data processing chip and a memory, namely: the receiver can be a data processing chip or a memory; the sender identification uniquely identifies a data processing chip in the data processing system.

In the data store-and-forward processing method according to another embodiment of the present invention, after the first data processing chip sends the request message, the identifier of the receiving party of the data to be stored in the request message may also be recorded, that is: it is recorded to which memory the pending data is sent in order to read the pending data from the memory later.

In an alternative example of an embodiment of the present invention, this operation 102 may be implemented as follows: responding to the first data processing chip in the at least two data processing chips to store data into the target memory, setting the working state of the first interconnection memory controller into a data writing state by the first data processing chip through the data processing unit in the first data processing chip, and sending a request message to the first interconnection memory controller; the first interconnect memory controller sends a request message to the connected first memory.

104, the first memory identifies whether the recipient identification in the request message is an identification of the first memory.

If the identifier of the receiving party is the identifier of the first memory, it indicates that the data to be processed in the request message is the data to be stored that needs to be stored, and operation 106 is performed. Otherwise, if the recipient identification is not the identification of the first memory, operation 108 is performed.

The first memory stores the pending data in the request message 106.

In an alternative example of an embodiment of the present invention, this operation 106 may be implemented as follows: the first memory stores data to be processed in a storage unit in the first memory.

After that, the subsequent flow of the present embodiment is not performed.

The first memory forwards the request message 108 to a second interconnect memory controller in a second data processing chip that is also connected to the first memory.

110, the second data processing chip identifies whether the recipient identification in the request message is an identification of the second data processing chip.

If the recipient identification in the request message is the identification of the second data processing chip, operation 112 is performed. Otherwise, if the recipient identification in the request message is not the identification of the second data processing chip, operation 114 is performed.

112, the second data processing chip reads the data to be processed in the request message for processing, e.g. storing or calculating.

After that, the subsequent flow of the present embodiment is not performed.

114, forwarding the request message to a second memory simultaneously connected to the third interconnection memory controller by the second data processing chip through the third interconnection memory controller in the second data processing chip, and executing operation 104 by using the second memory as a new first memory until the identifier of the receiver is the identifier of the current receiver currently receiving the request message, and storing the data to be processed in the request message by the memory as the current receiver or reading the data to be processed in the request message by the data processing chip as the current receiver for processing.

It should be noted that, taking the second memory as the new first memory means that the second memory is the same as the new first memory in operation, but not the connected data processing chip or the interconnection memory controller therein, and receives the request message sent by the interconnection memory controller connected with the second memory in the previous data processing chip along the transmission direction of the one-dimensional connection, if the identifier of the receiver is not the identifier of the second memory, forwards the request message to the interconnection memory controller connected with the second memory in the next data processing chip along the transmission direction of the one-dimensional connection.

Based on the data storage forwarding processing method provided by the embodiment of the invention, an interconnection storage controller is arranged in the data processing chip, the interconnection storage controller is connected with the memory, the data in the memory is read and written through the interconnection storage controller, and the data exchange with other data processing chips is realized through the interconnection storage controller and the memory. The embodiment of the invention comprises the following steps: the memory controller and the interconnection controller are not required to be independently arranged, so that the cost of the data processing chip is reduced, the IO pin density is reduced, the complexity of a PCB (printed circuit board) is reduced, the implementation difficulty and the cost of a data processing system are reduced, and the reliability of the data processing system is improved; all the data processing chips can share the storage space of the memory, when one data processing chip reads the data stored by other data processing chips from one memory, the data can be directly read from the memory without reading the data from the memory through the other data processing chips storing the data and forwarding the data to the current data processing chip, thereby improving the utilization rate of the storage space and reducing the complexity and time of data processing.

In each embodiment of the present invention, when a memory, a data processing chip, etc. receive a message or data to be forwarded, if a plurality of messages or data to be forwarded are received at the same time, the messages or data may be forwarded according to a preset priority rule, where the priority rule may include any one or more of the following, for example: service type, sender, receiver, sender type, receiver type, etc. The priority rule of the service type is used for explaining the transmission priority relation of the messages or data of different service types; the priority rule of the sender is used for explaining which messages or data sent by the sender need to be processed preferentially; the priority rule of the receiver is used for explaining which message or data sent to the receiver needs to be processed preferentially; the sender type comprises a memory and a data processing chip, and a priority rule of the sender type is used for explaining which types of messages or data of a receiver need to be processed preferentially; the receiver type comprises a memory and a data processing chip, and the priority rule of the receiver type is used for the message or the data of which type needs to be processed preferentially by the receiver.

Fig. 5 is a flowchart of another embodiment of the data store-and-forward processing method of the present invention. As shown in fig. 5, the data store-and-forward processing method of this embodiment may further include:

202, in response to a first data processing chip of the at least two data processing chips needing to store data to a target memory, the first data processing chip sets the working state of a first interconnection memory controller to a data writing state through a data processing unit in the first data processing chip, and sends a request message to the first interconnection memory controller.

In the data store-and-forward processing method according to another embodiment of the present invention, after the first data processing chip sends the request message, if the request message is a storage request message for storing data, the data processing unit may further record the identifier of the receiving party to be stored with the data in the request message, that is: it is recorded to which memory the pending data is sent in order to read the pending data from the memory later.

The first interconnect memory controller sends 204 a request message to the connected first memory.

The first store identifies 206 whether the recipient identification in the request message is an identification of the first store.

If the recipient identifier is the identifier of the first memory, it indicates that the data to be processed in the request message is the data to be stored that needs to be stored, and operation 208 is performed. Otherwise, if the recipient identification is not the identification of the first memory, operation 210 is performed.

208, the first memory stores the data to be processed in a storage unit in the first memory.

After that, the subsequent flow of the present embodiment is not performed.

The first memory forwards the request message 210 to a second interconnect memory controller in a second data processing chip that is also connected to the first memory.

212, the second data processing chip identifies whether the recipient identification in the request message is an identification of the second data processing chip.

If the recipient identification in the request message is the identification of the second data processing chip, operation 214 is performed. Otherwise, if the recipient identification in the request message is not the identification of the second data processing chip, operation 216 is performed.

214, the second data processing chip reads the data to be processed in the request message for processing, such as storage or calculation.

After that, the subsequent flow of the present embodiment is not performed.

And 216, forwarding the request message to a second memory simultaneously connected to the third interconnection memory controller through the third interconnection memory controller in the second data processing chip by the second data processing chip, and executing operation 206 by taking the second memory as a new first memory until the identification of the receiver is the identification of the current receiver currently receiving the request message, and storing the data to be processed in the request message by the memory serving as the current receiver or reading the data to be processed in the request message by the data processing chip serving as the current receiver for processing.

In still another embodiment of the foregoing embodiments of the data store-and-forward processing method according to the present invention, the sending, at the first data processing chip, a request message to the first interconnect memory controller may further include: the data processing unit in the first data processing chip determines that the data type of the data to be processed is shared data or private data, and the request message also comprises a data type identifier, wherein the data type identifier is used for identifying that the data type of the data to be processed is shared data or private data. Accordingly, the first memory stores the data to be processed in a storage unit in the first memory, including: the first memory stores the data to be processed in the corresponding memory area in the memory unit according to the data type identification in the request message.

Specifically, the first memory stores the data to be processed in the corresponding storage area in the storage unit according to the data type identifier in the request message, and includes: according to the data type identifier in the request message, if the data type of the data to be processed is private data, the first memory stores the data to be processed in a first memory area which is pre-allocated to the first data processing chip in the memory unit; and if the data type of the data to be processed is shared data, the first memory stores the data to be processed in a shared memory area in the memory unit.

In still another embodiment of the foregoing embodiments of the data store-and-forward processing method according to the present invention shown in fig. 1-2, in operation 102 or 202, when a first data processing chip of the at least two data processing chips needs to store data into the target memory, the method may further include: the data processing unit in the first data processing chip determines a target memory for receiving the data to be processed and a target storage area in the target memory according to the pre-configuration, acquires the identification of the target memory and the identification of the target storage area, and takes the identification of the target memory as the identification of a receiver; wherein the request message is specified to further include an identification of the target storage area. Accordingly, in operation 106 or 208, the first memory stores the data to be processed in the request message in the target storage area in the first memory according to the identification of the target storage area in the request message.

In an optional example of each of the foregoing embodiments of the data store-and-forward processing method of the present invention, in response to a first data processing chip needing to send data to a second data processing chip of at least two data processing chips, sending, by the first data processing chip, a request message to a first memory through a first interconnect memory controller may include: responding to the need of the first data processing chip to send data to the second data processing chip, setting the working state of the first interconnection memory controller to be a data exchange state by the data processing unit in the first data processing chip, and sending a request message to the first memory through the first interconnection memory controller; the first memory forwards the request message to the first memory.

In addition, in another optional example of each of the foregoing data store-and-forward processing method embodiments of the present invention, the memory includes a plurality of storage interfaces, each of which is correspondingly connected to one of the interconnected storage controllers in the different data processing chips, and receives, through one of the storage interfaces, a request message sent by the interconnected storage controller connected thereto, and sends, through the other one of the storage interfaces, the received request message to the interconnected storage controller in the data processing chip connected thereto through the other one of the storage interfaces, thereby implementing forwarding of the request message.

In addition, in the embodiments of the data store-and-forward processing method according to the present invention, the data processing chip may further include an operation of reading data from the receiving side (for example, a memory or other data processing chip). When the receiver is a memory, the data processing chip can read private data stored by the receiver from the memory and can also read shared data stored by each data processing chip in the data processing system; when the receiver is other data processing chips, the data processing chip can acquire data from the other data processing chips.

FIG. 6 is a flowchart of one embodiment of reading data from a receiving side by a first data processing chip according to an embodiment of the present invention. In this embodiment, the first data processing chip is taken as an example to read data, and a person skilled in the art can know the implementation scheme of the data processing chip that needs to read data from the receiving side based on the description of the embodiment of the present invention. As shown in fig. 6, in this embodiment, the first data processing chip reads data from the receiving side, including:

302, in response to a first data processing chip needing to read data from a receiver, a data processing unit in the first data processing chip sets a working state of a first interconnection storage controller connected to the receiver to be a data reading state, and sends a data reading request message to a first memory through the first interconnection storage controller, wherein the reading request message comprises a sender identifier and a receiver identifier, and the sender identifier is an identifier of the first data processing chip; the recipient identification is used to identify the recipient, who may be a memory or a data processing chip.

304, the first memory identifies whether the recipient identification in the request message is an identification of the first memory.

If the recipient identification is an identification of the first memory, operation 306 is performed. Otherwise, if the recipient identification is not the identification of the first memory, operation 310 is performed.

306, the first memory obtains the data requested by the data read request message from the first memory and returns the data requested by the data read request message to the first interconnect memory controller.

308, the first interconnect memory controller forwards the data requested by the data read request message to the data processing unit in the first data processing chip.

After that, the subsequent flow of the present embodiment is not performed.

The first memory forwards 310 the data read request message to a second data processing chip that is also connected to the first memory.

312, the second data processing chip identifies whether the recipient identification in the data read request message is an identification of the second data processing chip.

If the recipient identification in the data read request message is the identification of the second data processing chip, operation 312 is performed. Otherwise, if the recipient identification in the data read request message is not the identification of the second data processing chip, operation 318 is performed.

314, the second data processing chip obtains the data requested by the data read request message and transfers the data to the first memory along the reverse path of the data read request message.

In the embodiments of the present invention, the reverse direction refers to a direction opposite to a transmission direction of a message when the message is received.

316, the first memory returns the data requested by the data read request message to the first interconnect memory controller.

318, the first interconnect memory controller forwards the data requested by the data read request message to the data processing unit in the first data processing chip.

After that, the subsequent flow of the present embodiment is not performed.

The second data processing chip forwards 320 the data read request message to a second memory simultaneously connected to the second data processing chip.

And taking the second memory as a new first memory, executing 302 until the current receiver identifier is the current receiver identifier, acquiring data requested by the data reading request message by the current receiver, transmitting the data requested by the data reading request message to the first memory along a reverse transmission path of the data reading request message, returning the data requested by the data reading request message to the first interconnection memory controller by the first memory, and forwarding the data requested by the data reading request message to a data processing unit in the first data processing chip by the first interconnection memory controller.

In an alternative example of the embodiment shown in fig. 6, if the receiving party is a memory, the data type identifier is further included in the data read request message, where the data type identifier is used to identify that the data requested by the data read request message is shared data or private data. Accordingly, in operation 304, the first memory obtains the data requested by the data read request message from the first memory, including: if the data type identified by the identifier in the data reading request message is private data, the first memory reads the storage data requested by the data reading request message from a first storage area pre-allocated to the first data processing chip in a storage unit in the first memory; if the data type identified by the identifier in the data reading request message is shared data, the first memory reads the storage data requested by the request from the shared storage area in the storage unit in the first memory.

In another alternative example of the embodiment shown in fig. 6, the first data processing chip needs to read data from the receiving side, which may be: the first data processing chip determines a memory in which data to be read are located and a storage area in the memory as a target memory and a target storage area respectively, and acquires an identifier of the target memory and an identifier of the target storage area, wherein a receiver identifier is the identifier of the target memory, and correspondingly, the data reading request message can also comprise the identifier of the target storage area. Accordingly, in operation 304, the first memory obtains the data requested by the data read request message from the first memory, including: the first memory reads the data requested by the data read request message from the target storage area in the first memory according to the identification of the target storage area in the data read request message.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, so that the same or similar parts between the embodiments are mutually referred to. For the method, apparatus and system embodiments, the relevant places refer to each other because they correspond to each other.

The methods, apparatus, systems of the present invention may be implemented in numerous ways. For example, the methods and apparatus, systems of the present invention may be implemented by software, hardware, firmware, or any combination of software, hardware, firmware. The above-described sequence of steps for the method is for illustration only, and the steps of the method of the present invention are not limited to the sequence specifically described above unless specifically stated otherwise. Furthermore, in some embodiments, the present invention may also be embodied as programs recorded in a recording medium, the programs including machine-readable instructions for implementing the methods according to the present invention. Thus, the present invention also covers a recording medium storing a program for executing the method according to the present invention.

The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. The data storage forwarding processing method in the data processing system is characterized in that the data processing system comprises at least one memory and at least two data processing chips, and the memory and the data processing chips are sequentially connected at intervals to form one-dimensional connection; each data processing chip comprises at least one interconnection memory controller, and is connected with a memory through the interconnection memory controller; the at least one memory includes a first memory;

2. The method as recited in claim 1, further comprising:

the first data processing chip records and stores the identification of a receiving party of the data to be stored.

3. The method according to claim 1 or 2, wherein in response to a first data processing chip of the at least two data processing chips needing to store data to a target memory, the first data processing chip sends a request message to a first memory connected to a first interconnect memory controller of the first data processing chip through the first interconnect memory controller, comprising: when a first data processing chip in the at least two data processing chips needs to store data to a target memory, the first data processing chip sets the working state of the first interconnection memory controller to be a data writing state through a data processing unit in the first data processing chip, and sends the request message to the first interconnection memory controller; the first interconnection storage controller sends the request message to the connected first storage;

4. The method of claim 3, further comprising, prior to sending a request message to the first interconnect storage controller:

5. The method of claim 4, wherein the first memory stores the data to be processed in the corresponding storage area in the storage unit according to the data type identification in the request message, comprising:

6. The method of claim 3, wherein when a first data processing chip of the at least two data processing chips needs to store data to the target memory, further comprising: the data processing unit in the first data processing chip determines a target memory of the data to be processed and a target storage area in the target memory according to the pre-configuration, acquires the identification of the target memory and the identification of the target storage area, and takes the identification of the target memory as the identification of the receiver; the request message also comprises an identifier of the target storage area;

7. The method as recited in claim 1, further comprising:

In response to the first data processing chip needing to read data from a receiver, a data processing unit in the first data processing chip sets a working state of a first interconnection storage controller connected to the receiver to be a data reading state, and sends a data reading request message to the first memory through the first interconnection storage controller, wherein the data reading request message comprises a sender identifier and a receiver identifier, and the sender identifier is an identifier of the first data processing chip;

8. The method of claim 7, wherein the receiving side is a memory, and the data read request message further includes a data type identifier, and the data type identifier is used for identifying that the data type is shared data or private data;

and if the data type identified by the identifier in the data reading request message is shared data, the first memory reads the storage data requested by the data reading request message from a shared storage area in a storage unit in the first memory.

9. The method of claim 7, wherein the first data processing chip is required to read data from a receiving side, comprising:

10. The method of claim 1, wherein, in response to a first data processing chip of the at least two data processing chips needing to send data to a second data processing chip of the at least two data processing chips, the first data processing chip sends a request message to a first memory connected to a first interconnect memory controller of the first data processing chip through the first interconnect memory controller, comprising:

11. The method of claim 1, wherein the at least one memory each comprises a plurality of memory interfaces, each memory interface being correspondingly coupled to an interconnect memory controller in a different data processing chip, a request message sent by a coupled interconnect memory controller being received by one of the plurality of memory interfaces, the request message being sent by another one of the plurality of memory interfaces to an interconnect memory controller in the data processing chip coupled to the other memory interface.

12. The data processing chip is characterized by comprising a data processing unit and at least one interconnection memory controller, wherein the data processing unit is respectively connected with each interconnection memory controller in the at least one interconnection memory controller, and each interconnection memory controller is respectively correspondingly connected to a memory; wherein:

the data processing unit is used for sending a request message to a memory connected with one interconnection memory controller through one interconnection memory controller when data is required to be stored in a target memory or data is required to be sent to another data processing chip, wherein the request message comprises data to be processed, a receiver identifier and a sender identifier, the receiver identifier uniquely identifies a receiver chip in a data processing system, the receiver chip comprises the data processing chip and the memory, and the sender identifier uniquely identifies the data processing chip in the data processing system; and in response to receiving a request message via the interconnect memory controller, identifying whether a recipient identification in the request message is an identification of the data processing chip; if the identification of the receiving party in the request message is the identification of the data processing chip, reading the data to be processed for processing; otherwise, if the identification of the receiving party in the request message is not the identification of the data processing chip, forwarding the request message to another memory connected to the data processing chip at the same time through another interconnection memory controller;

13. The chip of claim 12, wherein the data processing unit is further configured to determine, before sending the request message to the interconnected storage controller, that the data to be processed is shared data or private data, and the request message further includes a data type identifier, where the data type identifier is used to identify that the data type is shared data or private data; and setting the working state of the interconnected storage controllers to be a data writing state.

14. The chip according to claim 12, wherein the data processing unit is specifically configured to determine, when the data to be processed needs to be stored, a target memory storing the data to be processed and a target storage area in the target memory according to a preset configuration, and acquire an identifier of the target memory and an identifier of the target storage area, and use the identifier of the target memory as the identifier of the receiving party; the request message also comprises an identifier of the target storage area; and setting the working state of the interconnected storage controllers to be a data writing state.

15. The chip according to claim 12, wherein the data processing unit is specifically configured to set the working state of the one interconnection memory controller to a data exchange state when data is required to be sent to the other data processing chip, and send the exchange data to the one memory through the one interconnection memory controller.

16. The chip of claim 12, wherein the data processing unit is further configured to set an operation state of an interconnect storage controller connected to the receiver to a data read state when data is required to be read from the receiver, and send a data read request message to the memory through the interconnect storage controller, where the read request message includes a sender identifier and a receiver identifier, and the sender identifier is an identifier of the data processing chip;

17. The chip of claim 16, wherein the data read request message further includes a data type identifier, and the data type identifier is used to identify the data type as shared data or private data.

18. The chip according to claim 16, wherein the data processing unit is specifically configured to determine, when data needs to be read from the receiving side, a memory in which the data needs to be read is located and a memory area in the memory are respectively used as a target memory and a target memory area, and acquire an identifier of the target memory and an identifier of the target memory area, where the receiving side identifier is specifically an identifier of the target memory; the request message also includes an identification of the target storage area.

19. A data processing system, comprising: the memory and the data processing chips are sequentially connected at intervals to form one-dimensional connection; each data processing chip comprises at least one interconnection memory controller, and is connected with a memory through the interconnection memory controller; the at least one memory includes a first memory; the at least two data processing chips comprise a first data processing chip and a second data processing chip; at least one interconnection memory controller in the first data processing chip comprises a first interconnection memory controller, and is connected with the first memory through the first interconnection memory controller; at least one interconnection memory controller in the second data processing chip comprises a second interconnection memory controller, and the second interconnection memory controller is connected with the first memory;

20. The system of claim 19, wherein the data processing chip comprises the data processing chip of any of claims 12-18.

21. The system of claim 20, wherein the first memory comprises: the system comprises a switching center unit, a storage unit and more than two storage interfaces, wherein each storage interface is respectively connected with an interconnection storage controller in a data processing chip;

the switching center unit is configured to receive the request message through a first storage interface connected to the first interconnection storage controller among the two or more storage interfaces, and identify whether the receiver identifier is an identifier of the first storage; if the receiver identifier is the identifier of the first memory, storing the data to be processed in the request message in the storage unit; if the receiver identifier is not the identifier of the first memory, forwarding the request message to the second interconnection memory controller in the second data processing chip connected to the first memory through a second memory interface connected with the second interconnection memory controller in the more than two memory interfaces; receiving the request message through a first storage interface connected with the first interconnection storage controller in the more than two storage interfaces, and identifying whether a receiver identifier in the request message is an identifier of the first storage; if the identification of the receiver in the request message is the identification of the first memory, acquiring the data requested by the request message from the storage unit, and returning the data requested by the request message to the first interconnection storage controller; otherwise, if the identifier of the receiver in the request message is not the identifier of the first memory, forwarding the request message to the second interconnection memory controller through the second memory interface; the storage unit is used for storing data.

22. The system of claim 21, wherein the storage unit comprises: a private storage area and a shared storage area;

23. The system according to claim 22, wherein the switching center unit is configured to, when obtaining the data requested by the request message from the storage unit according to the request message, specifically, read the storage data requested by the request message from the storage area pre-allocated to the first data processing chip if the data type of the data is private data according to the data type identifier; and if the data type of the data is shared data, reading the storage data requested by the request message from the shared storage area.

24. The system of claim 20, wherein the memory comprises: the system comprises a switching center unit, a storage unit and more than two storage interfaces, wherein each storage interface is respectively connected with an interconnection storage controller in a data processing chip;

the request message also comprises an identifier of the target storage area;

the switching center unit is configured to receive the request message through a first storage interface connected to the first interconnection storage controller among the two or more storage interfaces, and identify whether the receiver identifier is an identifier of the first storage; if the receiver identifier is the identifier of the first memory, storing the storage data in the target storage area in the storage unit according to the identifier of the target storage area; if the receiver identifier is not the identifier of the first memory, forwarding the request message to a second interconnection memory controller connected to the memory at the same time through a second memory interface connected to the second interconnection memory controller in the second data processing chip in the more than two memory interfaces; receiving the request message through a first storage interface connected with the first interconnection storage controller in the more than two storage interfaces, and identifying whether the receiver identifier is an identifier of the first storage; if the receiver identifier is the identifier of the first memory, acquiring data requested by the request message from the storage unit, and returning the data requested by the request message to the first interconnection storage controller; otherwise, if the receiver identifier is not the identifier of the first memory, forwarding the request message to the second interconnection memory controller through the second memory interface.

25. The system of claim 19, wherein the memory comprises: hybrid memory cube dynamic random access memory HMC DRAM, static random access memory SRAM, field programmable gate array FPGA, application specific integrated circuit ASIC, or multi-port hard disk.

26. The system of claim 19, wherein the interconnect memory controller is coupled to the memory via serializer/deserializer SERDES, ethernet, or bus and interface standard PCIE.