CN107633866A - A kind of electrically programmable fuse structures of semiconductor devices - Google Patents
A kind of electrically programmable fuse structures of semiconductor devices Download PDFInfo
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- CN107633866A CN107633866A CN201710986289.2A CN201710986289A CN107633866A CN 107633866 A CN107633866 A CN 107633866A CN 201710986289 A CN201710986289 A CN 201710986289A CN 107633866 A CN107633866 A CN 107633866A
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- electrically programmable
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- control module
- programmable fuse
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Abstract
The present invention proposes a kind of electrically programmable fuse structures of semiconductor devices, including：Control module and Pre-decoder module；Word line driver module, it is arranged at the control module and Pre-decoder module both sides up and down；Sax modules, it is arranged at left and right sides of the control module and Pre-decoder module；Described two word line driver modules and two Sax modules form decussate texture；Four memory cell arrays, setting is respectively symmetrically distributed according to the decussate texture.The electrically programmable fuse structures of semiconductor devices proposed by the present invention, it is clear to provide a kind of layout, signal is smooth, the more superior E fuse domains of performance, the domain is by symmetrical up and down by the memory cell array of sheet, and bus is distributed in surrounding cyclization by power supply, and logic selection circuit is then distributed in central, the signal behavior of decoder and the symmetry of array are obtained for relatively good improvement, so as to improve E fuse performance.
Description
Technical field
The present invention relates to CMOS IC Layouts field, and more particularly to a kind of electrical programming of semiconductor devices melts
Silk structure.
Background technology
In integrated circuit fields, fuse (Fuse) refers to some connecting lines that can be fused formed in integrated circuits.
Initially, fuse is for connecting the redundant circuit in integrated circuit, once detection finds that integrated circuit has defect, just using molten
Silk is repaired or substitutes defective circuit.Fuse is generally laser fuse (Laser Fuse) and electrically programmable fuse
Two kinds of (Electrically Programmable Fuse, hereinafter referred to as E-fuse).With the development of semiconductor technology, E-
Fuse gradually instead of laser fuse.
At present, used in the semiconductor device is mostly electrically programmable fuse structures (E-fuse), and E-fuse is once
The circuit and system design flexibility that property electrically programmable fuse is provided due to it are commonly used.Even sealed by IC chip
E-fuse can also be programmed after dress and installation in systems.E-fuse can also provide freely changing to circuit design,
The latter solves the various problems being likely to occur in life of product.It is smaller relative to ablative-type protective coating fuse E-fuse, thus there is circuit
Density advantages.Although E-fuse has above-mentioned various advantages, there is also there is drawback, such as present E-fuse usually requires to surpass
The voltage of standard mains voltage is crossed to program, but as technology development effort voltage reduces rapidly, so obtaining programming E-fuse
Too high voltage can be in accentuation techniques electrician be restricted, and E-fuse resistance can also change at present, to E-
Fuse application brings many problems.
Common E-fuse domains at present, all memory cell arrays are all in the upper of logic selection and decoder module
Side, as shown in figure 1, including memory cell array 10 (Bit cell array), control module 20 (Ctrl), Pre-decoder module
30 (Predec), Sax modules 40, word line driver module 50 (Wldr).Laying out pattern is inadequate symmetrically and evenly in Fig. 1, decoder
Signal behavior and signal trend it is not clear enough, in addition power supply also can not cyclization give in-line power, illustrate this domain performance also
There is improved space.
The content of the invention
The present invention proposes a kind of electrically programmable fuse structures of semiconductor devices, there is provided one kind layout is clear, and signal is smooth,
The more superior E-fuse domains of performance, the domain by by sheet memory cell array it is symmetrical up and down, and
Bus is distributed in surrounding cyclization by power supply, and logic selection circuit is then distributed in central, the signal behavior and array of decoder
Symmetry be obtained for relatively good improvement, so as to improve E-fuse performance.
In order to achieve the above object, the present invention proposes a kind of electrically programmable fuse structures of semiconductor devices, including：
Control module and Pre-decoder module；
Word line driver module, it is arranged at the control module and Pre-decoder module both sides up and down；
Sax modules, it is arranged at left and right sides of the control module and Pre-decoder module；
Described two word line driver modules and two Sax modules form decussate texture；
Four memory cell arrays, setting is respectively symmetrically distributed according to the decussate texture.
Further, bus is distributed in surrounding cyclization to the electrically programmable fuse structures with also including power supply.
Further, the control module, which receives, enters the Pre-decoder module after initial signal inputs, generation yp,
Tetra- groups of buses of ys, xp1, xp0 are supplied respectively to Sax modules and word line driver module.
Further, the control module enters word line driver module, the input letter after receiving initial signal input
Number and two groups of buses of xp1, xp0 produce two groups of buses of Wl_L and Wl_R together, for reading electrically programmable fuse memory cell battle array
Row then produce one group of bit line bus.
Further, the control module enters Sax modules after receiving initial signal input, into the signal of Sax modules
With two groups of buses of yp, ys and the bit line bus, finally decoding generates Fsource signal wires together.
The electrically programmable fuse structures of semiconductor devices proposed by the present invention, circuit enter pre-decode by Ctrl control modules
Device module and Sax modules/word line driver module, get up to determine that electrically programmable fuse stores by various digital processings and decoding
The reading point of cell array, while make array center's symmetry arrangement using rational Butut, so as to reach optimal performance.This
Invention provides that a kind of layout is clear, and signal is smooth, the more superior E-fuse domains of performance, and the domain is by by the storage of sheet
Cell array is symmetrical up and down, and bus is distributed in surrounding cyclization by power supply, and logic selection circuit is then distributed in
Central, the signal behavior of decoder and the symmetry of array are obtained for relatively good improvement, so as to improve E-fuse's
Performance.
Brief description of the drawings
Fig. 1 show E-fuse domain structures schematic diagram in the prior art.
Fig. 2 show the E-fuse domain structure schematic diagrames of present pre-ferred embodiments.
Embodiment
The embodiment of the present invention is provided below in conjunction with accompanying drawing, but the invention is not restricted to following embodiment.Root
According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simple
The form of change and non-accurately ratio is used, be only used for conveniently, lucidly aiding in illustrating the purpose of the embodiment of the present invention.
Fig. 2 is refer to, Fig. 2 show the E-fuse domain structure schematic diagrames of present pre-ferred embodiments.The present invention proposes
A kind of electrically programmable fuse structures of semiconductor devices, including：Control module 100 (Ctrl) and Pre-decoder module 200
(Predec)；Word line driver module 300 (Wldr), the control module 100 and Pre-decoder module are arranged at two about 200
Side；Sax modules 400, it is arranged at the left and right sides of control module 100 and Pre-decoder module 200；Described two wordline drivings
Device module 300 and two Sax modules 400 form decussate texture；Four memory cell arrays 500 (Bit cell array),
Setting is respectively symmetrically distributed according to the decussate texture.
According to present pre-ferred embodiments, bus is distributed in surrounding cyclization to the electrically programmable fuse structures with also including power supply.
The control module 100, which receives, enters the Pre-decoder module 200 after initial signal inputs, generation yp, ys,
Tetra- groups of buses of xp1, xp0 are supplied respectively to Sax modules 400 and word line driver module 300.
The control module 100, which receives, enters word line driver module 300 after initial signal input, the input signal with
Two groups of buses of xp1, xp0 produce two groups of buses of Wl_L and Wl_R together, for reading electrically programmable fuse memory cell array 500
Then one group of bit line bus is produced.
The control module 100 enters Sax modules 400 after receiving initial signal input, into the signal of Sax modules 400
With two groups of buses of yp, ys and the bit line bus, finally decoding generates Fsource signal wires together.
In summary, the electrically programmable fuse structures of semiconductor devices proposed by the present invention, circuit pass through Ctrl control modules
Into Pre-decoder module and Sax modules/word line driver module, get up to determine that electricity is compiled by various digital processings and decoding
The reading point of journey fuse storage unit array, while make array center's symmetry arrangement using rational Butut, most managed so as to reach
The performance thought.The present invention provides a kind of layout clearly, and signal is smooth, and the more superior E-fuse domains of performance, the domain passes through
The memory cell array of sheet is symmetrical up and down, and bus is distributed in surrounding cyclization, logic selection by power supply
Among circuit is then distributed in, the signal behavior of decoder and the symmetry of array are obtained for relatively good improvement, so as to carry
High E-fuse performance.
Although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention.Skill belonging to the present invention
Has usually intellectual in art field, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Cause
This, the scope of protection of the present invention is defined by those of the claims.
Claims (5)
- A kind of 1. electrically programmable fuse structures of semiconductor devices, it is characterised in that including：Control module and Pre-decoder module；Word line driver module, it is arranged at the control module and Pre-decoder module both sides up and down；Sax modules, it is arranged at left and right sides of the control module and Pre-decoder module；Described two word line driver modules and two Sax modules form decussate texture；Four memory cell arrays, setting is respectively symmetrically distributed according to the decussate texture.
- 2. the electrically programmable fuse structures of semiconductor devices according to claim 1, it is characterised in that the electrically programmable fuse knot Bus is distributed in surrounding cyclization to structure with also including power supply.
- 3. the electrically programmable fuse structures of semiconductor devices according to claim 1, it is characterised in that the control module connects Enter the Pre-decoder module after receiving initial signal input, generation tetra- groups of buses of yp, ys, xp1, xp0 are supplied respectively to Sax modules With word line driver module.
- 4. the electrically programmable fuse structures of semiconductor devices according to claim 3, it is characterised in that the control module connects Enter word line driver module after receiving initial signal input, two groups of buses of the input signal and xp1, xp0 produce Wl_L together And two groups of buses of Wl_R, then produce one group of bit line bus for reading electrically programmable fuse memory cell array.
- 5. the electrically programmable fuse structures of semiconductor devices according to claim 4, it is characterised in that the control module connects Enter Sax modules after receiving initial signal input, into two groups of buses of signal and yp, ys of Sax modules and the bit line bus, Finally decoding generates Fsource signal wires together.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710986289.2A CN107633866A (en) | 2017-10-20 | 2017-10-20 | A kind of electrically programmable fuse structures of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710986289.2A CN107633866A (en) | 2017-10-20 | 2017-10-20 | A kind of electrically programmable fuse structures of semiconductor devices |
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| CN107633866A true CN107633866A (en) | 2018-01-26 |
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| CN201710986289.2A Pending CN107633866A (en) | 2017-10-20 | 2017-10-20 | A kind of electrically programmable fuse structures of semiconductor devices |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4982372A (en) * | 1988-06-16 | 1991-01-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having divided word or bit line drivers and operating method therefor |
| JPH04163966A (en) * | 1990-10-29 | 1992-06-09 | Hitachi Ltd | Vertical eeprom and its writing method |
| CN1186344A (en) * | 1996-12-26 | 1998-07-01 | 三菱电机株式会社 | Semiconductor device |
| CN101236788A (en) * | 2007-01-08 | 2008-08-06 | 阿尔特拉公司 | Variable sized soft memory macros in structured cell arrays, and related methods |
| US20150243368A1 (en) * | 2014-02-26 | 2015-08-27 | Scott I. Remington | High-Speed Address Fault Detection Using Split Address ROM |
| US20160027529A1 (en) * | 2014-07-23 | 2016-01-28 | Freescale Semiconductor, Inc. | Address Fault Detection Circuit |
-
2017
- 2017-10-20 CN CN201710986289.2A patent/CN107633866A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4982372A (en) * | 1988-06-16 | 1991-01-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having divided word or bit line drivers and operating method therefor |
| JPH04163966A (en) * | 1990-10-29 | 1992-06-09 | Hitachi Ltd | Vertical eeprom and its writing method |
| CN1186344A (en) * | 1996-12-26 | 1998-07-01 | 三菱电机株式会社 | Semiconductor device |
| CN101236788A (en) * | 2007-01-08 | 2008-08-06 | 阿尔特拉公司 | Variable sized soft memory macros in structured cell arrays, and related methods |
| US20150243368A1 (en) * | 2014-02-26 | 2015-08-27 | Scott I. Remington | High-Speed Address Fault Detection Using Split Address ROM |
| US20160027529A1 (en) * | 2014-07-23 | 2016-01-28 | Freescale Semiconductor, Inc. | Address Fault Detection Circuit |
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Application publication date: 20180126 |
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| RJ01 | Rejection of invention patent application after publication |