CN106601300B - Electric fuse storage unit, electric fuse storage array and using method thereof - Google Patents
Electric fuse storage unit, electric fuse storage array and using method thereof Download PDFInfo
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- CN106601300B CN106601300B CN201510660942.7A CN201510660942A CN106601300B CN 106601300 B CN106601300 B CN 106601300B CN 201510660942 A CN201510660942 A CN 201510660942A CN 106601300 B CN106601300 B CN 106601300B
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Abstract
The invention provides an electric fuse storage unit, an electric fuse storage array and a using method thereof, and relates to the technical field of semiconductors. The method comprises the following steps: an electrical fuse having a first end and a second end; the grid electrode of the first transistor is connected with the first word line, the drain electrode of the first transistor is connected with the second end of the electric fuse, and the source electrode and the drain electrode of the first transistor are respectively connected with the adjacent electric fuse storage units; and the drain electrode of the second transistor is connected with the second end of the electric fuse, and the grid electrode of the second transistor is connected with the second word line. The invention realizes the limitation of the reading current by connecting a plurality of NMOS transistors with smaller sizes in series, so that the times of reading operation are not limited. And the writing operation is realized by connecting a plurality of pull-down NMOS transistors in parallel, so that the sizes of the first transistor and the second transistor in each efuse memory cell are both reduced, and the sizes of the memory cell and the memory array are both reduced obviously.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an electric fuse storage unit, an electric fuse storage array and a using method of the electric fuse storage array.
Background
In the field of semiconductor technology, electrically programmable fuse (eFuse) technology has found widespread application as one-time programmable (OTP) memory in many circuits due to its advantages of compatibility with CMOS logic devices and ease of use.
The eFuse technology is based on the electromigration theory, and stores information through whether the electric fuse is fused by current or not, the resistance of the polysilicon electric fuse is very small before fusing, the resistance can be regarded as infinite after continuous high current fusing, and the broken state of the electric fuse is permanently kept. eFuse technology has been widely used in redundancy circuits to improve the problem of chip failure or wafer ID, device base code, etc. in place of small capacity one time programmable memories.
FIG. 1A shows a schematic diagram of a prior art eFuse memory cell, which includes an electrical fuse and one NMOS transistor, and FIG. 1B shows a schematic diagram of a prior art eFuse memory array, which includes rows and columns of eFuse memory cells, with the gate of the NMOS in each eFuse memory cell connected to a word line WL, which is a signal line that controls the read operation, the current through the electrical fuse being limited by the read current and duration, thus, limiting the number of read operations.
As the width of polysilicon efuse is getting narrower, the limitation on the read operation becomes more severe, for example, in the 28nm node technology. The above problems exist, which make eFuse technology only applicable to applications with limited number of read operations, for example, when the system is turned on, the corresponding SRAM is used to store the macroscopic data of the eFuse; as another example, an already stored ID is rarely read unless the chip ID needs to be checked.
Therefore, it is necessary to provide a new capacitor wire memory cell and an electrical fuse memory array to solve the above technical problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the deficiencies of the prior art, an embodiment of the invention provides an electrical fuse memory cell, including:
an electrical fuse having a first end and a second end opposite the first end;
a first transistor, a gate of which is connected to a first word line, a drain of which is connected to the second end of the electrical fuse, and a source and a drain of which are respectively connected to their adjacent electrical fuse memory cells;
a second transistor, a drain of the second transistor being connected to the second end of the electrical fuse, a gate of the second transistor being connected to a second word line.
Further, the first transistor and the second transistor are both NMOS transistors.
Further, the first transistor is a PMOS transistor.
Further, the source of the second transistor is grounded.
Further, the first end of the electrical fuse is connected to a bit line.
Further, the source of the first transistor of the current column of the electric fuse memory unit is connected with the drain of the first transistor of the previous column of the adjacent electric fuse memory unit, and the drain of the first transistor of the current column of the electric fuse memory unit is connected with the source of the first transistor of the next column of the adjacent electric fuse memory unit.
An embodiment of the present invention provides an electrical fuse memory array, including:
the memory comprises a plurality of first word lines, a plurality of independent second word lines and a plurality of bit lines which are arranged in a crossed mode with the first word lines and the second word lines;
a plurality of e-fuse memory cells arranged in a plurality of rows and columns, each of the e-fuse memory cells comprising: an electrical fuse having a first end and a second end opposite the first end; a first transistor, a gate of the first transistor is connected to the first word line, a drain of the first transistor is connected to the second end of the electrical fuse, a source of the first transistor of a current column of electrical fuse memory cells is connected to a drain of a first transistor of a previous column of adjacent electrical fuse memory cells, and a drain of the first transistor of a current column of electrical fuse memory cells is connected to a source of a first transistor of a next column of adjacent electrical fuse memory cells, wherein the adjacent electrical fuse memory cells share the same first word line; and a drain of the second transistor is connected with the second end of the electric fuse, a source of the second transistor is grounded, and a gate of the second transistor is connected with the second word line, wherein the gate of each second transistor is respectively connected with different second word lines.
Furthermore, the device also comprises a plurality of PMOS transistors, and the drain electrode of each PMOS transistor is respectively connected with the bit line of the column or the row where the PMOS transistor is positioned.
Further, the first transistor and the second transistor are both NMOS transistors.
Further, the first end of the electrical fuse is connected to the bit line of the column or row in which the electrical fuse is located.
Further, the first transistor is a PMOS transistor.
Further, the number of the electric fuse memory cells is greater than or equal to 2.
An aspect of the present invention further provides a method for using the foregoing electrical fuse memory array, including:
connecting one of the plurality of first word lines with a high level to enable each first transistor in the plurality of electric fuse storage units connected with the first word line to be conducted, connecting a second word line connected with each second transistor in the plurality of electric fuse storage units with a high level to enable each second transistor to be conducted, enabling the second transistors in the plurality of electric fuse storage units to form a parallel circuit, and simultaneously sequentially opening PMOS transistors corresponding to the plurality of electric fuse storage units, so that the writing operation of the corresponding electric fuse storage units can be realized.
Another aspect of the present invention further provides a method for using the foregoing electrical fuse memory array, including:
when storage data in one electric fuse storage unit is scheduled to be read, a first word line connected with the electric fuse storage unit is connected with a high level, meanwhile, each first transistor in other electric fuse storage units sharing the same first word line with the electric fuse storage unit scheduled to be read is conducted, a second word line is connected with a high level, a second transistor connected with the second word line is conducted, wherein the second word line is connected with one of the other electric fuse storage units, and then each first transistor in the other electric fuse storage units and the conducted second transistor are connected in series to serve as a reading path and used for achieving reading operation.
In summary, by adding an NMOS transistor to be connected to an efuse memory cell adjacent to the NMOS transistor, and further implementing that the NMOS transistor of a plurality of adjacent memory cells is connected in series is used as a read path, compared with the prior art that only one pull-down NMOS transistor with a larger size is used as a read path, the embodiments of the present invention can implement limitation on read current by connecting a plurality of NMOS transistors with smaller sizes in series, so that the number of read operations is not limited, and implement write operations by connecting a plurality of pull-down NMOS transistors in parallel, so that the sizes of the first transistor and the second transistor in each efuse memory cell are both reduced, and the size of the memory cell and the size of the memory array are both significantly reduced.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1A illustrates a schematic diagram of a prior art eFuse memory cell;
FIG. 1B illustrates a schematic diagram of a prior art eFuse memory array;
FIG. 2 is a schematic diagram of an eFuse memory cell of one embodiment of the present invention;
FIG. 3 illustrates a schematic structural diagram of an eFuse storage array in one embodiment of the present invention;
FIG. 4 illustrates a schematic diagram of a neighboring eFuse memory cell of one embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, a detailed structure will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
An eFuse memory cell as set forth in one embodiment of the present invention is described below with reference to FIG. 2.
Illustratively, the eFuse memory cell of the present invention, as shown in FIG. 2, includes the following elements:
an electrical fuse 20 is included, the electrical fuse 20 having a first end 1 and a second end 2 opposite the first end 1. The first end of the electrical fuse is connected to a bit line (not shown).
Illustratively, the material of the electrical fuse 20 may include polysilicon. Wherein the first terminal 1 is an anode of the electrical fuse 20 and the second terminal is a cathode of the electrical fuse 20.
The memory further comprises a first transistor 21, wherein a gate of the first transistor 21 is connected to a first word line WL1, a drain N _ A of the first transistor 21 is connected to the second end 2 of the electrical fuse 20, and a source N _ B and a drain N _ A of the first transistor 21 are respectively connected to adjacent electrical fuse memory cells. Illustratively, the source N _ B of the first transistor 21 of the current column of the e-fuse memory unit is connected to the drain N _ a of the first transistor 21 of the previous column of the adjacent e-fuse memory unit, and the drain N _ a of the first transistor 21 of the current column of the e-fuse memory unit is connected to the source N _ B of the first transistor of the next column of the adjacent e-fuse memory unit.
The electric fuse further comprises a second transistor 22, wherein the drain of the second transistor 22 is connected with the second end 2 of the electric fuse 20, and the gate of the second transistor 22 is connected with a second word line WL 2. Further, the source of the second transistor 22 is grounded.
In one example, the first transistor 21 is an NMOS transistor and the second transistor 22 is an NMOS transistor. Wherein the size of the first transistor 21 is smaller than the size of the second transistor 22.
In the above-mentioned efuse memory cell, the size of the first transistor 21 can be smaller than that of a normal NMOS transistor, and specifically, the size of the first transistor can be selected appropriately according to the number of first transistors actually connected in series. Similarly, the size of the second transistor 22 can be reduced to be much smaller than the size of the NMOS transistor in the prior art, which can be calculated by the number of second transistors connected in parallel in the actual memory array.
Compared with the prior art that only one pull-down NMOS transistor with a larger size is used as a read path, the embodiment of the invention can realize the limitation of read current by serially connecting a plurality of NMOS transistors with smaller sizes, and realize the write operation by connecting a plurality of pull-down NMOS transistors in parallel, and simultaneously the sizes of the first transistor and the second transistor in each efuse memory cell are both reduced, so that the size of the memory cell is remarkably reduced.
The challenge of overcoming the number of read operations is mainly expressed in the following aspects:
(1) the magnitude of the maximum read current (read current) is limited, for example, the read current is 1/10 of the maximum burning current (burning current), when the maximum burning current is 50mA, the maximum read current is 5 mA; the maximum read time is also correspondingly limited, for example, if the maximum read time (read flow time) is 1s, the number of read accesses is about 10000000, and the calculation formula is 1/100 ns-10000000.
(2) The maximum current to be passed before firing (when not fired) is limited, for example, 1/100 which is the maximum firing current, the current to be passed is 5/100 mA which is 0.5 mA. And there is no time limit.
Illustratively, the first transistor can also be a PMOS transistor, and can also realize the same function.
In summary, the efuse memory cell in the embodiment of the invention is connected to an NMOS transistor by adding the NMOS transistor, so that the number of read operations is not limited, the write operation is not affected, and the size of the memory cell is significantly reduced.
Example two
In another embodiment of the present invention, an electrical fuse memory array is further provided, which includes the electrical fuse memory cells in the foregoing embodiments.
Specifically, the electrical fuse memory array in the embodiment of the present invention is described in detail with reference to fig. 3 and 4.
As shown in fig. 3, the electrical fuse memory array of the present embodiment includes a plurality of electrical fuse memory cells 30, and the plurality of electrical fuse memory cells 30 are arranged in a plurality of rows and a plurality of columns, for example, m rows and n columns, where m and n are integers. The memory array structure including only 4 efuse memory cells in 2 rows and 2 columns is shown in fig. 3, and the same applies to rows and columns of efuse memory arrays in other cases.
The electric fuse memory array in the embodiment of the invention further comprises a plurality of first word lines WL1, a plurality of independent second word lines WL2 and BL arranged to intersect the first word lines WL1 and the second word lines WL 2;
illustratively, the number of bit lines BL corresponds to the number of columns of efuse memory cells 30, e.g., there are n columns of efuse memory cells, and then there are n columns of bit lines BL. The number of the first word lines WL1 corresponds to the number of rows of the efuse memory cells 30, for example, m rows of the efuse memory cells may be provided, and m rows of the first word lines WL1 may be provided. Each row of the first word line WL1 connects the gates of the first transistors in the plurality of electrical fuse memory cells 30 of the row in which it is located.
In another example, the bit lines BL are arranged in rows, and the number of bit lines corresponds to the number of rows of the electric fuse memory cells, while the first word lines WL1 are arranged in columns, and the number of columns of the first word lines WL1 corresponds to the number of columns of the electric fuse memory cells 30.
And a plurality of independent second word lines WL2, wherein each second word line WL2 is used for controlling the on and off of a second transistor in the electric fuse memory cell connected with the second word line WL2, and the second transistor is controlled independently because the second word lines WL2 are independent. Illustratively, the number of second word lines WL2 is equal to the number of second transistors.
The electrical fuse memory array in the embodiment of the present invention further includes a plurality of PMOS transistors 31, a drain of each of the PMOS transistors 31 is connected to the bit line BL of the column or the row where the PMOS transistor 31 is located, and the number of the PMOS transistors may be equal to the number of columns of the electrical fuse memory units, for example, if the plurality of electrical fuse memory units 30 are arranged in n columns, there are n PMOS transistors 31, and each PMOS transistor 31 corresponds to one column of the electrical fuse memory units. Further, the source of each of the PMOS transistors 31 is connected to a power supply line Vdd adapted to supply a power supply voltage, the gate of each of the PMOS transistors is connected to a column decoder adapted to supply a column decoding signal for controlling the PMOS transistors to be turned on or off to each column of the PMOS transistors.
As shown in fig. 4, each of the electrical fuse memory cells 30 illustratively includes: an electrical fuse 20, the electrical fuse 20 having a first end and a second end opposite the first end; a first transistor 21, a gate of the first transistor 21 is connected to the first word line WL1 of the row, a drain of the first transistor 21 is connected to the second end of the electrical fuse 20, a source N _ B of the first transistor 21 of the electrical fuse memory cell of a current column is connected to a drain N _ a of the first transistor 21 of the electrical fuse memory cell of a previous column, and a drain N _ a of the first transistor 21 of the electrical fuse memory cell of the current column is connected to a source N _ B of the first transistor of the electrical fuse memory cell of a next column.
Wherein the adjacent electric fuse memory cells 30 share the same first word line WL 1; a second transistor 22, a drain of the second transistor 22 is connected to the second terminal of the electrical fuse 20, a source of the second transistor 22 is grounded, and a gate of the second transistor 22 is connected to the second word line WL2, wherein a gate of each of the second transistors 22 is connected to a different second word line WL 2.
Illustratively, the material of the electrical fuse may include polysilicon. Wherein the first end is an anode of an electrical fuse and the second end is a cathode of the electrical fuse.
Further, the first end of the electrical fuse is connected to the bit line BL of the column or row in which the electrical fuse is located.
In the electric fuse memory array of the embodiment of the invention, NMOS transistors having a smaller size may be used as the first transistor and the second transistor, wherein the size of the second transistor may be slightly larger than the first transistor.
Further, in the electric fuse memory array, the number of the electric fuse memory cells is greater than or equal to 2.
In another aspect of the present invention, a method for using the electrical fuse memory array includes: connecting one of the plurality of first word lines with a high level to enable each first transistor in the plurality of electric fuse storage units connected with the first word line to be conducted, connecting a second word line connected with each second transistor in the plurality of electric fuse storage units with a high level to enable each second transistor to be conducted, enabling the second transistors in the plurality of electric fuse storage units to form a parallel circuit, and simultaneously sequentially opening PMOS transistors corresponding to the plurality of electric fuse storage units, so that the writing operation of the corresponding electric fuse storage units can be realized.
Specifically, referring to fig. 4, taking two connected memory cells as an example for specific description, the word line WL1 and the word line WL11 are connected to high level to turn on each first transistor 21 in the two electrical fuse memory cells, wherein the word line WL1 and the word line WL11 are located in the same row and in the same word line, and the second word lines WL2 and WL21 connected to the gate of each second transistor 22 in each electrical fuse memory cell are connected to high level to turn on each second transistor 22, so that the second transistors 22 in the plurality of electrical fuse memory cells form a parallel circuit, and the PMOS transistors corresponding to the electrical fuse memory cells are sequentially turned on at the same time, and thus the write operation for the corresponding electrical fuse memory cells can be realized.
In a write operation device, the electrical fuse must encounter a burn current, and the non-burn fuse resistor must not be able to draw a current greater than the maximum measured current flow. By adopting the electric fuse storage array provided by the embodiment of the invention, the second transistor can form a parallel circuit, so that the total current of a writing circuit is increased, the electric fuse can be fused, and the writing operation is realized. Meanwhile, the smaller size of the second transistor and the first transistor will significantly reduce the area of the memory cell.
In another aspect of the present invention, a method for using the electrical fuse memory array described above is further provided, including: when storage data in one electric fuse storage unit is scheduled to be read, a first word line connected with the electric fuse storage unit is connected with a high level, meanwhile, each first transistor in other electric fuse storage units sharing the same first word line with the electric fuse storage unit scheduled to be read is conducted, a second word line is connected with a high level, a second transistor connected with the second word line is conducted, wherein the second word line is connected with one of the other electric fuse storage units, and then each first transistor in the other electric fuse storage units and the conducted second transistor are connected in series to serve as a reading path and used for achieving reading operation.
Specifically, referring to fig. 4, the word line WL1 and the word line WL11 are turned on, each first transistor 21 in each electric fuse memory cell 30 is turned on, and the word line WL21 connected to the gate of one of the second transistors 22 is turned on to turn on the second transistor 22, so that the first transistor in the electric fuse memory cell 30 on the right side in fig. 4 and the second transistor connected to the word line WL21 are connected in series for performing a read operation, that is, a current path shown by an arrow in fig. 4 is a read path including the electric fuse in the electric fuse memory cell on the left side, the first transistor 21 in the electric fuse memory cell 30 on the right side and the second transistor connected to the word line WL21 in a series circuit. It is noted that although the word line WL1 and the word line WL11 are not shown connected together, they are actually the same word line and are not shown here for convenience.
Since the plurality of first transistors and the one second transistor are connected in series, the resistance value of the read path can be regarded as the sum of the resistance values of the plurality of first transistors and the one second transistor, and therefore, when the total resistance value is slightly larger than the resistance value of the read path in the prior art, the read path can play a role in limiting the read current. Therefore, the size of the first transistor and the second transistor can be significantly reduced compared to the size of the read operation transistor in the prior art, so that the area of the electrical fuse memory array can be significantly reduced.
For example, a memory array with 64 × 16 1 for 1K bit (bits) eFuses includes A [1:1] to A [64:16], and 3 devices in the eFuse memory array include an eFuse, a first transistor and a second transistor, and for convenience, the eFuse in the eFuse macro cell A [1:1] is defined as AR [1:1], the first transistor is defined as ACN [1:1], and the second transistor is defined as APN [1:1 ]. Assuming 100 times the current measured during firing, the size of the memory cell in the embodiment of the present invention can be reduced by approximately 50% compared to the prior art. The size of the NMOS transistor typically accounts for 80% of the memory cell size in the prior art.
In the embodiment of the present invention, the on-state current (saturation current) Ids of the transistor is proportional to the size of the memory cell. If the on-current Ids of the first transistor is made to be about 0.16 times the Ids of the prior art NMOS transistor and the Ids of the second transistor is made to be about 0.2 times the Ids of the prior art NMOS transistor. The parallel firing current when turning on enough of the first and second transistors will be greater than the prior art single path firing current. For example, 16 first transistors and 17 second transistors, which are located in the same word line or the same row, may also turn on more first transistors and second transistors, for example, ACN [14:1] to ACN [46:1] and APN [14:1] to APN [46:1] in the memory array, which may make the fuse current larger, for example, may increase to 102.1% of the fuse current in the prior art, thereby blowing the electrical fuse and realizing the write operation.
And when the read operation is carried out, 16 first transistors and one second transistor are connected in series, the read current is reduced by nearly 100 times of the original burning current. For example, reading eFuse A [30:1] data in an eFuse memory cell, the read path may be eFuse AR [30:1], ACN [31:1] to ACN [46:1] and APN [46:1] in the memory array, and the read current may be reduced, for example, to 0.05.
The size of the electrical fuse memory cell can be reduced approximately to 48.8% of the prior art, for example, if the size of the memory cell of the prior art is 1 unit, the size of the electrical fuse AR is 0.2 unit, and the sum of the sizes of the first transistor and the second transistor is 0.8 × 0.16+0.2 unit, so that the total size of the electrical fuse memory cell is 0.488 unit, which is 48.8% of the size of the memory cell of the prior art.
In summary, one NMOS transistor is added to connect with its adjacent efuse memory cell, so as to implement that the NMOS transistor of a plurality of adjacent memory cells is connected in series as a read path, and compared with the prior art that only one pull-down NMOS transistor with a larger size is used as a read path, the embodiment of the present invention can implement limitation on the read current by connecting a plurality of NMOS transistors with a smaller size in series, so that the number of read operations is not limited. And the writing operation is realized by connecting a plurality of pull-down NMOS transistors in parallel, so that the sizes of the first transistor and the second transistor in each efuse memory cell are both reduced, and the sizes of the memory cell and the memory array are both reduced obviously.
The present invention has been illustrated by the above two embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the above-mentioned embodiments, and that many variations and modifications may be made in accordance with the teaching of the present invention, for example, the first transistor is a PMOS transistor, and the same function may be achieved, and these variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (8)
1. An electrical fuse memory array, comprising:
the memory comprises a plurality of first word lines, a plurality of independent second word lines and a plurality of bit lines which are arranged in a crossed mode with the first word lines and the second word lines;
a plurality of e-fuse memory cells arranged in a plurality of rows and columns, each of the e-fuse memory cells comprising: an electrical fuse having a first end and a second end opposite the first end; a first transistor, a gate of the first transistor is connected to the first word line, a drain of the first transistor is connected to the second end of the electrical fuse, a source of the first transistor of a current column of electrical fuse memory cells is connected to a drain of a first transistor of a previous column of adjacent electrical fuse memory cells, and a drain of the first transistor of a current column of electrical fuse memory cells is connected to a source of a first transistor of a next column of adjacent electrical fuse memory cells, wherein the adjacent electrical fuse memory cells share the same first word line; and a drain of the second transistor is connected with the second end of the electric fuse, a source of the second transistor is grounded, and a gate of the second transistor is connected with the second word line, wherein the gate of each second transistor is respectively connected with different second word lines.
2. The efuse memory array of claim 1, further comprising a plurality of PMOS transistors, each PMOS transistor having a drain connected to the bit line of its corresponding column or row.
3. The electrical fuse memory array of claim 1, wherein the first transistor and the second transistor are both NMOS transistors.
4. The efuse memory array of claim 1, wherein the first end of the efuse is connected to the bit line of the column or row in which it is located.
5. The efuse memory array of claim 1, wherein the first transistor is a PMOS transistor.
6. The efuse memory array of claim 1, wherein the number of efuse memory cells is greater than or equal to 2.
7. A method of using the electrical fuse memory array of any of claims 1-6, comprising:
connecting one of the plurality of first word lines with a high level to enable each first transistor in the plurality of electric fuse storage units connected with the first word line to be conducted, connecting a second word line connected with each second transistor in the plurality of electric fuse storage units with a high level to enable each second transistor to be conducted, enabling the second transistors in the plurality of electric fuse storage units to form a parallel circuit, and simultaneously sequentially opening PMOS transistors corresponding to the plurality of electric fuse storage units, so that the writing operation of the corresponding electric fuse storage units can be realized.
8. A method of using the electrical fuse memory array of any of claims 1-6, comprising:
when storage data in one electric fuse storage unit is scheduled to be read, a first word line connected with the electric fuse storage unit is connected with a high level, meanwhile, each first transistor in other electric fuse storage units sharing the same first word line with the electric fuse storage unit scheduled to be read is conducted, a second word line is connected with a high level, a second transistor connected with the second word line is conducted, wherein the second word line is connected with one of the other electric fuse storage units, and then each first transistor in the other electric fuse storage units and the conducted second transistor are connected in series to serve as a reading path and used for achieving reading operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510660942.7A CN106601300B (en) | 2015-10-14 | 2015-10-14 | Electric fuse storage unit, electric fuse storage array and using method thereof |
Applications Claiming Priority (1)
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| US8542549B2 (en) * | 2011-08-08 | 2013-09-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical fuse bit cell |
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