CN106601300A - Electric fuse memory cell, electric fuse storage array and usage method thereof - Google Patents
Electric fuse memory cell, electric fuse storage array and usage method thereof Download PDFInfo
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- CN106601300A CN106601300A CN201510660942.7A CN201510660942A CN106601300A CN 106601300 A CN106601300 A CN 106601300A CN 201510660942 A CN201510660942 A CN 201510660942A CN 106601300 A CN106601300 A CN 106601300A
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Abstract
The invention provides an electric fuse memory cell, an electric fuse storage array and a usage method thereof, and relates to the field of semiconductor technology. The electric fuse memory cell comprises the following components: an electric fuse with a first terminal and a second terminal; a first transistor, wherein a grid of the first transistor is connected to a first word line, a drain electrode of the first transistor is connected to the second terminal of an electric fuse, and a source electrode and a drain electrode of the first transistor are respectively connected to the adjacent electric fuse memory cell; a second transistor, wherein the drain electrode of the second transistor and the second terminal of the electric fuse are connected, and a grid of the second transistor is connected to a second word line. Multiple NMOS transistors with small dimensions are connected in series connection in order to realize restriction of a read-out current, and the frequency of read operation is not limited. Multiple pull-down NMOS transistors are connected in parallel mode, in order to realize write operation, dimensions of the first transistor and the second transistor in each efuse memory cell are reduced, and dimensions of the memory cell and the storage array are substantially reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, single in particular to a kind of storage of electric fuse
Unit, electric fuse storage array and its using method.
Background technology
In technical field of semiconductors, electrically programmable fuse (eFuse) technology due to with
The advantage such as CMOS logic device is compatible and easy to use and as disposable programmable (OTP)
Memorizer is widely used in many circuits.
EFuse technology is theoretical according to electromigration, by electric fuse by the fusing of electric current whether depositing
Storage information, polysilicon electric fuse resistance very little before fusing, the electricity after lasting high current fusing
Infinity is visually done in resistance, and the state of electric fuse fracture is by permanent holding.EFuse technology
It has been widely used in redundant circuit to improve the problem of chip failure or the ID of chip, if
Standby basic code etc. is replacing the disposable programmable memory of low capacity.
Figure 1A shows the schematic diagram of existing eFuse memory element, eFuse memory element,
Including electric fuse and a nmos pass transistor, Figure 1B shows existing eFuse storages battle array
The schematic diagram of row, it includes rows and columns eFuse memory element, and each eFuse storage is single
Grid connection wordline WL of the NMOS in unit, wordline WL is the signal for controlling read operation
Line, is limited by the electric current of electric fuse by read current and persistent period, therefore, limit
The number of times of read operation.
Because the width of polysilicon electric fuse is more and more narrow, change is limited more for read operation
Seriously, for example in 28nm node technologies.The presence of the problems referred to above so that eFuse technology
In being only used for the application of limited read operation number of times, for example, when system is opened, with accordingly
SRAM store eFuse macro-data；Again for example, stored ID is seldom read,
Unless needed for inspection chip id.
Therefore, it is necessary to a kind of new electric fuse memory element and electric fuse storage array are proposed,
To solve above-mentioned technical problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be concrete real
Apply in mode part and further describe.The Summary of the present invention is not meant to
Attempt the key feature and essential features for limiting technical scheme required for protection, less
Mean the protection domain for attempting to determine technical scheme required for protection.
For the deficiencies in the prior art, it is single that the embodiment of the present invention one provides a kind of electric fuse storage
Unit, including：
Electric fuse, the electric fuse has first end and second end relative with the first end；
The first transistor, the grid of the first transistor connects the first wordline, and described first is brilliant
The drain electrode of body pipe is connected with second end of the electric fuse, the source electrode of the first transistor
The electric fuse memory element being adjacent respectively with drain electrode is connected；
Transistor seconds, second end of the drain electrode of the transistor seconds and the electric fuse
Connection, the grid of the transistor seconds connects the second wordline.
Further, the first transistor and the transistor seconds are nmos pass transistor.
Further, the first transistor is PMOS transistor.
Further, the source ground of the transistor seconds.
Further, the first end connection bit line of the electric fuse.
Further, the source electrode of the first transistor and the first of adjacent electric fuse memory element
The drain electrode of transistor is connected, the drain electrode of the first transistor and adjacent electric fuse memory element
The first transistor source electrode be connected.
The embodiment of the present invention two provides a kind of electric fuse storage array, including：
Some articles of the first wordline, some articles of the second independent wordline and with first wordline and
Two wordline some bit lines arranged in a crossed manner；
Into several electric fuse memory element of rows and columns arrangement, each described electric fuse is deposited
Storage unit includes：Electric fuse, the electric fuse has first end and relative with the first end
Second end；The first transistor, the grid of the first transistor connects first wordline, institute
State the drain electrode of the first transistor to be connected with second end of the electric fuse, the first crystal
The drain electrode of the source electrode of pipe and the first transistor of adjacent electric fuse memory element is connected, and described the
The drain electrode of one transistor is connected with the source electrode of the first transistor of adjacent electric fuse memory element,
Wherein described adjacent electric fuse memory element shares the first wordline described in same；Second crystal
Pipe, the drain electrode of the transistor seconds is connected with second end of the electric fuse, and described the
The source ground of two-transistor, the grid of the transistor seconds connects second wordline, its
In, the grid of each transistor seconds connects respectively different second wordline.
Further, also including several PMOS transistors, each described PMOS transistor
Drain electrode respectively with its column or the bit line of row.
Further, the first transistor and the transistor seconds are nmos pass transistor.
Further, the first end of the electric fuse connects institute's rheme of its column or row
Line.
Further, the first transistor is PMOS transistor.
Further, the number of the electric fuse memory element is more than or equal to 2.
An aspect of of the present present invention also provides a kind of using method of aforesaid electric fuse storage array,
Including：
One in some the first wordline is connect into high level, makes to be connected with first wordline
Some electric fuse memory element in the conducting of each the first transistor, and will be with some electricity
The second wordline that each transistor seconds in fuse storage unit is connected connects high level, makes every
The individual transistor seconds is both turned on, described second in described several electric fuse memory element
Transistor constitutes parallel circuit, while opening relative with some electric fuse memory element successively
The PMOS transistor answered, you can realize for the write operation of corresponding electric fuse memory element.
Another aspect of the present invention also provides a kind of user of aforesaid electric fuse storage array
Method, including：
The predetermined data storage read in an electric fuse memory element, then will be with the electric fuse storage
The first wordline that unit is connected connects high level, while making to be deposited with the electric fuse of the predetermined reading
Storage unit shares each in some other electric fuse memory element of same first wordline
The first transistor is turned on, and second wordline is connect into high level, makes to be connected with second wordline
Transistor seconds conducting, wherein, described other electric fuses storages of second wordline connection are single
One in unit, then each the first transistor in described some other capacitive memory cells and
Path is read in the transistor seconds series connection conduct of conducting, for realizing read operation.
In sum, by increase the efuse being adjacent is deposited with a nmos pass transistor
Storage unit connects, and then realizes coming the nmos pass transistor of multiple consecutive storage units of connecting
It is only brilliant than larger pull-down NMOS using a size with prior art as path is read
Body pipe is compared as path is read, and the embodiment of the present invention can be less by the multiple sizes of series connection
Nmos pass transistor is realizing the restriction for read current so that read operation number of times is unrestricted,
And making the parallel connection of multiple pulldown NMOS transistors by way of, realize write operation, therefore often
The size of the first transistor and transistor seconds in individual efuse memory element reduces so that
The size of memory element and the size of storage array are substantially reduced.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A shows the structural representation of existing eFuse memory element；
Figure 1B shows the structural representation of existing eFuse storage arrays；
Fig. 2 is the structural representation of the eFuse memory element of one embodiment of the present of invention；
Fig. 3 shows the structural representation of the eFuse storage arrays in one embodiment of the present of invention
Figure；
Fig. 4 shows the structure of the adjacent eFuse memory element of one embodiment of the present of invention
Schematic diagram.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
Can be carried out without the need for one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, for some technical characteristics well known in the art are not described.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
In order to clear, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from start to finish
Icon note represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer and
It is adjacent, be connected or coupled to other elements or layer, or there may be element between two parties or layer.
Conversely, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then there is no element between two parties or layer.Should
Understand, although can using term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, without departing from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience here and by using from
And an element or feature shown in figure are described with other elements or the relation of feature.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and operate
In device different orientation.For example, if the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
Be other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " may include upper and lower two orientations.Device can additionally be orientated and (be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When here is used, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " including ", when using in this specification, determine the feature,
The presence of integer, step, operation, element and/or part, but be not excluded for it is one or more its
The presence or addition of its feature, integer, step, operation, element, part and/or group.
When here is used, term "and/or" includes any and all combination of related Listed Items.
Herein with reference to the horizontal stroke of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Sectional view is describing inventive embodiment.As a result, it is contemplated that due to such as manufacturing technology and/
Or from the change of shown shape caused by tolerance.Therefore, embodiments of the invention should not limit to
In the given shape in area shown here, but including inclined due to for example manufacturing caused shape
Difference.For example, be shown as the injection region of rectangle its edge generally there is circle or bending features and
/ or implantation concentration gradient, rather than the binary change from injection region to non-injection regions.Equally,
The disposal area formed by injection can cause the surface that the disposal area and injection are passed through when carrying out
Between area in some injection.Therefore, the area for showing in figure is substantially schematic, it
Shape be not intended display device area true form and be not intended limit the present invention
Scope.
In order to thoroughly understand the present invention, detailed structure will be proposed in following description, so as to
Explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, so
And in addition to these detailed descriptions, the present invention can also have other embodiment.
Embodiment one
Below, deposit come a kind of eFuse for describing one embodiment of the present of invention proposition with reference to Fig. 2
Storage unit.
Exemplarily, eFuse memory element of the invention as shown in Figure 2, including following unit
Part：
Including electric fuse 20, the electric fuse 20 have first end 1 and with the first end 1
The second relative end 2.The first end connection bit line (not shown) of the electric fuse.
Exemplarily, the material of the electric fuse 20 can include polysilicon.Wherein described
One end 1 is the anode of electric fuse 20, and second end is the negative electrode of electric fuse 20.
Also include the first transistor 21, the grid of the first transistor 21 connects the first wordline
WL1, the drain electrode N_A of the first transistor 21 and described the second of the electric fuse 20
End 2 connects, the source electrode N_B of the first transistor 21 and drain N_A respectively with its phase
Adjacent electric fuse memory element is connected.Exemplarily, the source electrode N_B of the first transistor 21
It is connected with the drain electrode N_A of the first transistor 21 of adjacent electric fuse memory element, described the
The drain electrode N_A of one transistor 21 and the source of the first transistor of adjacent electric fuse memory element
Pole N_B is connected.
Also include transistor seconds 22, the drain electrode of the transistor seconds 22 and the electric fuse
20 second end 2 connects, and the grid of the transistor seconds 22 connects the second wordline
WL2.Further, the source ground of the transistor seconds 22.
In one example, the first transistor 21 be nmos pass transistor, described second
Transistor 22 is nmos pass transistor.Wherein, the size of the first transistor 21 compares institute
The size for stating transistor seconds 22 is little.
In above-mentioned efuse memory element, the size of the first transistor 21 can be than common
Nmos pass transistor is little, specifically can be selected according to the quantity of the first transistor of actual series connection
The size of suitable the first transistor.In the same manner, the size of transistor seconds 22 can be also reduced,
It is set to be much smaller than the size of nmos pass transistor in prior art, its size can be by actually depositing
The quantity of the transistor seconds in parallel in storage array is calculated.
By increasing the efuse memory element being adjacent is connected with a nmos pass transistor
Connect, and then realize being used as reading road by the nmos pass transistor of multiple consecutive storage units of connecting
Footpath, only a size is used than larger pulldown NMOS transistor conduct with prior art
Read path to compare, the embodiment of the present invention can be by the less NMOS crystal of the multiple sizes of series connection
Pipe realizing the restriction for read current, and by making multiple pulldown NMOS transistors in parallel
Mode, write operation is realized, while the first transistor in each efuse memory element and
The size of two-transistor reduces, therefore the size of memory element is substantially reduced.
The challenge for wherein overcoming read operation number of times is mainly manifested in following aspect：
(1) size of maximum read current (read current) is restricted, and for example, reads electricity
Fuse electric current (burning current) for maximum 1/10 is flowed, when maximum fuses electric current for 50mA
When, then maximum read current is 5mA；Maximum readout time is also restricted accordingly, for example,
Maximum readout time (read flow time) is 1s, then read access number of times is about 10000000
Secondary, calculating formula is 1/100ns=10000000.
(2) maximum measured (when not fusing) before fusing flows through electric current and is restricted, for example
Fuse electric current for maximum 1/100, then flow through electric current for 5/100=0.5mA.And without secondary
Number is limited.
Exemplarily, the first transistor can also be capable of achieving phase with PMOS transistor
Same function.
In sum, the electric fuse memory element in the embodiment of the present invention is by increasing and one
Nmos pass transistor connects the efuse memory element being adjacent so that the number of times of read operation
It is unrestricted, while the realization of write operation is not affected, and also the size of memory element is substantially reduced.
Embodiment two
A kind of electric fuse storage array is also provided in another embodiment of the present invention, the electric fuse is deposited
Storage array includes the electric fuse memory element in previous embodiment.
Specifically, the electric fuse storage array in the embodiment of the present invention is entered with reference to Fig. 3 and Fig. 4
Row is described in detail.
As shown in figure 3, the electric fuse storage array of this enforcement includes that several electric fuse storages are single
Unit 30, the 30 one-tenth rows and columns arrangements of described several electric fuse memory element, for example, row
M rows are arranged into, n row, wherein m and n is integer.Illustrate only in Fig. 3 including 2 rows and 2
The memory array structure of 4 electric fuse memory element of row, for other situation rows and columns
Electric fuse storage array be equally applicable.
Electric fuse storage array in the embodiment of the present invention also includes some the first wordline
WL1, some the second independent wordline WL2 and with first wordline WL1 and the second word
BL line WL2 arranged in a crossed manner；
Exemplarily, the quantity of bit line BL is corresponding with the columns of electric fuse memory element 30,
For example, there is n row electric fuse memory element, then there are n row bit line BL.First wordline WL1
Quantity it is corresponding with the line number of electric fuse memory element 30, for example, have m row electric fuses to deposit
Storage unit, then can arrange wordline WL1 of m rows first.Connect it per wordline WL1 of a line first
The grid of the first transistor in the multiple electric fuse memory element 30 being expert at.
In another example, bit line BL arrangement in a row, then the quantity of bit line deposit with electric fuse
The line number correspondence of storage unit, and the first wordline WL1 arrayed in columns, then the first wordline WL1
Columns it is corresponding with the columns of electric fuse memory element 30.
Some the second independent wordline WL2, are used to control and it per wordline WL2 of bar second
The conducting and cut-off of the transistor seconds in connected electric fuse memory element, due to the second wordline
WL2 is independent, therefore for the control of transistor seconds is also independent.Exemplarily,
The quantity of the second wordline WL2 is equal with the quantity of transistor seconds.
Electric fuse storage array in the embodiment of the present invention also includes several PMOS transistors
31, each PMOS transistor 31 drain electrode respectively with its column or the bit line of row
BL is connected, and the quantity of the PMOS transistor can be equal to the columns of electric fuse memory element,
For example, if several electric fuse memory element 30 are arranged as n row, there is n PMOS
Transistor 31, the corresponding string electric fuse memory element of each PMOS transistor 31.Enter one
Step ground, the source electrode connection power line Vdd of each PMOS transistor 31, power line
Vdd is applied to offer supply voltage, and the grid of each PMOS transistor is connected to row
Decoder, column decoder is applied to each column PMOS transistor offer column decoding signal, should
Column decoding signal is used to control the on or off of PMOS transistor.
As shown in figure 4, exemplarily, each described electric fuse memory element 30 includes：Electricity
Fuse 20, the electric fuse 20 has first end and second end relative with the first end；
The first transistor 21, the grid of the first transistor 21 connect its be expert at described first
Wordline WL1, the drain electrode of the first transistor 21 and described the second of the electric fuse 20
End connection, the source electrode N_B of the first transistor 21 and adjacent electric fuse memory element
The drain electrode N_A of the first transistor 21 is connected, the drain electrode N_A of the first transistor 21 with
The source electrode N_B of the first transistor of adjacent electric fuse memory element is connected,
Wherein described adjacent electric fuse memory element 30 shares the first wordline described in same
WL1；Transistor seconds 22, the drain electrode of the transistor seconds 22 and the electric fuse 20
Second end connection, the source ground of the transistor seconds 22, second crystal
The grid of pipe 22 connects second wordline WL2, wherein, each described transistor seconds 22
Grid connect the second different wordline WL2 respectively.
Exemplarily, the material of the electric fuse can include polysilicon.Wherein described first end
For the anode of electric fuse, second end is the negative electrode of electric fuse.
Further, the first end of the electric fuse connects the described of its column or row
Bit line BL.
In the electric fuse storage array of the embodiment of the present invention, it is possible to use size is less
Nmos pass transistor is used as the first transistor and transistor seconds, the wherein size of transistor seconds
The first transistor can be slightly larger than.
Further, in electric fuse storage array, the quantity of the electric fuse memory element is big
In or equal to 2.
Another aspect of the present invention also provides a kind of user of above-mentioned electric fuse storage array
Method, including：One in some the first wordline is connect into high level, is made and first wordline
Each the first transistor conducting in some electric fuse memory element being connected, and will with it is described
The second wordline that each transistor seconds in some electric fuse memory element is connected connects high electricity
It is flat, it is both turned on each described transistor seconds, in described several electric fuse memory element
The transistor seconds constitutes parallel circuit, while open being stored with some electric fuses successively
The corresponding PMOS transistor of unit, you can realize for corresponding electric fuse memory element
Write operation.
Specifically, with reference to Fig. 4, it is specifically described by taking two connected memory element as an example,
Wordline WL1 and wordline WL11 are connect into high level, is made every in two electric fuse memory element
Individual the first transistor 21 is turned on, and wherein wordline WL1 and wordline WL11 are located at same a line, its
In same wordline, and by with each electric fuse memory element in each transistor seconds 22
The second wordline WL2, WL21 for being connected of grid connect high level, make each transistor seconds
22 conductings, then the transistor seconds 22 in described several electric fuse memory element is constituted
Parallel circuit, while the PMOS transistor corresponding with electric fuse memory element is opened successively,
It is capable of achieving for the write operation of corresponding electric fuse memory element.
In write operation device, electric fuse must run into and fuse electric current, and non-fuse fuse resistor
Device must flow out and flow through the also big electric current of electric current than maximum measurement.And adopt the present invention
The electric fuse storage array of embodiment, can cause transistor seconds to form parallel circuit so as to write
The total current increase of circuit, electric fuse more can fuse, and realize write operation.Meanwhile, second
The size of transistor and the first transistor is less, will be substantially reduced the area of memory element.
Another aspect of the present invention, also provides a kind of user of above-mentioned electric fuse storage array
Method, including：The predetermined data storage read in an electric fuse memory element, then will be with the electric smelting
The first wordline that silk memory element is connected connects high level, while making the electricity with the predetermined reading
Fuse storage unit is shared in some other electric fuse memory element of same first wordline
The conducting of each the first transistor, second wordline is connect into high level, make and second wordline
The transistor seconds conducting being connected, wherein, other electric fuses described in the second wordline connection
One in memory element, then each first crystal in described some other capacitive memory cells
Path is read in pipe and the transistor seconds series connection conduct for turning on, for realizing read operation.
Specifically, with reference to Fig. 4, wordline WL1 and wordline WL11 are connect into high level, each
Each the first transistor 21 in electric fuse memory element 30 is both turned on, and will be with one of them
Wordline WL21 that the grid of transistor seconds 22 is connected connects high level, makes second crystal
Pipe 22 is turned on, then in Fig. 4 right side electric fuse memory element 30 in the first transistor and with
The connected transistor seconds series connection of wordline WL21, for realizing read operation, namely such as Fig. 4
Current path shown in middle arrow as reads path, and it is included in the electric fuse memory element of left side
Electric fuse, the first transistor 21 in right side electric fuse memory element 30 and with wordline WL21
Connected transistor seconds, the series circuit of composition.Although it should be noted that illustrating in figure
Wordline WL1 and wordline WL11 do not link together, but it is actual its be same wordline,
Here is for the ease of illustrating and is not connected with.
Due to multiple the first transistors and the transistor seconds of connecting, therefore read the resistance in path
Value can be considered as the resistance value sum of multiple the first transistors and a transistor seconds, therefore,
In resistance value of its total resistance value slightly larger than the reading path of prior art, you can play restriction
The effect of read current.Therefore, the size of the first transistor and transistor seconds can be relatively existing
The size of the read operation transistor of technology is substantially reduced, therefore the area of electric fuse storage array also can
It is obviously reduced.
By taking the storage array with 64*16 of 1K bits (bits) electric fuse as an example, storage
Array includes A [1:1] to A [64:16], 3 devices in electric fuse storage array include electric smelting
Silk, the first transistor and transistor seconds, are easy to statement in order to after, define the grand list of electric fuse
First A [1:1] electric fuse in is AR [1:1], the first transistor is ACN [1:1], second is brilliant
Body pipe is APN [1:1].Hypothesis fuses 100 times that flow through electric current measured during electric current, then originally
The size of the memory element in inventive embodiments can reduce compared with prior art nearly 50%.
Generally in the prior art the size of nmos pass transistor accounts for the 80% of memory cell size.
In the embodiment of the present invention, using transistor conducting electric current (saturation current) Ids and size into
Direct ratio is assessing the diminution ratio of memory element.If making conducting electric current Ids of the first transistor
About 0.16 times of the Ids of prior art nmos pass transistor, and the Ids of transistor seconds
About 0.2 times of the Ids of prior art nmos pass transistor.Then when opening all of enough the
Parallel connection when one transistor and transistor seconds fuses electric current by than the single-pathway of prior art
Fuse electric current big.Such as 16 the first transistors and 17 transistor secondses, it is located at identical
Wordline or same a line, can also open more the first transistors and transistor seconds, for example,
ACN [14 in storage array:1] to ACN [46:1] and APN [14:1] extremely
APN[46:1], can cause to fuse the bigger of electric current change, for example, it is possible to increase in prior art
The 102.1% of electric current, and then the electric fuse that fuses are fused, write operation is realized.
And when read operation, when 16 the first transistors of series connection and a transistor seconds, read electricity
Flow to reduce and close 100 times fuse electric current originally.For example in reading an electric fuse memory element
Electric fuse A [30:1] data, then it can be the electric fuse AR [30 in storage array to read path:1],
ACN[31:1] to ACN [46:1] and APN [46:1], then read current will reduce, for example
Original 0.05 can be reduced to.
The size of electric fuse memory element can be approximate be reduced into the 48.8% of prior art, example
Such as, if the memory cell size of prior art is 1 unit, the size of electric fuse AR is
The size sum of 0.2 unit, the first transistor and transistor seconds is 0.8* (0.16+0.2)
Individual unit, therefore total size of electric fuse memory element is 0.488 unit, is existing skill
The 48.8% of the size of the electric fuse memory element of art.
In sum, by increase the efuse being adjacent is deposited with a nmos pass transistor
Storage unit connects, and then realizes coming the nmos pass transistor of multiple consecutive storage units of connecting
It is only brilliant than larger pull-down NMOS using a size with prior art as path is read
Body pipe is compared as path is read, and the embodiment of the present invention can be less by the multiple sizes of series connection
Nmos pass transistor is realizing the restriction for read current so that the number of times of read operation is unrestricted
System.And by way of making multiple pulldown NMOS transistors in parallel, write operation is realized, because
The size of the first transistor and transistor seconds in this each efuse memory element reduces,
So that the size of memory element and storage array is substantially reduced.
The present invention is illustrated by above-mentioned two embodiment, but it is to be understood that,
Above-described embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to institute
In the scope of embodiments of description.In addition it will be appreciated by persons skilled in the art that the present invention simultaneously
Be not limited to above-described embodiment, teaching of the invention can also make more kinds of modifications and
Modification, for example, the first transistor is PMOS transistor, is also capable of achieving same function,
These variants and modifications are all fallen within scope of the present invention.The protection of the present invention
Scope is defined by the appended claims and its equivalent scope.
Claims (14)
1. a kind of electric fuse memory element, including：
Electric fuse, the electric fuse has first end and second end relative with the first end；
The first transistor, the grid of the first transistor connects the first wordline, and described first is brilliant
The drain electrode of body pipe is connected with second end of the electric fuse, the source electrode of the first transistor
The electric fuse memory element being adjacent respectively with drain electrode is connected；
Transistor seconds, second end of the drain electrode of the transistor seconds and the electric fuse
Connection, the grid of the transistor seconds connects the second wordline.
2. electric fuse memory element according to claim 1, it is characterised in that described
The first transistor and the transistor seconds are nmos pass transistor.
3. electric fuse memory element according to claim 1, it is characterised in that described
The first transistor is PMOS transistor.
4. electric fuse memory element according to claim 1, it is characterised in that described
The source ground of transistor seconds.
5. electric fuse memory element according to claim 1, it is characterised in that described
The first end connection bit line of electric fuse.
6. electric fuse memory element according to claim 1, it is characterised in that described
The drain electrode phase of the source electrode of the first transistor and the first transistor of adjacent electric fuse memory element
Even, the drain electrode of the first transistor and the first transistor of adjacent electric fuse memory element
Source electrode is connected.
7. a kind of electric fuse storage array, including：
Some articles of the first wordline, some articles of the second independent wordline and with first wordline and
Two wordline some bit lines arranged in a crossed manner；
Into several electric fuse memory element of rows and columns arrangement, each described electric fuse is deposited
Storage unit includes：Electric fuse, the electric fuse has first end and relative with the first end
Second end；The first transistor, the grid of the first transistor connects first wordline, institute
State the drain electrode of the first transistor to be connected with second end of the electric fuse, the first crystal
The drain electrode of the source electrode of pipe and the first transistor of adjacent electric fuse memory element is connected, and described the
The drain electrode of one transistor is connected with the source electrode of the first transistor of adjacent electric fuse memory element,
Wherein described adjacent electric fuse memory element shares the first wordline described in same；Second crystal
Pipe, the drain electrode of the transistor seconds is connected with second end of the electric fuse, and described the
The source ground of two-transistor, the grid of the transistor seconds connects second wordline, its
In, the grid of each transistor seconds connects respectively different second wordline.
8. electric fuse storage array according to claim 7, it is characterised in that also wrap
Include several PMOS transistors, the drain electrode of each PMOS transistor respectively with its institute
In row or the bit line of row.
9. electric fuse storage array according to claim 7, it is characterised in that described
The first transistor and the transistor seconds are nmos pass transistor.
10. electric fuse storage array according to claim 7, it is characterised in that described
The first end of electric fuse connects the bit line of its column or row.
11. electric fuse storage arrays according to claim 7, it is characterised in that described
The first transistor is PMOS transistor.
12. electric fuse storage arrays according to claim 7, it is characterised in that described
The number of electric fuse memory element is more than or equal to 2.
A kind of 13. electric fuse storage arrays as any one of claim 7 to 12
Using method, including：
One in some the first wordline is connect into high level, makes to be connected with first wordline
Some electric fuse memory element in the conducting of each the first transistor, and will be with some electricity
The second wordline that each transistor seconds in fuse storage unit is connected connects high level, makes every
The individual transistor seconds is both turned on, described second in described several electric fuse memory element
Transistor constitutes parallel circuit, while opening relative with some electric fuse memory element successively
The PMOS transistor answered, you can realize for the write operation of corresponding electric fuse memory element.
A kind of 14. electric fuse storage arrays as any one of claim 7 to 12
Using method, including：
The predetermined data storage read in an electric fuse memory element, then will be with the electric fuse storage
The first wordline that unit is connected connects high level, while making to be deposited with the electric fuse of the predetermined reading
Storage unit shares each in some other electric fuse memory element of same first wordline
The first transistor is turned on, and second wordline is connect into high level, makes to be connected with second wordline
Transistor seconds conducting, wherein, described other electric fuses storages of second wordline connection are single
One in unit, then each the first transistor in described some other capacitive memory cells and
Path is read in the transistor seconds series connection conduct of conducting, for realizing read operation.
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| CN113327641A (en) * | 2020-02-28 | 2021-08-31 | 中芯国际集成电路制造(上海)有限公司 | eFuse storage unit, eFuse storage array, using method of eFuse storage array and eFuse system |
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