KR102173038B1 - Anti-fuse of semiconductor device and method for fabricating the same - Google Patents

Abstract

The present invention relates to an anti-fuse array of a semiconductor device and a method of operating the same, and more particularly, to an anti-fuse array technology capable of minimizing the area consumption of the anti-fuse array.
An anti-fuse array of a semiconductor device according to an embodiment of the present invention includes: a plurality of first transistors formed by being connected in a matrix structure on a semiconductor substrate; A plurality of second transistors formed at respective first ends of the plurality of first transistors in a first direction of the matrix structure; And a plurality of third transistors formed at each of second ends of the plurality of first transistors in a second direction perpendicular to the first direction.

Description

Anti-fuse array of semiconductor device and its operation method {ANTI-FUSE OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to an anti-fuse array of a semiconductor device and a method of operating the same, and more particularly, to an anti-fuse array technology capable of minimizing area consumption of the anti-fuse array.

In recent years, with the rapid spread of information media such as computers, semiconductor devices are also rapidly developing. In terms of its function, semiconductor devices are required to operate at high speed and have a large storage capacity. Accordingly, semiconductor device manufacturing technology is developing in the direction of improving the degree of integration, reliability, and response speed.

In such a semiconductor device, defects may occur during a manufacturing process, and cells having such poor conditions can be detected early and regenerated through a repair process.

Anti-fuse is required for this repair process, and anti-fuse not only enables repair at the package level, but also reduces the dependence of the existing laser fuse equipment and process due to the increase in net die, improvement of product characteristics, and high integration. It is a trend that is being used a lot to overcome.

An embodiment of the present invention has an object to improve the production rate by reducing the area of the antifuse array.

An anti-fuse array of a semiconductor device according to an embodiment of the present invention includes: a plurality of first transistors formed by being connected in a matrix structure on a semiconductor substrate; A plurality of second transistors formed at each of first ends of the plurality of first transistors in a first direction of the matrix structure; And a plurality of third transistors formed at each of second ends of the plurality of first transistors in a second direction perpendicular to the first direction.

In addition, a method of operating an anti-fute array according to the present invention includes: a plurality of first transistors connected to each other in a matrix structure on a semiconductor substrate; A plurality of second transistors formed at respective first ends of the plurality of first transistors in a first direction of the matrix structure; And a plurality of third transistors formed at each of second ends of the plurality of first transistors in a second direction perpendicular to the first direction, the method of operating an anti-fuse array comprising: Applying a first voltage to at least one; Applying a second voltage to at least one of the plurality of third transistors; A step in which the first transistor at a point where the second transistor to which the first voltage is applied and the third transistor to which the second voltage is applied is intersected by the difference between the first voltage and the second voltage is ruptured. Can include.

The present technology has the effect of improving the production rate by reducing the area of the anti-fuse array without adding a semiconductor device process.

1 is a circuit diagram of an antifuse array according to an embodiment of the present invention.
2 is a plan view of an antifuse array according to an embodiment of the present invention.
3 is a cross-sectional view of an antifuse array taken along an X-X' axis of the plan view of FIG. 3.
FIG. 4 is a cross-sectional view of an antifuse array taken along the Y-Y' axis of the plan view of FIG. 3.
5 is a diagram illustrating a method of operating a program of an antifuse array according to an embodiment of the present invention.
6 is a view for explaining a read operation method of an antifuse array according to an embodiment of the present invention.

Hereinafter, in order to describe in detail enough that those of ordinary skill in the art to which the present invention pertains can easily implement the technical idea of the present invention, a most preferred embodiment of the present invention will be described with reference to the accompanying drawings.

The antifuse array is composed of a plurality of program transistors, select transistors, and metal contacts. To program a selected cell, one program transistor, select transistor, and Each bit line (metal contact) must be selected.

That is, when a high voltage is applied to the program gate, the gate insulating film of the program transistor is ruptured due to a level difference with the low voltage applied through the bit line. At this time, when a certain voltage is applied to the select gate, a channel region is formed under the select gate, so that the high voltage applied to the program gate is output through a channel region under the select gate through a bit line (metal contact) on the side of the select gate. .

In the present invention, a program transistor is formed in a matrix structure in which the program gate line and the channel line intersect, and a select gate is formed at the end of the program gate line so that only the program gate selected by the select gate at the end is ruptured. can do.

Accordingly, compared to a structure in which the program gate and the select gate are formed in a one-to-one correspondence, the number of select transistors compared to the program transistor can be reduced, thereby minimizing the area of the antifuse array.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 6.

1 is a circuit diagram of an antifuse array according to an exemplary embodiment of the present invention, FIG. 2 is a perspective view of an antifuse array according to an exemplary embodiment of the present invention, and FIG. 3 is an antifuse cut in the plane of FIG. It is a cross-sectional view of the fuse array, and FIG. 4 is a cross-sectional view of the anti-fuse array of FIG. 3 taken along the Y-Y' axis.

First, referring to FIG. 1, the anti-fuse array according to the present invention includes a program transistor having a matrix structure (a first transistor 130) and a select transistor formed at an end of the program transistor 130 having a matrix structure in the first direction. It includes two transistors 110 and a select transistor (a third transistor 120) formed at an end of the program transistor 130 having a matrix structure in the second direction.

Referring to FIGS. 1 and 2 together to specifically describe the configuration of the anti-fuse array, a plurality of channels spaced apart from each other in a first direction in the semiconductor substrate 101 to form the program transistor 130 having a matrix structure Lines 103a to 103d are formed, and a plurality of gate lines 107a to 107d are formed to be spaced apart at predetermined intervals in a direction perpendicular to the channel lines 103a to 103d, and the channel lines 103a to 103d and the gate The lines 107a to 107d are vertically crossed, and one program transistor is formed at the crossing point.

At this time, the channel lines 103a to 103d may be formed through ion implantation or may be formed by depositing a material that can be used as a channel. In addition, gate insulating film lines 105a to 105d are formed between the semiconductor substrate 101 and the gate lines 107a to 107d, so that the gate insulating film lines 105a to 105d and the gate lines 107a to 107d are stacked. Have.

In addition, the gate insulating layer lines 105a to 105d and the gate lines 107a to 107d are sequentially stacked on the entire surface of the semiconductor substrate 101 with a gate insulating layer material and a gate conductive material, and then use a mask to form a line type gate insulating layer. It is formed by etching a material and a gate conductive material. Also, the gate lines 107a to 107d are formed in a stacked structure of the gate conductive material 11 and the capping layer 12, and the gate conductive material 13 may be formed of a conductive material such as polysilicon or tungsten.

On the other hand, the select transistor 110 is formed at the end side of the gate lines 107a to 107d of the program transistor 130 in the long axis direction and spaced apart from the gate lines 107a to 107d by a predetermined interval. 1, the select transistors 111 to 114 are formed in one-to-one correspondence with the gate lines 107a to 107d. In addition, the select transistor 110 includes select gates 110a to 110d on the semiconductor substrate between the channel regions 102a to 102d and the channel regions 104a to 104d, and the semiconductor substrate and the select gates 110a to 110d Gate insulating films 108a to 108d are provided therebetween. In addition, the select transistor 110 is electrically connected to the program transistor 130 and the metal structure 140.

In addition, the select transistor 120 is formed to be connected to the channel lines 103a to 103d at ends of the channel lines 103a to 103d of the program transistor 130 in the long axis direction. In this case, as shown in FIG. 1, the select transistors 121 to 124 are formed in a one-to-one correspondence with the channel lines 103a to 103d. In addition, the select transistor 120 includes gate insulating films 109a to 109d formed over the channel lines 103a to 103d and the channel regions 106a to 106d, and select gates formed over the gate insulating films 109a to 109d. 120a to 120d). In addition, the select transistor 120 is electrically connected by using the program transistor 130 and the channel lines 103a to 103d in common.

At this time, the gate insulating films 108a to 108d and the select gates 110a to 110d of the select transistor 110, the gate insulating films 109a to 109d of the select transistor 120, and the select gates 120a to 120d are the program transistor 130 ), the gate insulating layer lines 105a to 105d and the gate lines 107a to 107d are formed simultaneously. In addition, the select gates 110a to 110d and the select gates 120a to 120d are formed in a stacked structure of a gate conductive material 13 and a capping layer 14, and the gate conductive material 13 is formed of polysilicon or tungsten. It may be formed of a conductive material.

Hereinafter, referring to FIG. 3 which is a cross-sectional view of FIG. 2 taken along the X-X' axis and FIG. 4 which is a cross-sectional view of FIG. 2 taken along the Y-Y' axis, the program transistor 130 and the select transistors 110 and 120 ) Will be described in detail.

First, referring to FIG. 3, channel lines 103a to 103d are formed in a line type up to the position of the select gate 120a, and a channel region 106a is formed on the other side of the select gate 120a. Accordingly, the channel line 103a and the channel region 106a become drain or source regions and are driven together with the select gate 120a as the select transistor 121. In addition, a stacked structure of a plurality of gate insulating layer lines 105a to 105d and gate lines 107a to 107d spaced apart at a predetermined interval is formed on the line-type channel line 103a.

Meanwhile, referring to FIG. 4, in the program transistor 130, a plurality of channel lines 103a to 103d spaced apart from each other at a predetermined interval are formed in the semiconductor substrate 101, and a channel line in a direction perpendicular to the channel lines 103a to 103d. A gate insulating layer line 105a and a gate line 107a stacked in a line type are formed on the lines 103a to 103d.

In addition, a select transistor is provided that is spaced apart from the gate lines 107a to 107d at a predetermined interval in the long axis direction of the gate lines 107a to 107d. The select transistor includes a gate insulating layer 108a formed on an upper portion between the channel region 102a and the channel region 104a, and a select gate 110a formed on the gate insulating layer 108a.

Meanwhile, as shown in FIG. 1, a metal structure 140 is formed to connect the program transistor 130 and the select transistor 110. As shown in FIG. 2, the metal structure 140 has a channel region ( 104a to 104d) metal contacts 141a to 141d formed on the top, metal contacts 142a to 142d formed on the gate lines 107a to 107d, metal contacts 141a to 141d, and metal contacts 142a to 142d And metal lines 143a to 143d connecting them. That is, the metal structure 140 connects the gate lines 107a to 107d and the select gates 110a to 110d so that they correspond to each other in a one-to-one correspondence.

Referring to the cross-sectional view of FIG. 4, a metal contact (a first metal contact, 142a) is formed on the gate line 107a, and a metal contact (a second metal contact, 141a) is a channel region 104a of the select gate 110a. ) Is formed on the top, and the metal contact 141a and the metal contact 142a are connected by a metal line 143a. Accordingly, the gate line 107a of the program transistor and the channel region 104a of the select transistor are electrically connected through the metal contacts 141a and 142a and the metal line 143a.

As described above, the present invention forms the program transistor 130 having a matrix structure through the gate lines 107a to 107d and channel lines 103a to 103d that cross vertically, and selects one of the matrix structures. Each of the select transistors 110 and 120 is provided at the end of the program transistor 130 (the end of the channel line and the end of the gate line).

Accordingly, the present invention can minimize the area of the anti-fuse array by providing one select transistor corresponding to one gate line connected to a plurality of program transistors and one select transistor corresponding to one channel line. have.

Hereinafter, a method of operating an antifuse array according to an embodiment of the present invention will be described in detail with reference to FIGS. 5 and 6.

First, FIG. 5 is a diagram for explaining a program operation method of an antifuse array according to an embodiment of the present invention.

Referring to FIG. 5(i), first, it is assumed that the select transistors 110 and 120 are in a floating state in which no voltage is applied in the initial state. That is, when all the select transistors 110 and 120 are in a floating state, a desired select transistor is turned on in order to select a program transistor to be programmed (disrupted). In FIG. 5, the select transistors 121 and 123 and the select transistor 112 are turned on and a voltage is applied through the turned on select transistors 121 and 123 and the select transistor 112 to burst the program transistors A and B. An example is disclosed.

That is, when a ground voltage is applied to the select transistors 121 and 123 connected to the channel lines 103a and 103c and a power voltage is applied to the select transistor 112 connected to the gate line 107b, the channel line 103a , 103c and the gate line 107b, a voltage difference occurs in the program transistors A and B at the intersection of the gate insulating film. At this time, the remaining gate lines 107a, 107c, and 107d and the remaining channel lines 105b and 105d are in a floating state, and thus the channel lines 105b and 105d and the gate lines 107a, 107c, and 107d are No rupture occurs in the program transistor at the intersection point.

It is preferable that such a program operation proceeds sequentially in the first direction. Here, the first direction refers to a direction that approaches the select transistor 120 from left to right.

That is, referring to (ii), after the program transistors A and B connected to the gate line 107b are ruptured, the program transistors connected to the gate line 107c are ruptured, and sequentially connected to the gate line 107d. Burst the program transistors.

This is because when the program transistors connected to the gate line 107c are ruptured after the program transistors connected to the gate line 107c are ruptured, a leakage current is generated by the program transistors connected to the gate line 107c which has already been ruptured. This is because a case in which the program transistors connected to 107b cannot be ruptured may occur.

For example, in the case of attempting to rupture the program transistors (A, B) after rupturing the program transistors (C, D) in Fig. 5(ii), a leakage current is generated by the ruptured program transistors (C, D). do. That is, even if voltage is applied to the select transistor 112 and the select transistor 123 to rupture the program transistor B, a leakage current is generated in the already ruptured program transistor D on the right side of the program transistor B. As a result, the voltage difference applied to the program transistor B is weakened, and thus it may be difficult to rupture.

Accordingly, it is preferable that the anti-fuse of the present invention burst the program transistors sequentially in a direction closer to the select transistor 120.

6 is a view for explaining a read operation method of an antifuse array according to an embodiment of the present invention.

Referring to FIG. 6(i), first, it is assumed that the select transistors 110 and 120 are in a floating state in which no voltage is applied in the initial state.

In order to read the program transistor E at the point where the channel line 103b and the gate line 107c intersect as in (i) of FIG. 6, a select transistor 113 connected to the channel line 103b A read voltage VRD is applied to and a ground voltage is applied to the select transistor 122 connected to the gate line 107c. Accordingly, since the program transistor E has already been ruptured, current flows, and a current value flowing through the program transistor E is read. In this case, the current value can be measured using a separate device, and measuring the current value and leading the value to "1" or "0" according to the current value can be applied as a general fuse lead technique.

For example, if the current value is higher than a certain level, it can be assumed that the fuse value is "1" and if the current value is less than a certain level, the fuse value is "0". If the current value is higher than a certain level, the fuse is in a burst state. If the current value is less than a certain level, it can be determined that the fuse is not blown.

In Fig. 6(ii), the program transistor E'is not ruptured. At this time, in order to read the program transistor E', a read voltage VRD is applied to the select transistor 113 connected to the channel line 103b, and the read voltage VRD is applied to the select transistor 122 connected to the gate line 107c. Apply the ground voltage. Accordingly, a current must flow through the program transistor E'due to the voltage difference, but since the program transistor E'is not ruptured, the current does not flow.

Accordingly, when measuring the current flowing through the program transistor E', a current level below a certain level may be measured.

As described above, according to the present invention, programming can be performed by forming a program transistor in a matrix structure and forming a select gate at the end of the program gate line so that only the program gate selected by the select gate at the end is ruptured. Accordingly, compared to a structure in which the program gate and the select gate are made to correspond one-to-one, the area of the anti-fuse array can be minimized by providing one select gate for a plurality of program gates.

The above description is merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains will be able to make various modifications and variations without departing from the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

101: semiconductor substrate
102a ~ 102d: channel area
103a ~ 103d: channel line
104a ~ 104d: channel area
105a to 105d: gate insulating film line
106a ~ 106d: channel area
107a to 107d: gate line
108a to 108d: gate insulating film
109a to 109d: gate insulating film
110, 120: select transistor
130: programmable transistor
140: metal structure
111 ~ 114: select gate
121 to 124: select gate
141a to 141d: metal contact
142a to 142d: metal contact
143a to 143d: metal line

Claims (20)

A plurality of gate lines extending in a first direction, a plurality of channel lines extending in a second direction to cross the plurality of gate lines, and a plurality of channel lines positioned under the gate lines so as to overlap the plurality of channel lines A plurality of first transistors including gate insulating layer lines;
A plurality of second transistors connected to each of the plurality of gate lines; And
An antifuse array including a plurality of third transistors connected to each of the plurality of channel lines. ◈ Claim 2 was abandoned upon payment of the set registration fee. The method according to claim 1,
Wherein the first transistors are program transistors, and the second transistors and the third transistors are select transistors. ◈ Claim 3 was abandoned upon payment of the set registration fee. The method of claim 1, wherein the channel lines
An anti-fuse array formed in a semiconductor substrate and formed at a predetermined interval in the first direction. ◈ Claim 4 was abandoned upon payment of the set registration fee. The method of claim 3,
The channel lines are antifuse array, characterized in that formed through ion implantation. ◈ Claim 5 was abandoned upon payment of the set registration fee. The method of claim 3,
Each of the third transistors,
A first channel region formed in the semiconductor substrate;
A second channel region spaced apart from the first channel region and connected to any one of the channel lines;
A gate insulating layer formed on an upper portion between the first channel region and the second channel region; And
A gate electrode formed on the gate insulating layer;
Anti-fuse array comprising a. ◈ Claim 6 was abandoned upon payment of the set registration fee. The method of claim 3,
And the third transistors are connected to ends of the channel lines in the second direction. ◈ Claim 7 was abandoned upon payment of the set registration fee. The method of claim 3,
Each of the second transistors,
First and second channel regions formed at predetermined intervals in the semiconductor substrate;
A gate insulating layer formed between the first and second channel regions; And
A gate electrode formed on the gate insulating layer
Anti-fuse array comprising a. ◈ Claim 8 was abandoned upon payment of the set registration fee. The method of claim 3,
The second transistors,
Anti-fuse array, characterized in that formed to be spaced apart from ends of the gate lines in the first direction by a predetermined interval. ◈ Claim 9 was abandoned upon payment of the set registration fee. The method of claim 3,
The anti-fuse array, further comprising metal structures connecting the plurality of first transistors and the plurality of second transistors. ◈ Claim 10 was abandoned upon payment of the set registration fee. The method of claim 9,
The metal structures,
First metal contacts connected to the gate lines of the first transistors;
Second metal contacts connected to the channel regions of the second transistors; And
Metal lines connecting the first metal contacts and the second metal contacts
Anti-fuse array comprising a. ◈ Claim 11 was abandoned upon payment of the set registration fee. The method of claim 9,
The metal structures,
Anti-fuse array, characterized in that formed in a one-to-one correspondence with the gate lines. ◈ Claim 12 was abandoned upon payment of the set registration fee. The method of claim 3,
The third transistors are formed to correspond to the channel lines one-to-one. delete ◈ Claim 14 was abandoned upon payment of the set registration fee. The method of claim 5,
The first channel region and the second channel region,
Anti-fuse array, characterized in that formed at the same time through ion implantation when the channel lines are formed. A plurality of first transistors positioned at points where the plurality of gate lines and the plurality of channel lines cross; A plurality of second transistors connected to each of the gate lines; And a plurality of third transistors connected to each of the channel lines, the method comprising:
Applying a first voltage to at least one of the plurality of second transistors;
Applying a second voltage to at least one of the plurality of third transistors;
And rupture of at least one of the plurality of first transistors to which the first voltage and the second voltage are applied,
The step of rupturing the at least one transistor
The method of operating an anti-fuse array, characterized in that sequentially bursting in a direction approaching the third transistors. ◈ Claim 16 was abandoned upon payment of the set registration fee. The method of claim 15,
In a program mode, the first voltage is a power voltage (VDD) level, and the second voltage is a ground voltage (VSS) level. ◈ Claim 17 was abandoned upon payment of the set registration fee. The method of claim 15,
And performing a read operation by applying a third voltage to at least one of the plurality of second transistors and applying a fourth voltage to at least one of the plurality of third transistors. How the fuse array works. ◈ Claim 18 was abandoned upon payment of the set registration fee. The method of claim 17,
In a read mode, the third voltage is a read voltage (VRD) level, and the fourth voltage is a ground voltage (VSS) level. ◈ Claim 19 was abandoned upon payment of the set registration fee. The method of claim 15,
Wherein the first transistors are program transistors, and the second transistors and the third transistors are select transistors. delete

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