CN107624001B - Circuit board electroplating method - Google Patents
Circuit board electroplating method Download PDFInfo
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- CN107624001B CN107624001B CN201710892577.1A CN201710892577A CN107624001B CN 107624001 B CN107624001 B CN 107624001B CN 201710892577 A CN201710892577 A CN 201710892577A CN 107624001 B CN107624001 B CN 107624001B
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- thickness
- electroplating
- hard gold
- target value
- circuit board
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electroplating Methods And Accessories (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention relates to a circuit board electroplating method, which comprises the following steps: s10: providing a circuit board having a DUT region and a TC bit; s20: setting a target value K of the thickness of the hard gold; s30: performing primary electroplating on the circuit board according to the target value K of the thickness of the hard gold; s40: measuring the thickness of the hard gold of the DUT region and the TC bit, and if the thickness of the hard gold of the DUT region is greater than the target value K and the thickness of the hard gold of the TC bit is less than the target value K, executing step S50; s50: providing an electroplating-resistant protective layer on the DUT region; s60: carrying out secondary electroplating on the circuit board according to the target value K of the thickness of the hard gold; s70: and measuring the thickness of the hard gold at the TC position, and executing the subsequent production steps if the thickness of the hard gold at the TC position is greater than the target value K. The electroplating method of the circuit board can avoid gold infiltration in a DUT area, ensure enough thickness of hard gold at TC position and has good electroplating effect.
Description
Technical Field
The invention relates to the technical field of circuit board production, in particular to a circuit board electroplating method.
Background
In the process of producing the circuit board, customers have certain requirements on the thickness of the electroplated hard gold. Under the influence of the distribution of power lines, the current of an isolated DUT (semiconductor device) area on a circuit board is concentrated, so that the hard gold thickness of the DUT area is too large, and the adverse phenomenon of gold infiltration is easy to occur. The thickness of the hard gold of the TC (transistor cell) bit is easily insufficient, and the production requirements cannot be met.
Disclosure of Invention
Based on this, the present invention overcomes the defects of the prior art and provides a method for electroplating a circuit board, which on one hand avoids the occurrence of gold infiltration in the DUT region and on the other hand ensures sufficient thickness of hard gold at the TC site.
A circuit board electroplating method comprises the following steps:
s10: providing a circuit board having a DUT region and a TC bit;
s20: setting a target value K of the thickness of the hard gold;
s30: performing primary electroplating on the circuit board according to the target value K of the thickness of the hard gold;
s40: measuring the thickness of the hard gold of the DUT region and the TC bit, and if the thickness of the hard gold of the DUT region is greater than the target value K and the thickness of the hard gold of the TC bit is less than the target value K, executing step S50;
s50: providing an electroplating-resistant protective layer on the DUT region;
s60: carrying out secondary electroplating on the circuit board according to the target value K of the thickness of the hard gold;
s70: and measuring the thickness of the hard gold at the TC position, and executing the subsequent production steps if the thickness of the hard gold at the TC position is greater than the target value K.
The electroplating method of the circuit board comprises the steps of firstly electroplating the circuit board for the first time to enable the thickness of the hard gold of the DUT area to meet the production requirement, then arranging the electroplating-proof protective layer on the DUT area to avoid electroplating again, and finally electroplating the circuit board for the second time to enable the thickness of the hard gold of the TC position to meet the production requirement. Therefore, the method can avoid gold infiltration in a DUT region, ensure enough thickness of hard gold at TC position and has good electroplating effect.
Further, in step S40, if the thickness of the hard gold of the DUT region is smaller than the target value K and the thickness of the hard gold of the TC bit is smaller than the target value K, step S30 is executed again.
The first electroplating can be carried out for multiple times, and the circuit board is electroplated for the first time until the thickness of the hard gold in the DUT area meets the production requirement, so that the electroplating quality is ensured.
Further, in step S40, if the thickness of the hard gold of the DUT region is greater than the target value K and the thickness of the hard gold of the TC bit is greater than the target value K, the following steps are performed.
After the circuit board is electroplated for the first time, if the thicknesses of the hard gold of the DUT area and the TC position meet the production requirements, the subsequent production steps are executed, the electroplating for the second time is not carried out, and the electroplating is avoided.
Further, between step S20 and step S30, the following steps are also included:
s21: the area of the DUT region S1 and the area of the TC bit S2 are measured, and if the ratio of S2 to S1 is smaller than the predetermined value, the subsequent production steps are performed after step S30 is performed.
When the area of the DUT region is smaller than that of the TC site, the electroplating is completed by performing the first electroplating without performing the second electroplating, thereby improving the electroplating efficiency.
Further, the preset value is 25-35. If the preset value is too large, the circuit board with larger area of some DUT areas and TC positions is not electroplated for the second time, gold infiltration is easy to occur in the DUT areas, and the thickness of hard gold at the TC positions is easy to be insufficient; if the preset value is too small, the circuit board with smaller area of some DUT area and TC bit needs to be electroplated for the second time, and the electroplating efficiency is lower.
Further, the preset value is 30. The preset value is 30, which is an optimal value, if the ratio of S2 to S1 is more than 30, the second electroplating is carried out to finish the electroplating; and if the ratio of S2 to S1 is less than 30, the first electroplating is carried out to finish the electroplating, and the second electroplating is not carried out.
Further, in step S70, if the thickness of the hard gold at the TC bit is smaller than the target value K, step S60 is executed again.
The second electroplating can be repeated, and the circuit board is electroplated for the second time until the thickness of the hard gold at the TC position meets the production requirement, so that the electroplating quality is ensured.
Further, step S30 specifically includes the following steps:
and calculating a first electroplating parameter according to the target value K of the thickness of the hard gold, and electroplating the circuit board for the first time by using the first electroplating parameter.
Therefore, the thickness of the hard gold in the DUT area meets the production requirement by primary electroplating as much as possible, and the electroplating efficiency is improved.
Further, step S60 specifically includes the following steps:
and calculating a second electroplating parameter by combining the hard gold thickness at the TC position according to the hard gold thickness target value K, and carrying out secondary electroplating on the circuit board by using the second electroplating parameter.
Therefore, the thickness of the hard gold at the TC position meets the production requirement through primary electroplating for the second time as far as possible, and the electroplating efficiency is improved.
Furthermore, the anti-electroplating protective layer is peelable blue glue, and has good anti-electroplating effect and strong toughness.
Drawings
Fig. 1 is a schematic flow chart of a circuit board electroplating method according to an embodiment of the invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, the method for electroplating a circuit board according to the present embodiment includes the following steps:
s10: a circuit board is provided having a DUT region and a TC bit.
S20: setting a target value K of the thickness of the hard gold.
The target value K for the thickness of the hard gold should be set on the basis of the customer's request.
S21: the area of the DUT region S1 and the area of the TC bit S2 are measured, and if the ratio of S2 to S1 is smaller than the predetermined value, the subsequent production steps are performed after step S30 is performed.
When the area of the DUT region is smaller than that of the TC site, the electroplating is completed by performing the first electroplating without performing the second electroplating, thereby improving the electroplating efficiency.
Preferably, the preset value is 25-35. If the preset value is too large, the circuit board with larger area of some DUT areas and TC positions is not electroplated for the second time, gold infiltration is easy to occur in the DUT areas, and the thickness of hard gold at the TC positions is easy to be insufficient; if the preset value is too small, the circuit board with smaller area of some DUT area and TC bit needs to be electroplated for the second time, and the electroplating efficiency is lower.
In the present embodiment, the preset value is 30. The preset value is 30, which is an optimal value, if the ratio of S2 to S1 is more than 30, the second electroplating is carried out to finish the electroplating; and if the ratio of S2 to S1 is less than 30, the first electroplating is carried out to finish the electroplating, and the second electroplating is not carried out.
S30: and carrying out primary electroplating on the circuit board according to the target value K of the thickness of the hard gold.
Specifically, step S30 includes the steps of:
and calculating a first electroplating parameter according to the target value K of the thickness of the hard gold, and electroplating the circuit board for the first time by using the first electroplating parameter.
Therefore, the thickness of the hard gold in the DUT area meets the production requirement by primary electroplating as much as possible, and the electroplating efficiency is improved.
S40: and measuring the thickness of the hard gold of the DUT region and the TC bit, and if the thickness of the hard gold of the DUT region is greater than the target value K and the thickness of the hard gold of the TC bit is less than the target value K, executing step S50.
In step S40, if the thickness of the hard gold in the DUT region is smaller than the target value K and the thickness of the hard gold in the TC bit is smaller than the target value K, step S30 is executed again.
The first electroplating can be carried out for multiple times, and the circuit board is electroplated for the first time until the thickness of the hard gold in the DUT area meets the production requirement, so that the electroplating quality is ensured.
In step S40, if the thickness of the hard gold in the DUT region is greater than the target value K and the thickness of the hard gold in the TC bit is greater than the target value K, the following steps are performed.
After the circuit board is electroplated for the first time, if the thicknesses of the hard gold of the DUT area and the TC position meet the production requirements, the subsequent production steps are executed, the electroplating for the second time is not carried out, and the electroplating is avoided.
S50: an anti-plating protective layer is disposed over the DUT region.
The electroplating-resistant protective layer is peelable blue glue, and is good in electroplating-resistant effect and strong in toughness.
S60: and carrying out secondary electroplating on the circuit board according to the target value K of the thickness of the hard gold.
Specifically, step S60 includes the steps of:
and calculating a second electroplating parameter by combining the hard gold thickness at the TC position according to the hard gold thickness target value K, and carrying out secondary electroplating on the circuit board by using the second electroplating parameter.
Therefore, the thickness of the hard gold at the TC position meets the production requirement through primary electroplating for the second time as far as possible, and the electroplating efficiency is improved.
S70: and measuring the thickness of the hard gold at the TC position, and executing the subsequent production steps if the thickness of the hard gold at the TC position is greater than the target value K.
In step S70, if the thickness of the hard gold at the TC bit is smaller than the target value K, step S60 is executed again.
The second electroplating can be repeated, and the circuit board is electroplated for the second time until the thickness of the hard gold at the TC position meets the production requirement, so that the electroplating quality is ensured.
The electroplating method of the circuit board comprises the steps of firstly electroplating the circuit board for the first time to enable the thickness of the hard gold of the DUT area to meet the production requirement, then arranging the electroplating-proof protective layer on the DUT area to avoid electroplating again, and finally electroplating the circuit board for the second time to enable the thickness of the hard gold of the TC position to meet the production requirement. Therefore, the method can avoid gold infiltration in a DUT region, ensure enough thickness of hard gold at TC position and has good electroplating effect.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A circuit board electroplating method is characterized by comprising the following steps:
s10: providing a circuit board having a semiconductor device DUT region and a transistor cell TC bit;
s20: setting a target value K of the thickness of the hard gold;
s30: performing primary electroplating on the circuit board according to the target value K of the thickness of the hard gold;
s40: measuring the thickness of the hard gold of the DUT area and the TC bit, measuring the area S1 of the DUT area and the area S2 of the TC bit, and executing step S50 if the thickness of the hard gold of the DUT area is greater than a target value K, the thickness of the hard gold of the TC bit is less than the target value K, and the ratio of S2 to S1 is greater than a preset value;
s50: providing an electroplating-resistant protective layer on the DUT region;
s60: carrying out secondary electroplating on the circuit board according to the target value K of the thickness of the hard gold;
s70: and measuring the thickness of the hard gold at the TC position, and executing the subsequent production steps if the thickness of the hard gold at the TC position is greater than the target value K.
2. The method of claim 1, wherein in step S40, if the thickness of the hard gold at the DUT area is smaller than the target value K and the thickness of the hard gold at the TC bit is smaller than the target value K, the step S30 is executed again.
3. The method of claim 1, wherein in step S40, if the thickness of the hard gold at the DUT area is greater than the target value K and the thickness of the hard gold at the TC bit is greater than the target value K, the subsequent production step in step S70 is performed.
4. The circuit board plating method according to claim 1, further comprising, between step S20 and step S30, the steps of:
s21: the area S1 of the DUT region and the area S2 of the TC bit are measured, and if the ratio of S2 to S1 is smaller than the preset value, the subsequent production step in step S70 is performed after step S30 is performed.
5. The method of claim 4, wherein the predetermined value is 25-35.
6. The circuit board electroplating method according to claim 5, wherein the preset value is 30.
7. The method of claim 1, wherein in step S70, if the thickness of the hard gold at TC is less than the target value K, the step S60 is executed again.
8. The circuit board electroplating method according to claim 1, wherein the step S30 specifically comprises the steps of:
and calculating a first electroplating parameter according to the target value K of the thickness of the hard gold, and electroplating the circuit board for the first time by using the first electroplating parameter.
9. The method as claimed in claim 8, wherein step S60 comprises the following steps:
and calculating a second electroplating parameter by combining the hard gold thickness at the TC position according to the hard gold thickness target value K, and carrying out secondary electroplating on the circuit board by using the second electroplating parameter.
10. The method of claim 1, wherein the plating resist layer is a peelable blue glue.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710892577.1A CN107624001B (en) | 2017-09-27 | 2017-09-27 | Circuit board electroplating method |
| PCT/CN2017/120109 WO2019061920A1 (en) | 2017-09-27 | 2017-12-29 | Circuit board electroplating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710892577.1A CN107624001B (en) | 2017-09-27 | 2017-09-27 | Circuit board electroplating method |
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| Publication Number | Publication Date |
|---|---|
| CN107624001A CN107624001A (en) | 2018-01-23 |
| CN107624001B true CN107624001B (en) | 2020-05-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710892577.1A Active CN107624001B (en) | 2017-09-27 | 2017-09-27 | Circuit board electroplating method |
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| Country | Link |
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| CN (1) | CN107624001B (en) |
| WO (1) | WO2019061920A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108650801B (en) * | 2018-04-02 | 2020-07-10 | 皆利士多层线路版(中山)有限公司 | Gold immersion method of thick copper circuit board |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101699940A (en) * | 2009-11-10 | 2010-04-28 | 广州兴森快捷电路科技有限公司 | Manufacture method of golden finger printed board |
| CN103237416A (en) * | 2013-05-08 | 2013-08-07 | 无锡江南计算技术研究所 | Pattern fabrication method capable of realizing hard gold electroplating and soft gold electroplating on same surface |
| CN104411099A (en) * | 2014-12-04 | 2015-03-11 | 奥士康科技（益阳）有限公司 | Transfer method for circuitous pattern of heavy copper printed circuit board |
| CN105142351A (en) * | 2015-08-04 | 2015-12-09 | 深圳市景旺电子股份有限公司 | Leadless local gold electroplating method |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7837851B2 (en) * | 2005-05-25 | 2010-11-23 | Applied Materials, Inc. | In-situ profile measurement in an electroplating process |
| KR20140035701A (en) * | 2012-09-14 | 2014-03-24 | 삼성전기주식회사 | Method fo forming au thin-film and printed circuit board |
| JP2015029027A (en) * | 2013-07-31 | 2015-02-12 | イビデン株式会社 | Printed wiring board |
| CN104562122B (en) * | 2014-12-26 | 2016-12-07 | 惠州市特创电子科技有限公司 | The delay compensation method of electro-coppering thickness and system |
| CN105764257A (en) * | 2015-04-17 | 2016-07-13 | 东莞生益电子有限公司 | PCB flatness control method |
| CN106535504A (en) * | 2016-11-18 | 2017-03-22 | 江门崇达电路技术有限公司 | Manufacturing technology of whole-plate nickel and gold plating half-slotted hole |
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2017
- 2017-09-27 CN CN201710892577.1A patent/CN107624001B/en active Active
- 2017-12-29 WO PCT/CN2017/120109 patent/WO2019061920A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101699940A (en) * | 2009-11-10 | 2010-04-28 | 广州兴森快捷电路科技有限公司 | Manufacture method of golden finger printed board |
| CN103237416A (en) * | 2013-05-08 | 2013-08-07 | 无锡江南计算技术研究所 | Pattern fabrication method capable of realizing hard gold electroplating and soft gold electroplating on same surface |
| CN104411099A (en) * | 2014-12-04 | 2015-03-11 | 奥士康科技（益阳）有限公司 | Transfer method for circuitous pattern of heavy copper printed circuit board |
| CN105142351A (en) * | 2015-08-04 | 2015-12-09 | 深圳市景旺电子股份有限公司 | Leadless local gold electroplating method |
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| Publication number | Publication date |
|---|---|
| CN107624001A (en) | 2018-01-23 |
| WO2019061920A1 (en) | 2019-04-04 |
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