CN107611180A - A kind of vertical channel structure electric double layer thin film transistor (TFT) and preparation method thereof - Google Patents
A kind of vertical channel structure electric double layer thin film transistor (TFT) and preparation method thereof Download PDFInfo
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- CN107611180A CN107611180A CN201710581052.6A CN201710581052A CN107611180A CN 107611180 A CN107611180 A CN 107611180A CN 201710581052 A CN201710581052 A CN 201710581052A CN 107611180 A CN107611180 A CN 107611180A
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Abstract
The invention discloses electric double layer thin film transistor (TFT) of a kind of vertical channel structure and preparation method thereof.The thin film transistor (TFT) includes substrate, gate electrode layer, electrolyte gate dielectric layer, source electrode layer, semiconductor channel layer, drain electrode successively from bottom to top, and source electrode layer is arranged at the top of electrolyte gate dielectric layer；Semiconductor channel layer is arranged at the top of source electrode layer；Drain electrode is arranged at the top of semiconductor channel layer；Source electrode layer is ultra-thin porous structural conductive film；Electrolyte gate dielectric layer uses the electrolyte with electric double layer effect.The thin film transistor (TFT) of the present invention effectively reduces channel length, so as to improve drain current, reduces operating voltage by using vertical channel structure.The present invention can effectively the driving force of enhanced film transistor, reduce power consumption, and there is the advantages such as technique is simple, cost is cheap, is easily integrated, be advantageous to be applied in the Low Power Electronic System such as flexibility, portable, portable, wearable and TFT integrated sensors field.
Description
Technical field
The invention belongs to technical field of semiconductors, the electric double layer thin film transistor (TFT) of more particularly to a kind of vertical channel structure and
Its preparation method.
Background technology
In recent years, thin film transistor (TFT) (TFT) is in random access memory (RAM), too flat panel imaging, integrated sensor, spy
It is not it is widely paid close attention to and is studied as AMLCD and AMOLED application in display field.For many years, for TFT
Active layer semi-conducting material experienced by silicon substrate to oxide, or even the transformation to organic matter, all kinds of TFT performance also obtain
Constantly improve.
In recent years, using zinc oxide be representative oxide TFT because its have relatively high mobility, transparency high and low temperature
The many advantages such as technique, most promise to be silicon substrate TFT widely used at present optimal replacer.Many for TFT should
With, in order to reach higher integrated level, bigger current density, traditional means mainly by reduce TFT channel length come
Realize, and the TFT of vertical channel structure can be realized easily because its channel length is determined by the thickness of its semiconductor channel layer
Ultrashort channel length, and will not the channel length as horizontal channel TFT limited by photoetching process.But common is vertical
The TFT of channel structure mostly uses side grid structure, it is necessary to repeatedly photoetching and mask, complex process, industrialization cost of implementation compared with
Height, it is unfavorable for its extensive use in low-end electronic system.In addition, traditional TFT device generally use insulated by oxide films
As gate dielectric layer, driving voltage is relatively higher, and device power consumption is larger, so as to limit it in flexibility, portable, portable etc.
The application potential of field of electronic systems.
The content of the invention
In order to overcome the disadvantages mentioned above of prior art and deficiency, it is an object of the invention to provide a kind of simple in construction, surpass
The vertical channel structure thin film transistor (TFT) of low driving voltage.The advantage of the device includes：First, the device uses ionic electrolytes
As gate dielectric layer, ultra-thin electric double layer effect is formed using electrolyte gate medium and active layer interface, equivalent grid is greatly improved and is situated between
Matter electric capacity, so as to which the operating voltage of device be greatly lowered；Second, the device uses vertical channel structure, and channel length is by ditch
The thickness of channel layer is determined, is not limited by photoetching process, especially device enter deep-submicron after, vertical channel structure it is excellent
Gesture embodies obvious all the more；3rd, the device architecture is simple, low manufacture cost, is easily integrated and industrialization.
Another object of the present invention is to the preparation method for the electric double layer thin film transistor (TFT) for providing above-mentioned vertical channel structure.
The purpose of the present invention is achieved through the following technical solutions.
A kind of electric double layer thin film transistor (TFT) of vertical channel structure, it includes substrate, gate electrode layer, electricity successively from bottom to top
Matter gate dielectric layer, source electrode layer, semiconductor channel layer, drain electrode are solved, the gate electrode layer is arranged at the substrate；It is described
Electrolyte gate dielectric layer is arranged on gate electrode layer；The source electrode layer is arranged on electrolyte gate dielectric layer；It is described
Semiconductor channel layer is arranged at the top of source electrode layer；The drain electrode is arranged on semiconductor channel layer.
Further, the electrolyte gate dielectric layer part covering grid electrode layer；Electrolysis is completely covered in the source electrode layer
Matter gate dielectric layer；The semiconductor channel layer segment covers source electrode layer；Semiconductor channel layer is completely covered in the drain electrode layer.
Further, the thickness of the electrolyte gate dielectric layer is 1~5 micron, and the electrolyte gate dielectric layer is energy shape
Into the inorganic insulation deielectric-coating (such as column silica) or polyion organic bath (such as polyvinylamine, ox of electric double layer effect
One kind in seralbumin, chitosan), but not limited to this.
Further, the thickness of the semiconductor channel layer is 30~60 nanometers, the semiconductor channel layer to be inorganic or
Organic semiconductor thin-film.
Further, the material of the gate electrode layer, source electrode layer and drain electrode is Al, Cu, Ag, Au or ITO conductive thin
One kind in film.
Further, the thickness of the gate electrode layer is 80~100 nanometers；The source electrode layer thickness is less than 20 nanometers,
And there is loose structure；The drain electrode layer thickness is 100~200 nanometers.
Further, the substrate is glass substrate or plastic supporting base.
The preparation method of the electric double layer thin film transistor (TFT) of described vertical channel structure, comprises the following steps：
(1) conductive film is deposited on substrate as gate electrode layer；The thickness of the gate electrode layer is 80~100 nanometers；
(2) deposition has the electrolyte of electric double layer effect as gate dielectric layer, the electrolyte on gate electrode layer
Gate dielectric layer part covering grid electrode layer, the electrolyte gate medium are organic for the inorganic insulating material or polyion of ion doping
Electrolyte；
(3) one layer of ultra-thin porous structural conductive film is deposited on gate dielectric layer as source electrode layer；The source electrode layer portion
Divide covering gate dielectric layer, the thickness of the source electrode layer is less than 20 nanometers；
(4) the deposited semiconductor film on source electrode layer, semiconductor channel layer is formed；The channel layer is inorganic semiconductor
Film or organic semiconductor thin-film；
(5) conductive film is deposited on semiconductor channel layer as drain electrode；The thickness of the drain electrode is 100~200
Nanometer.
Compared with prior art, the present invention has advantages below and beneficial effect：
The present invention, which uses, has mobile ion electrolyte as gate dielectric layer, the shape at gate medium and active layer interface
Into electric double layer effect；Using vertical channel structure, channel length is greatly shortened, increases current density, and structure is relatively simple.
Therefore, compared with the TFT of existing horizontal channel structure, the device has stronger driving force, is easy to 3D and integrates；With it is existing
The TFT of vertical channel structure compare, the threshold voltage of the device is smaller, low in energy consumption, and technique is more simple, is easy to inexpensive production
Industry.
Brief description of the drawings
Fig. 1 a are the device architecture schematic perspective view of the electric double layer thin film transistor (TFT) of the vertical channel structure of the present invention；
Fig. 1 b are the top view of device architecture shown in Fig. 1 a；
Fig. 1 c are the sectional view of device architecture shown in Fig. 1 a；
Fig. 2 a~Fig. 2 e are structural representation corresponding to each step of the preparation method of thin film transistor (TFT) in example.
Embodiment
With reference to specific embodiments and the drawings, the present invention is described in further detail, but the embodiment party of the present invention
Formula not limited to this.
Embodiment 1
Such as Fig. 1 a~Fig. 1 c, the electric double layer thin film transistor (TFT) of the vertical channel structure of the present embodiment uses bottom grating structure, from
Include substrate 1, gate electrode layer 2, electrolyte gate dielectric layer 3, source electrode layer 4, semiconductor channel layer 5, drain electrode on down successively
Layer 6；The electrolyte gate dielectric layer part covers grid layer；Electrolyte gate dielectric layer is completely covered in the source electrode layer；It is described
Semiconductor channel layer segment covers source electrode layer；Semiconductor channel layer is completely covered in the drain electrode.
The substrate of the present embodiment can be glass substrate or plastic supporting base.
The semiconductor channel layer of the present embodiment is 30~60 nanometers and indium-doped sows zinc oxide (IGZO) semiconductive thin film.
The gate dielectric layer of the present embodiment is 1~5 micron thick of electrolyte film layer, with realize ultra-low operating voltage and
Low-power consumption.
The source electrode layer of the present embodiment is 10~20 Nano ultrathin Au films.
The preparation method of the electric double layer thin film transistor (TFT) of the vertical channel structure of the present embodiment, comprises the following steps：
(1) Al for depositing 80~100 nanometer thickness on glass or plastic base using vacuum evaporation or sputtering technology is thin
Film is as gate electrode layer, as shown in Figure 2 a.
(2) 1~5 micron thick is deposited on gate electrode layer using plasma-enhanced chemical vapor deposition (PECVD) technology
Column silicon dioxide film forms electrolyte gate dielectric layer, and electrolyte gate dielectric layer can also select polyvinylamine, bovine serum albumin
In vain, the organic polyelectrolyte such as chitosan film is to realize electric double layer effect so as to reduce operating voltage.The electrolyte grid
Dielectric layer segments covering grid electrode layer, as shown in Figure 2 b.
(3) 10~20 nanometer thickness are deposited on electrolyte gate dielectric layer using spin coating technique, vacuum evaporation or sputtering technology
Au films as source electrode layer, the source electrode layer can all cover electrolyte gate dielectric layer, as shown in Fig. 2 (c).
(4) IGZO films are deposited as semiconductor channel layer, the semiconductor on source electrode layer using magnetron sputtering method
Raceway groove layer segment covers source electrode layer, as shown in Figure 2 d.
(5) the Al films of 100~200 nanometer thickness are deposited on semiconductor channel layer using vacuum evaporation or sputtering technology
As drain electrode layer, the drain electrode layer can all cover semiconductor channel layer, as shown in Figure 2 e.
The present invention, which uses, has mobile ion electrolyte as gate dielectric layer, the shape at gate medium and active layer interface
Into electric double layer effect；Using vertical channel structure, channel length is greatly shortened, increases drain current, reduces operating voltage,
And structure is relatively simple.Therefore, compared with the TFT of existing horizontal channel structure, the device has stronger driving energy
Power, it is easy to 3D and integrates.
Above-described embodiment is the preferable embodiment of the present invention, but embodiments of the present invention are not by the embodiment
Limitation, other any Spirit Essences without departing from the present invention with made under principle change, modification, replacement, combine, simplification,
Equivalent substitute mode is should be, is included within protection scope of the present invention.
Claims (8)
- A kind of 1. electric double layer thin film transistor (TFT) of vertical channel structure, it is characterised in that：Include substrate successively from bottom to top（1）、 Gate electrode layer（2）, electrolyte gate dielectric layer（3）, source electrode layer（4）, semiconductor channel layer（5）, drain electrode（6）, the grid electricity Pole layer（2）It is arranged at the substrate（1）On；The electrolyte gate dielectric layer（3）It is arranged on gate electrode layer；The source Electrode layer（4）It is arranged on electrolyte gate dielectric layer；The semiconductor channel layer（5）It is arranged at the top of source electrode layer；Institute State drain electrode（6）It is arranged on semiconductor channel layer.
- 2. the electric double layer thin film transistor (TFT) of vertical channel structure according to claim 1, it is characterised in that：The electrolyte grid Dielectric layer segments covering grid electrode layer；Electrolyte gate dielectric layer is completely covered in the source electrode layer；The semiconductor channel layer portion Divide covering source electrode layer；Semiconductor channel layer is completely covered in the drain electrode layer.
- 3. the electric double layer thin film transistor (TFT) of vertical channel structure according to claim 1, it is characterised in that：The electrolyte grid The thickness of dielectric layer be 1 ~ 5 micron, the electrolyte gate dielectric layer be can be formed electric double layer effect inorganic insulation deielectric-coating or Polyion organic bath.
- 4. the electric double layer thin film transistor (TFT) of vertical channel structure according to claim 1, it is characterised in that：The semiconductor ditch The thickness of channel layer is 30 ~ 60 nanometers, and the semiconductor channel layer is inorganic or organic semiconductor thin-film.
- 5. the electric double layer thin film transistor (TFT) of vertical channel structure according to claim 1, it is characterised in that：The grid electricity The material of pole layer, source electrode layer and drain electrode is one kind in Al, Cu, Ag, Au or ITO conductive film.
- 6. the electric double layer thin film transistor (TFT) of vertical channel structure according to claim 1, it is characterised in that：The grid electricity The thickness of pole layer is 80 ~ 100 nanometers；The source electrode layer thickness is less than 20 nanometers, and has loose structure；The drain electrode layer Thickness is 100 ~ 200 nanometers.
- 7. the electric double layer thin film transistor (TFT) of vertical channel structure according to claim 1, it is characterised in that：The substrate For glass substrate or plastic supporting base.
- 8. preparing the method for the electric double layer thin film transistor (TFT) of any one of claim 1 ~ 7 vertical channel structure, its feature exists In comprising the following steps：(1) conductive film is deposited on substrate as gate electrode layer；(2) deposition has the electrolyte of electric double layer effect as gate dielectric layer on gate electrode layer；(3) one layer of ultra-thin porous structural conductive film is deposited on gate dielectric layer as source electrode layer；(4) the deposited semiconductor film on source electrode layer, semiconductor channel layer is formed；(5) layer of conductive film is deposited on semiconductor channel layer as drain electrode.
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| CN108414603A (en) * | 2018-01-29 | 2018-08-17 | 江南大学 | A kind of humidity sensor and preparation method thereof based on electric double layer thin film transistor (TFT) |
| WO2020042616A1 (en) * | 2018-08-31 | 2020-03-05 | Boe Technology Group Co., Ltd. | Display panel and fabricating method thereof |
| CN111048664A (en) * | 2019-12-07 | 2020-04-21 | 福州大学 | Organic electrochemical transistor with vertical structure and preparation method thereof |
| CN111048665A (en) * | 2019-12-27 | 2020-04-21 | 福州大学 | Fibrous vertical channel transistor and preparation method thereof |
| CN111463222A (en) * | 2020-04-13 | 2020-07-28 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display device |
| CN113013253A (en) * | 2021-02-24 | 2021-06-22 | 中国科学院宁波材料技术与工程研究所 | P-type thin film transistor, preparation method thereof and phase inverter |
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| CN113013253A (en) * | 2021-02-24 | 2021-06-22 | 中国科学院宁波材料技术与工程研究所 | P-type thin film transistor, preparation method thereof and phase inverter |
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