CN107610735B - Shift temporary storage device - Google Patents
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- CN107610735B CN107610735B CN201710879398.4A CN201710879398A CN107610735B CN 107610735 B CN107610735 B CN 107610735B CN 201710879398 A CN201710879398 A CN 201710879398A CN 107610735 B CN107610735 B CN 107610735B
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Abstract
The invention discloses a shift register, which comprises a plurality of shift register units, wherein each shift register unit comprises a pull-down circuit, a first pull-down control circuit and a second pull-down control circuit. The first pull-down control circuit comprises a first receiving terminal, a second receiving terminal and a first output terminal. The first receiving end is used for receiving the first low-frequency signal. The second pull-down control circuit comprises a third receiving end, a fourth receiving end and a second output end. The third receiving end is used for receiving the second low-frequency signal. When the first low-frequency signal is at a high level, the second low-frequency signal is at a low level. When the first low-frequency signal is at a low level, the first low-frequency signal is at a high level. The first low-frequency signal and the second low-frequency signal are periodically switched between a high level and a low level.
Description
Technical Field
The present disclosure relates to a shift register, and more particularly, to a shift register capable of reducing bias stress (stress).
Background
Advanced display devices are becoming an important feature of current consumer electronics products, and liquid crystal displays have become widely used as displays with high resolution color screens for various electronic devices such as mobile phones, Personal Digital Assistants (PDAs), digital cameras, computer screens, or notebook computer screens.
The liquid crystal display includes a gate driver and a source driver. In the current lcd panel design, the gate driver is equivalently a shift register (shift register) for outputting scan signals to the lcd panel at regular intervals. The shift register comprises a plurality of shift register units, and each shift register unit delays and outputs an input signal into an output signal according to a clock signal. The next stage of shift register unit takes the output signal of the previous stage of shift register unit as the input signal, and delays and outputs the input signal to become the output signal of the next stage of shift register unit. However, the gate voltage of the transistor of the shift register unit remains at the high voltage for a long time after the delay output, and does not return to the low voltage level until the next scan cycle, which may cause the threshold voltage of the transistor to shift (shift). In addition, when the transistor is biased positively or negatively, the longer the bias time, the greater the influence on the shift of the threshold voltage of the transistor, which affects the effective operation of the transistor and the lifetime of the transistor. Finally, the lifetime of the shift register is even shortened.
Therefore, how to improve the bias stress (stress) of the transistors of the shift register is one of the problems to be improved in the art.
Disclosure of Invention
One aspect of the present invention provides a shift register. The shift register comprises a plurality of shift register units which are connected in series, and each shift register unit comprises a pull-down circuit, a first pull-down control circuit and a second pull-down control circuit. The first pull-down control circuit is electrically coupled to the pull-down circuit, and the first pull-down control circuit includes a first receiving terminal, a second receiving terminal and a first output terminal. The first receiving end is used for receiving the first low-frequency signal. The second receiving end is used for receiving the first clock signal. The first output end is electrically coupled to the pull-down circuit. The second pull-down control circuit is electrically coupled to the pull-down circuit. The second pull-down control circuit comprises a third receiving end, a fourth receiving end and a second output end. The third receiving end is used for receiving the second low-frequency signal. The fourth receiving end is used for receiving the first clock signal. The second output end is electrically coupled to the first output end. When the first low-frequency signal is at a high level, the second low-frequency signal is at a low level. When the first low-frequency signal is at a low level, the first low-frequency signal is at a high level. The first low-frequency signal and the second low-frequency signal are periodically switched between a high level and a low level.
One aspect of the present invention provides a shift register. The shift register comprises a plurality of shift register units, and the plurality of shift register units are sequentially connected in series to form a plurality of stages of shift register units. The plurality of shift register units of each stage respectively receive a first clock signal, a second clock signal, a first low-frequency signal, a second low-frequency signal and a low reference potential, and output a gate driving signal and a pull-down driving signal. The plurality of shift register units of each stage further include a pull-up circuit, a pull-down circuit, a first pull-down control circuit and a second pull-down control circuit. The pull-up circuit is provided with a first output end and a second output end, and respectively outputs a grid driving signal and a pull-down driving signal correspondingly, and the pull-up circuit is used for receiving a second clock pulse signal. The pull-down circuit is electrically coupled to the first output end and the second output end of the pull-up circuit and receives the low reference potential. The first pull-down control circuit is electrically coupled to the pull-down circuit and receives a first low-frequency signal and a first clock signal. The second pull-down control circuit is electrically coupled to the pull-down circuit and receives a second low-frequency signal and a first clock signal. The first low-frequency signal and the second low-frequency signal are complementary potentials, and the period of the first low-frequency signal and the period of the second low-frequency signal are both larger than the period of the first clock signal.
Therefore, according to the technical aspect of the present invention, embodiments of the present invention effectively improve the problem of bias stress of the transistors of the shift register by providing a shift register.
Drawings
In order to make the aforementioned and other objects, features, advantages and embodiments of the invention more comprehensible, the following description is given:
fig. 1 is a schematic diagram of a shift register according to some embodiments of the disclosure;
fig. 2 is a schematic diagram of a shift register unit according to some embodiments of the disclosure;
FIG. 3 is a waveform diagram of a signal wave according to some embodiments of the disclosure; and
fig. 4 is a schematic diagram of another shift register unit according to some embodiments of the disclosure.
Wherein, the reference numbers:
100: shift temporary storage device
100_1 to 100_ N: shift temporary storage unit
200A, 200B: shift temporary storage unit
210: pull-down circuit
220A, 220B: first pull-down control circuit
230A, 230B: second pull-down control circuit
240: pull-up circuit
250: pull-up control circuit
T1, T2, T7, T8, T9, T10: transistor with a metal gate electrode
T3, T4, T5, T6, T11, T12: transistor with a metal gate electrode
T13, T14, T15, T16, T17: transistor with a metal gate electrode
C1: capacitor with a capacitor element
R1, R2, R3, R4: receiving end
O1, O2: output end
VSS: low reference potential
ST (n), ST (n-2): pull-down driving signal
G (n), G (n-2), G (n + 4): gate drive signal
P (n): pull down signal
Q (n): pull-up control signal
LC1, LC 2: low frequency signal
HC1, HC 2: clock signal
300: signal wave
VGH: high level
VGL: low level of electricity
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Elements and configurations in the specific illustrations are used in the following discussion to simplify the present disclosure. Any examples discussed are intended for illustrative purposes only and do not limit the scope or meaning of the invention or its illustrations in any way. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples, which are for purposes of simplicity and clarity, and do not in themselves dictate a relationship between the various embodiments and/or configurations discussed below.
The term (terms) used throughout the specification and claims has the ordinary meaning as commonly understood in the art, in the disclosure herein and in the claims, unless otherwise indicated. Certain terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the present disclosure.
As used herein, to "couple" or "connect" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and "couple" or "connect" may also mean that two or more elements are in operation or act with each other.
It will be understood that the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections. These elements, components, regions, layers and/or regions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. As used herein, the word "and/or" includes any combination of one or more of the associated listed items. Reference to "and/or" in this document refers to any one, all, or any combination of at least one of the listed elements.
Please refer to fig. 1. Fig. 1 is a schematic diagram of a shift register 100 according to some embodiments of the disclosure. As shown in FIG. 1, the shift register 100 includes a plurality of shift register units 100_1 to 100_ N, and the plurality of shift register units 100_1 to 100_ N are connected in series. Each of the shift register units 100_ 1-100 _ N can output gate driving signals G (1) -G (N) and pull-down driving signals ST (1) -ST (N), respectively. The detailed embodiments of the shift register units 100_1 to 100_ N will be described with reference to FIGS. 1 to 3.
Please refer to fig. 2. Fig. 2 is a schematic diagram of a shift register unit 200A according to some embodiments of the disclosure. The shift register unit 200A may be used to represent any one of the shift register units 100_ 1-100 _ N shown in FIG. 1. As shown in fig. 2, the shift register unit 200A includes a pull-down circuit 210, a first pull-down control circuit 220A, and a second pull-down control circuit 230A. The first pull-down control circuit 220A is electrically coupled to the pull-down circuit 210, and the first pull-down control circuit 220A includes a receiving terminal R1, a receiving terminal R2 and an output terminal O1. The receiver R1 is used for receiving the first low frequency signal LC1, the receiver R2 is used for receiving the clock signal HC2, and the output O1 is electrically coupled to the pull-down circuit 210. The second pull-down control circuit 230A is electrically coupled to the pull-down circuit 210, and the second pull-down control circuit 230A includes a receiver R3, a receiver R4, and an output O2. The receiver R3 is used for receiving the second low frequency signal LC2, the receiver R4 is used for receiving the clock signal HC2, and the output O2 is electrically coupled to the output O1 and the pull-down circuit 210.
Please refer to fig. 3. Fig. 3 is a waveform diagram of a signal wave 300 according to some embodiments of the disclosure. As shown in fig. 3, the first low frequency signal LC1 is complementary to the second low frequency signal LC 2. That is, when the first low frequency signal LC1 is at the high level VGH, the second low frequency signal LC2 is at the low level VGL, and when the first low frequency signal LC1 is at the low level VGL, the second low frequency signal LC2 is at the high level VGH. In some embodiments, the periods of the first low frequency signal LC1 and the second low frequency signal LC2 are greater than the periods of the clock signal HC1 and the clock signal HC 2. In some embodiments, the period of the first low frequency signal LC1 and the period of the second low frequency signal LC2 are about 1-3 seconds. In some embodiments, the period of the first low frequency signal LC1 and the period of the second low frequency signal LC2 are about 1-5 seconds. In some embodiments, the period of the clock signals HC1 and HC2 is about 10-200 μ s, but not limited thereto.
Please refer back to fig. 2. As shown in fig. 2, in some embodiments, the first pull-down control circuit 220A includes a transistor T1, and the second pull-down control circuit 230A includes a transistor T2. The transistor T1 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal of the transistor T1 is configured to receive the clock signal HC2, the second terminal of the transistor T1 is configured to output the pull-down signal p (n), and the control terminal of the transistor T1 is configured to receive the first low-frequency signal LC 1. The transistor T2 includes a first terminal, a second terminal, and a control terminal. The first terminal of the transistor T2 is used for receiving the clock signal HC2, the second terminal of the transistor T2 is used for outputting the pull-down signal p (n), and the control terminal of the transistor T2 is used for receiving the second low frequency signal LC 2.
Please refer to fig. 2 and fig. 3. When the first low-frequency signal LC1 is at the high level VGH, i.e. the control terminal is at the high level VGH, the transistor T1 turns on the transistor T1, so that the second terminal is substantially the clock signal HC 2. Meanwhile, during the period when the first low frequency signal LC1 is at the high level VGH, the clock signal HC2 is switched between the high level VGH and the low level VGL periodically. In this case, with the periodic voltage switching of the clock signal HC2, the voltage difference between the control terminal and the second terminal of the transistor T1 exhibits a periodic variation larger than zero potential and substantially zero potential. Thus, the stress behavior of the transistor T1 exhibits a positive bias. Similarly, when the first low-frequency signal LC1 is at the low level VGL, i.e. the control terminal thereof is at the low level VGL, the transistor T1 is in a substantially non-conductive state, and the second terminal thereof is substantially the clock signal HC 2. In this case, with the periodic voltage switching of the clock signal HC2, the voltage difference between the control terminal and the second terminal of the transistor T1 exhibits a periodic variation smaller than zero potential and substantially zero potential. Thus, the stress behavior of the transistor T1 exhibits a negative bias. In view of the above, when the first low-frequency signal LC1 is at the high level VGH, the first pull-down control circuit 220A is activated to make the transistor T1 exhibit a stress of positive bias; when the first low-frequency signal LC1 is at the low level VGL, the first pull-down control circuit 220A is deactivated, so that the transistor T1 exhibits a stress of negative bias. Therefore, the stress of the transistor T1 can be in an alternating condition of positive bias and negative bias, so that the stresses can cancel each other, thereby reducing the shift of the threshold voltage of the transistor.
When the second low-frequency signal LC2 is at the high level VGH, i.e. the control terminal is at the high level VGH, the transistor T2 turns on the transistor T2, so that the second terminal is substantially the clock signal HC 2. Meanwhile, during the period when the second low frequency signal LC2 is at the high level VGH, the clock signal HC2 is switched between the high level VGH and the low level VGL periodically. In this case, with the periodic voltage switching of the clock signal HC2, the voltage difference between the control terminal and the second terminal of the transistor T2 exhibits a periodic variation larger than zero potential and substantially zero potential. Thus, the stress behavior of the transistor T2 exhibits a positive bias. Similarly, when the second low-frequency signal LC2 is at the low level VGL, i.e. the control terminal thereof is at the low level VGL, the transistor T2 is substantially non-conductive, and the second terminal thereof is substantially the clock signal HC 2. In this case, with the periodic voltage switching of the clock signal HC2, the voltage difference between the control terminal and the second terminal of the transistor T2 exhibits a periodic variation smaller than zero potential and substantially zero potential. Thus, the stress behavior of the transistor T2 exhibits a negative bias. In view of the above, when the second low-frequency signal LC2 is at the high level VGH, the second pull-down control circuit 230A is activated to make the transistor T2 exhibit a stress of positive bias; when the second low-frequency signal LC2 is at the low level VGL, the second pull-down control circuit 230A is deactivated, such that the transistor T2 exhibits a negatively biased stress. Therefore, the stress of the transistor T2 can be in an alternating condition of positive bias and negative bias, so that the stresses can cancel each other, thereby reducing the shift of the threshold voltage of the transistor.
Please refer back to fig. 2. In some embodiments, the shift register unit 200A further includes a pull-up circuit 240, a pull-up control circuit 250 and a pull-down circuit 210. The pull-down circuit 210 is electrically coupled to the first pull-down control circuit 220A and the second pull-down control circuit 230A. The pull-up circuit 240 is electrically coupled to the pull-up control circuit 250 and the pull-down circuit 210. The pull-up control circuit 250 is electrically coupled to the pull-up circuit 240 and the pull-down circuit 210.
The pull-up circuit 240 receives the clock signal HC1 and outputs a gate output signal g (n) and a pull-down driving signal st (n) at different output terminals. The pull-up control circuit 250 receives the gate driving signal G (n-2) of the first two stages and the pull-down driving signal ST (n-2) of the first two stages and outputs a pull-up control signal q (n).
In some embodiments, the pull-up control circuit 250 includes a transistor T13. The first terminal of the transistor T13 is used for receiving the gate driving signal G (n-2) of the previous two stages, the second terminal of the transistor T13 is used for outputting the pull-up control signal q (n), and the control terminal of the transistor T13 is used for receiving the pull-down driving signal ST (n-2) of the previous two stages.
In some embodiments, the pull-up circuit 240 includes a capacitor C1, a transistor T14, and a transistor T15. The first terminal of the transistor T14 and the first terminal of the transistor T15 respectively receive the clock signal HC 1. The second terminal of the transistor T15 outputs a gate driving signal g (n), and the second terminal of the transistor T14 outputs a pull-down driving signal st (n). The capacitor C1 has a first terminal coupled to the control terminal of the transistor T14 and the control terminal of the transistor T15, and a second terminal coupled to the second terminal of the transistor T15.
In some embodiments, the pull-down circuit 210 includes a transistor T7, a transistor T8, a transistor T9, and a transistor T10. The control terminal of the transistor T8, the control terminal of the transistor T9, and the control terminal of the transistor T10 are electrically coupled to the first pull-down control circuit 220A and the second pull-down control circuit 230A, respectively. Specifically, the first pull-down control circuit 220A and the second pull-down control circuit 230A can output the pull-down signal p (n), so that the pull-down circuit 210 can receive the pull-down signal p (n). The second terminal of the transistor T9 and the second terminal of the transistor T10 are electrically coupled to each other, for example, the second terminal of the transistor T9 and the second terminal of the transistor T10 can be respectively configured to receive the low reference potential VSS. The first terminals of the transistors T9 and T10 are electrically coupled to the pull-up circuit 240, respectively. The second terminal of the transistor T8 is electrically coupled to the pull-up control circuit 250 and the pull-up circuit 240, respectively. In detail, the first terminal of the transistor T9 is used for receiving the pull-down driving signal st (n), the first terminal of the transistor T10 is coupled to the gate driving signal g (n), and the first terminal of the transistor T8 is used for receiving the pull-up control signal q (n).
In some embodiments, the control terminal of the transistor T7 of the pull-down circuit 210 is configured to receive the pull-up control signal q (n), the first terminal of the transistor T7 is configured to receive the pull-down signal p (n), and the second terminal of the transistor T7 is configured to receive the low reference potential VSS. The pull-up control signal q (n) is outputted from the pull-up control circuit 250, and the pull-down signal p (n) is outputted from the first pull-down control circuit 220A and the second pull-down control circuit 230A.
Please refer to fig. 2 again. In some embodiments, the shift register cell 200A further includes a transistor T16 and a transistor T17. The control terminal of the transistor T16 is used for receiving the pull-down driving signal st (n), the first terminal of the transistor T16 is coupled to the pull-up control circuit 250 or used for receiving the pull-up control signal q (n), and the second terminal of the transistor T16 is used for receiving the low reference potential VSS. The control terminal of the transistor T17 is for receiving the gate driving signal G (n +4) of the next four stages, the first terminal of the transistor T17 is coupled to the pull-up circuit 240, and the second terminal of the transistor T16 is for receiving the low reference voltage VSS.
Please refer to fig. 4. Fig. 4 is a schematic diagram of another shift register unit 200B according to some embodiments of the disclosure. The shift register unit 200B may be used to represent any one of the shift register units 100_ 1-100 _ N shown in FIG. 1. As shown in fig. 4, the shift register unit 200B includes a pull-down circuit 210, a first pull-down control circuit 220B, a second pull-down control circuit 230B, a pull-up circuit 240, and a pull-up control circuit 250. The pull-down circuit 210, the pull-up circuit 240, and the pull-up control circuit 250 of the shift register unit 200B in fig. 4 have the same structures as the pull-down circuit 210, the pull-up circuit 240, and the pull-up control circuit 250 of the shift register unit 200A in fig. 2. And will not be repeated here.
Please refer to fig. 4. In some embodiments, the first pull-down control circuit 220B includes a transistor T3 and a transistor T4. The control terminal of the transistor T3 receives the first low frequency signal LC1 at its second terminal. The first terminal of the transistor T4 receives the clock signal HC2, and the second terminal of the transistor T4 outputs the pull-down signal p (n). The first terminal of the transistor T3 is electrically coupled to the control terminal of the transistor T4. In some embodiments, the second pull-down control circuit 230B includes a transistor T5 and a transistor T6. The control terminal of the transistor T5 receives the second low frequency signal LC2 at its first terminal. The second terminal of the transistor T6 receives the clock signal HC2, and the first terminal of the transistor T6 outputs the pull-down signal p (n). The second terminal of the transistor T5 is electrically coupled to the control terminal of the transistor T6.
In some embodiments, the first pull-down control circuit 220B further includes a transistor T11, and the second pull-down control circuit 230B further includes a transistor T12. In detail, the first terminal of the transistor T11 and the second terminal of the transistor T12 can receive the low reference potential VSS respectively, such that the first terminal of the transistor T11 and the second terminal of the transistor T12 are electrically coupled to each other. The second terminal of the transistor T11 is electrically coupled to the control terminal of the transistor T4 and the first terminal of the transistor T3. The first terminal of the transistor T12 is electrically coupled to the control terminal of the transistor T6 and the second terminal of the transistor T5. The control terminal of the transistor T11 and the control terminal of the transistor T12 may receive the pull-up control signal q (n), respectively.
Please refer to fig. 3 and fig. 4. For the transistor T4, when the first low-frequency signal LC1 is at the high level VGH, i.e., the control terminal of the transistor T3 is at the high level VGH, the transistor T3 is turned on, so that the control terminal of the transistor T4 is at the high level VGH. In this way, the transistor T4 is turned on, and the second terminal of the transistor T4 is substantially the clock signal HC 2. Meanwhile, during the period when the first low frequency signal LC1 is at the high level VGH, the clock signal HC2 is switched between the high level VGH and the low level VGL periodically. In this case, with the periodic voltage switching of the clock signal HC2, the voltage difference between the control terminal and the second terminal of the transistor T4 exhibits a periodic variation larger than zero potential and substantially zero potential. Thus, the stress behavior of the transistor T4 exhibits a positive bias. Similarly, when the first low-frequency signal LC1 is at the low level VGL, i.e. the control terminal thereof is at the low level VGL, the transistor T3 is in a substantially non-conductive state, so that the control terminal of the transistor T4 is at the low level VGL. Thus, the transistor T4 is in a non-conducting state, and the second terminal of the transistor T4 is substantially the clock signal HC 2. In this case, with the periodic voltage switching of the clock signal HC2, the voltage difference between the control terminal and the second terminal of the transistor T4 exhibits a periodic variation smaller than zero potential and substantially zero potential, so that the stress behavior of the transistor T4 exhibits a negative bias. In view of the above, when the first low-frequency signal LC1 is at the high level VGH, the first pull-down control circuit 220B is activated to make the transistor T4 exhibit a stress of positive bias; when the first low-frequency signal LC1 is at the low level VGL, the first pull-down control circuit 220B is deactivated, so that the transistor T4 exhibits a stress of negative bias. Therefore, the stress of the transistor T4 can be in an alternating condition of positive bias and negative bias, so that the stresses can cancel each other, thereby reducing the shift of the threshold voltage of the transistor.
For the transistor T6, when the second low-frequency signal LC2 is at the high level VGH, i.e., the control terminal of the transistor T5 is at the high level VGH, the transistor T5 is turned on, so that the control terminal of the transistor T6 is at the high level VGH. In this way, the transistor T6 is turned on, and the second terminal of the transistor T6 is substantially the clock signal HC 2. Meanwhile, during the period when the second low frequency signal LC2 is at the high level VGH, the clock signal HC2 is switched between the high level VGH and the low level VGL periodically. In this case, with the periodic voltage switching of the clock signal HC2, the voltage difference between the control terminal and the second terminal of the transistor T6 exhibits a periodic variation larger than zero potential and substantially zero potential. Therefore, the stress behavior of the transistor T6 will exhibit a positive bias. Similarly, when the second low-frequency signal LC2 is at the low level VGL, i.e. the control terminal thereof is at the low level VGL, the transistor T5 is in a substantially non-conductive state, so that the control terminal of the transistor T6 is at the low level VGL. Thus, the transistor T6 is in a non-conducting state, and the second terminal of the transistor T6 is substantially the clock signal HC 2. In this case, with the periodic voltage switching of the clock signal HC2, the voltage difference between the control terminal and the second terminal of the transistor T6 exhibits a periodic variation smaller than zero potential and substantially zero potential. Therefore, the stress behavior of the transistor T6 exhibits a negative bias. In view of the above, when the second low-frequency signal LC2 is at the high level VGH, the second pull-down control circuit 230B is activated, so that the transistor T6 is biased positively to exhibit stress; when the second low-frequency signal LC2 is at the low level VGL, the second pull-down control circuit 230B is deactivated, such that the transistor T6 exhibits a negatively biased stress. Therefore, the stress of the transistor T6 can be in an alternating condition of positive bias and negative bias, so that the stresses can cancel each other, thereby reducing the shift of the threshold voltage of the transistor.
As described above, in the shift registers 200A and 200B, the transistors in the pull-down control circuit of the shift register are alternately biased positive and negative by the first low-frequency signal LC1, the second low-frequency signal LC2 and the clock signal HC2, so that the stresses can be cancelled out, and the threshold voltage of the transistors can be reduced.
In view of the foregoing, embodiments of the present invention provide a shift register, so as to effectively improve the problem of improving the bias stress of the transistors of the shift register.
Additionally, the above illustration includes exemplary steps in sequential order, but the steps need not be performed in the order shown. It is within the contemplation of the disclosure that the steps may be performed in a different order. Steps may be added, substituted, changed in order, and/or omitted as appropriate within the spirit and scope of embodiments of the present disclosure.
Although the present disclosure has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be limited only by the terms of the appended claims.
Claims (9)
1. A shift register, comprising:
a plurality of shift register units, the shift register units being connected in series, each of the shift register units comprising:
a pull-down circuit;
a first pull-down control circuit electrically coupled to the pull-down circuit, the first pull-down control circuit comprising:
a first receiving end for receiving a first low frequency signal;
a second receiving end for receiving a first clock signal; and
a first output end electrically coupled to the pull-down circuit; and
a second pull-down control circuit electrically coupled to the pull-down circuit, the second pull-down control circuit comprising:
a third receiving end for receiving a second low frequency signal;
a fourth receiving end for receiving the first clock signal; and
a second output end electrically coupled to the first output end;
when the first low-frequency signal is at a high level, the second low-frequency signal is at a low level; when the first low-frequency signal is at a low level, the first low-frequency signal is at a high level, wherein the first low-frequency signal and the second low-frequency signal are periodically switched between the high level and the low level, a period of the first low-frequency signal is greater than a period of the first clock signal, and the period of the second low-frequency signal is greater than the period of the first clock signal.
2. The shift register of claim 1, wherein the first pull-down control circuit of each of the shift register units comprises a first transistor having a first terminal, a second terminal and a control terminal, the control terminal receives the first low frequency signal, the first terminal receives the first clock signal, and the second terminal outputs a pull-down signal; the second pull-down control circuit comprises a second transistor having a first end, a second end and a control end, wherein the control end receives the second low-frequency signal, the first end receives the first clock signal, and the second end is used for outputting the pull-down signal, wherein the pull-down signal is generated according to the first low-frequency signal and the first clock signal.
3. The shift register of claim 2, wherein the first pull-down control circuit comprises:
a first transistor having a first end, a second end and a control end, wherein the control end and the second end receive the first low frequency signal; and
a second transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal receives the first clock signal, the second terminal outputs the pull-down signal, and the first terminal of the first transistor is electrically coupled to the control terminal of the second transistor.
4. The shift register of claim 3, wherein the second pull-down control circuit comprises:
a third transistor having a first end, a second end and a control end, wherein the control end and the first end receive the second low frequency signal; and
a fourth transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal receives the first clock signal, the first terminal outputs the pull-down signal, and the second terminal of the third transistor is electrically coupled to the control terminal of the fourth transistor.
5. The shift register as claimed in claim 4, wherein in each of the shift register units, the first pull-down control circuit comprises a fifth transistor, the second pull-down control circuit comprises a sixth transistor, the fifth transistor and the sixth transistor respectively have a first terminal, a second terminal and a control terminal, the first terminal of the fifth transistor is electrically coupled to the second terminal of the sixth transistor, the second terminal of the fifth transistor is electrically coupled to the control terminal of the second transistor, the first terminal of the sixth transistor is electrically coupled to the control terminal of the fourth transistor, and the control terminal of the fifth transistor and the control terminal of the sixth transistor respectively receive a pull-up control signal outputted by a pull-up control circuit.
6. The shift register as claimed in claim 1, wherein the shift register units are connected in series to form a multi-stage shift register unit, and the shift register units of each stage can output a gate driving signal and a pull-down driving signal, and each of the shift register units comprises:
the pull-up circuit is electrically coupled with the pull-down circuit and can receive a second clock signal and output a grid output signal and the pull-down driving signal; and
and the pull-up control circuit is electrically coupled to the pull-up circuit and the pull-down circuit and receives the grid driving signals of the first two stages and the pull-down driving signals of the first two stages.
7. The shift register as claimed in claim 6, wherein the pull-down circuit of the shift register units of each stage further comprises a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor respectively have a first terminal, a second terminal and a control terminal, wherein the first terminal of the seventh transistor, the control terminal of the eighth transistor, the control terminal of the ninth transistor and the control terminal of the tenth transistor are respectively electrically coupled to the first pull-down control circuit, the second terminal of the seventh transistor, the second terminal of the ninth transistor and the second terminal of the tenth transistor are electrically coupled to each other, and the first terminal of the ninth transistor and the first terminal of the tenth transistor are respectively electrically coupled to the pull-up circuit, the second terminal of the eighth transistor is electrically coupled to the pull-up control circuit and the pull-up circuit, respectively.
8. The shift register as claimed in claim 6, wherein a period of the first low frequency signal is 1-5 seconds, and the period of the first clock signal is 10-200 μ s.
9. A kind of shift register, characterized by, include a plurality of shift register units, and these shift register units are connected in series each other sequentially and form a multistage shift register unit, wherein these shift register units of each stage receive a first clock pulse signal, a second clock pulse signal, a first low frequency signal, a second low frequency signal and a low reference potential respectively, and output a grid drive signal and a pull-down drive signal, and these shift register units of each stage further include:
a pull-up circuit having a first output terminal and a second output terminal, and outputting the gate driving signal and the pull-down driving signal respectively, wherein the pull-up circuit is used for receiving the second clock signal;
a pull-down circuit electrically coupled to the first output terminal and the second output terminal of the pull-up circuit and receiving the low reference potential;
a first pull-down control circuit electrically coupled to the pull-down circuit and receiving the first low frequency signal and the first clock signal; and
a second pull-down control circuit electrically coupled to the pull-down circuit and receiving the second low frequency signal and the first clock signal;
the first low-frequency signal and the second low-frequency signal are complementary potentials, and a period of the first low-frequency signal and a period of the second low-frequency signal are both greater than a period of the first clock signal.
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|---|---|---|---|
| TW106125329 | 2017-07-27 | ||
| TW106125329A TWI627633B (en) | 2017-07-27 | 2017-07-27 | Shift register |
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| CN107610735A CN107610735A (en) | 2018-01-19 |
| CN107610735B true CN107610735B (en) | 2020-06-23 |
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| CN104036751A (en) * | 2014-05-05 | 2014-09-10 | 友达光电股份有限公司 | Shift register |
| KR20140111433A (en) * | 2013-03-11 | 2014-09-19 | 엘지디스플레이 주식회사 | Gate shift register and display device using the same |
| CN104376874A (en) * | 2014-09-10 | 2015-02-25 | 友达光电股份有限公司 | Shift register |
| CN105528985A (en) * | 2016-02-03 | 2016-04-27 | 京东方科技集团股份有限公司 | Shift register unit, driving method and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7817771B2 (en) * | 2008-12-15 | 2010-10-19 | Au Optronics Corporation | Shift register |
| TWI511459B (en) * | 2012-10-11 | 2015-12-01 | Au Optronics Corp | Gate driving circuit capable of preventing current leakage |
| TWI505245B (en) * | 2012-10-12 | 2015-10-21 | Au Optronics Corp | Shift register |
| KR102343894B1 (en) * | 2015-04-07 | 2021-12-27 | 삼성디스플레이 주식회사 | Display device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140111433A (en) * | 2013-03-11 | 2014-09-19 | 엘지디스플레이 주식회사 | Gate shift register and display device using the same |
| CN104036751A (en) * | 2014-05-05 | 2014-09-10 | 友达光电股份有限公司 | Shift register |
| CN104376874A (en) * | 2014-09-10 | 2015-02-25 | 友达光电股份有限公司 | Shift register |
| CN105528985A (en) * | 2016-02-03 | 2016-04-27 | 京东方科技集团股份有限公司 | Shift register unit, driving method and display device |
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| Publication number | Publication date |
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| CN107610735A (en) | 2018-01-19 |
| TWI627633B (en) | 2018-06-21 |
| TW201911324A (en) | 2019-03-16 |
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