TWI627633B - Shift register - Google Patents

Abstract

A shift register includes a plurality of shift register units, and each shift register unit includes a pull-down circuit, a first pull-down control circuit and a second pull-down control circuit. The first pull-down control circuit includes a first receiving end, a second receiving end, and a first output end. The first receiving end is configured to receive the first low frequency signal. The second pull-down control circuit includes a third receiving end, a fourth receiving end, and a second output end. The third receiving end is configured to receive the second low frequency signal. When the first low frequency signal is at a high level, the second low frequency signal is at a low level. When the first low frequency signal is at a low level, the first low frequency signal is at a high level. The first low frequency signal and the second low frequency signal are periodically converted between a high level and a low level.

Description

Shift register

This case relates to a shift register and, in particular, to a shift register that reduces the bias stress.

Advanced display has become an important feature of today's consumer electronics products. LCD monitors have become widely used in a variety of electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or notebook screens. Color screen display.

The liquid crystal display includes a gate driver and a source driver. In the current liquid crystal display panel design, the gate driver is equivalently a shift register for outputting the scan signal to the liquid crystal display panel at regular intervals. The shift register includes a plurality of shift register units, and each shift register unit delays the input signal as an output signal according to the clock signal. The shift register unit of the next stage uses the output signal of the shift register unit of the previous stage as the input signal, and delays the output to become its own output signal. However, the gate voltage of the transistor of the shift register unit will remain at a high voltage for a long time after the delay output, and will not return to the low voltage level until the next scan cycle, thus causing the transistor to be caused. The threshold voltage shifts. this In addition, when the transistor is in a positive or negative bias voltage, the longer the bias time, the greater the influence on the critical voltage offset of the transistor, which affects the effective operation of the transistor, which affects the service life of the transistor. In the end, it even leads to a shortened service life of the shift register.

Therefore, how to improve the bias stress of the transistor of the shift register is one of the problems to be improved in the art.

One aspect of the case is to provide a shift register. The shift register includes a plurality of shift temporary storage units, and the plurality of shift temporary storage units are connected in series, and each of the plurality of shift temporary storage units respectively includes a pull-down circuit, a first pull-down control circuit and a second pull-down Control circuit. The first pull-down control circuit is electrically coupled to the pull-down circuit, and the first pull-down control circuit includes a first receiving end, a second receiving end, and a first output end. The first receiving end is configured to receive the first low frequency signal. The second receiving end is configured to receive the first clock signal. The first output is electrically coupled to the pull-down circuit. The second pull-down control circuit is electrically coupled to the pull-down circuit. The second pull-down control circuit includes a third receiving end, a fourth receiving end, and a second output end. The third receiving end is configured to receive the second low frequency signal. The fourth receiving end is configured to receive the first clock signal. The second output is electrically coupled to the first output. When the first low frequency signal is at a high level, the second low frequency signal is at a low level. When the first low frequency signal is at a low level, the second low frequency signal is at a high level. The first low frequency signal and the second low frequency signal are periodically converted between a high level and a low level.

One aspect of the case is to provide a shift register. The shift register includes a plurality of shift register units, and the plurality of shift register units are mutually A plurality of shift register units are formed in series. The plurality of shift temporary storage units of each stage respectively receive the first clock signal, the second clock signal, the first low frequency signal, the second low frequency signal and the low reference potential, and output the gate driving signal and the pull-down driving signal. The plurality of shift register units of each stage further includes a pull-up circuit, a pull-down circuit, a first pull-down control circuit and a second pull-down control circuit. The pull-up circuit has a first output end and a second output end, and respectively corresponding to the output gate drive signal and the pull-down drive signal, and the pull-up circuit is configured to receive the second clock signal. The pull-down circuit is electrically coupled to the first output end and the second output end of the pull-up circuit, and is received at a low reference potential. The first pull-down control circuit is electrically coupled to the pull-down circuit and receives the first low frequency signal and the first clock signal. The second pull-down control circuit is electrically coupled to the pull-down circuit and receives the second low frequency signal and the first clock signal. The first low frequency signal and the second low frequency signal are complementary potentials, and the period of the first low frequency signal and the period of the second low frequency signal are both greater than the period of the first clock signal.

Therefore, according to the technical aspect of the present invention, the embodiment of the present invention effectively improves the bias stress of the transistor of the shift register by providing a shift register.

100‧‧‧Shift register

100_1~100_N‧‧‧Shift register unit

200A, 200B‧‧‧ shift register unit

210‧‧‧ Pulldown circuit

220A, 220B‧‧‧ first pull-down control circuit

230A, 230B‧‧‧ second pull-down control circuit

240‧‧‧ Pull-up circuit

250‧‧‧ Pull-up control circuit

T1, T2, T7, T8, T9, T10‧‧‧ transistors

T3, T4, T5, T6, T11, T12‧‧‧ transistors

T13, T14, T15, T16, T17‧‧‧ transistors

C1‧‧‧ capacitor

R1, R2, R3, R4‧‧‧ receiving end

O1, O2‧‧‧ output

VSS‧‧‧low reference potential

ST(n), ST(n-2)‧‧‧ pulldown drive signal

G(n), G(n-2), G(n+4)‧‧‧ gate drive signals

P(n)‧‧‧ pulldown signal

Q(n)‧‧‧ Pull-up control signal

LC1, LC2‧‧‧ low frequency signal

HC1, HC2‧‧‧ clock signals

300‧‧‧Signal wave

VGH‧‧‧ high standard

VGL‧‧‧ low level

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Schematic diagram of FIG. 2 is a shifting diagram according to some embodiments of the present disclosure. FIG. 3 is a waveform diagram of a signal wave according to some embodiments of the present invention; and FIG. 4 is a schematic diagram of another shift register unit according to some embodiments of the present disclosure. .

The following disclosure provides many different embodiments or illustrations for implementing different features of the invention. The elements and configurations of the specific illustrations are used in the following discussion to simplify the disclosure. Any examples discussed are for illustrative purposes only and are not intended to limit the scope and meaning of the invention or its examples. In addition, the present disclosure may repeatedly recite numerical symbols and/or letters in different examples, which are for simplicity and elaboration, and do not specify the relationship between the various embodiments and/or configurations in the following discussion.

The terms used in the entire specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, the content disclosed herein, and the particular content. Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the disclosure.

"Coupling" or "connecting" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, and "coupled" or " Connections may also mean that two or more elements operate or interact with each other.

In this article, use the words first, second, third, etc. It is to be understood that various elements, components, regions, layers and/or blocks are described. However, these elements, components, regions, layers and/or blocks should not be limited by these terms. These terms are only used to identify a single element, component, region, layer, and/or block. Thus, a singular element, component, region, layer and/or block may be referred to as a second element, component, region, layer and/or block, without departing from the spirit of the invention. As used herein, the term "and/or" encompasses any combination of one or more of the listed associated items. "and/or" as used in this document refers to any combination of any, all or at least one of the listed elements.

Please refer to Figure 1. FIG. 1 is a schematic diagram of a shift register 100 according to some embodiments of the present disclosure. As shown in FIG. 1 , the shift register 100 includes a plurality of shift register units 100_1 100 100_N, and the plurality of shift register units 100_1 100 100_N are connected in series. Each of the shift register units 100_1 100 100_N can output gate drive signals G(1) to G(N) and pull-down drive signals ST(1) to ST(N), respectively. The detailed embodiments of the shift register units 100_1 to 100_N will be described below with reference to FIGS. 1 to 3 .

Please refer to Figure 2. FIG. 2 is a schematic diagram of a shift register unit 200A according to some embodiments of the present disclosure. The shift register unit 200A can be used to indicate any one of the shift register units 100_1 100 100_N in FIG. 1 . As shown in FIG. 2, the shift register unit 200A includes a pull-down circuit 210, a first pull-down control circuit 220A, and a second pull-down control circuit 230A. The first pull-down control circuit 220A is electrically coupled to the pull-down circuit 210, and the first pull-down control circuit 220A includes a receiving end R1, a receiving end R2, and an output end O1. The receiving end R1 is configured to receive the first low frequency signal LC1, and the receiving end R2 is used to receive the clock signal HC2, and the output terminal O1 is electrically coupled to the pull-down circuit 210. The second pull-down control circuit 230A is electrically coupled to the pull-down circuit 210, and the second pull-down control circuit 230A includes a receiving end R3, a receiving end R4, and an output end O2. The receiving end R3 is configured to receive the second low frequency signal LC2, the receiving end R4 is configured to receive the clock signal HC2, and the output end O2 is electrically coupled to the output end O1 and the pull-down circuit 210.

Please refer to Figure 3. FIG. 3 is a waveform diagram of a signal wave 300 according to some embodiments of the present disclosure. As shown in FIG. 3, the first low frequency signal LC1 is complementary to the second low frequency signal LC2. That is, when the first low frequency signal LC1 is at the high level VGH, the second low frequency signal LC2 is the low level VGL, and when the first low frequency signal LC1 is at the low level VGL, the second low frequency signal LC2 is at the high level VGH. In some embodiments, the period of the first low frequency signal LC1 and the second low frequency signal LC2 is greater than the period of the clock signal HC1 and the clock signal HC2. In some embodiments, the period of the first low frequency signal LC1 and the second low frequency signal LC2 is about 1 to 3 seconds. In some embodiments, the period of the first low frequency signal LC1 and the second low frequency signal LC2 is about 1 to 5 seconds. In some embodiments, the period of the clock signal HC1 and the clock signal HC2 is about 10 to 200 microseconds, but the present invention is not limited thereto.

Please refer back to Figure 2. As depicted in FIG. 2, in some embodiments, the first pull-down control circuit 220A includes a transistor T1 and the second pull-down control circuit 230A includes a transistor T2. The transistor T1 includes a first end, a second end, and a control end, and the first end of the transistor T1 is for receiving the clock signal HC2, and the second end of the transistor T1 is for outputting the pull-down signal P(n), the transistor The control end of T1 is for receiving the first low frequency signal LC1. Transistor T2 contains the first One end, the second end, and the control end. The first end of the transistor T2 is used to receive the clock signal HC2, the second end of the transistor T2 is used to output the pull-down signal P(n), and the control end of the transistor T2 is used to receive the second low-frequency signal LC2.

Please refer to Figure 2 and Figure 3 together. As seen from the transistor T1, when the first low frequency signal LC1 is at a high level VGH, that is, its control terminal is at a high level VGH, the transistor T1 is in an on state, such that the second terminal is substantially the clock signal HC2. At the same time, when the first low frequency signal LC1 is in the high level VGH, the clock signal HC2 is switched between the plurality of periodic high level VGH and the low level VGL. In this case, as the periodic voltage of the clock signal HC2 switches, the voltage difference between the control terminal and the second terminal of the transistor T1 exhibits a periodic variation greater than zero potential and substantially zero potential. As a result, the stress behavior of the transistor T1 will exhibit a positive bias. Similarly, when the first low frequency signal LC1 is at a low level VGL, that is, its control terminal is a low level VGL, the transistor T1 is substantially in a non-conducting state, and its second end is substantially a clock signal HC2. In this case, as the periodic voltage of the clock signal HC2 switches, the voltage difference between the control terminal and the second terminal of the transistor T1 exhibits a periodic variation of less than zero potential and substantially zero potential. As a result, the stress behavior of the transistor T1 exhibits a negative bias. In combination with the above description, when the first low frequency signal LC1 is at the high level VGH, the first pull-down control circuit 220A operates to make the transistor T1 be a positively biased stress representation; and when the first low frequency signal LC1 is at a low level In the case of VGL, the first pull-down control circuit 220A is not activated, so that the transistor T1 exhibits a stress of a negative bias. Therefore, the stress of the transistor T1 can be alternated between a positive bias and a negative bias, so that the stresses can cancel each other, thereby reducing the deflection of the threshold voltage of the transistor.

As seen from the transistor T2, when the second low frequency signal LC2 is at a high level VGH, that is, its control terminal is at a high level VGH, the transistor T2 is in an on state, such that the second terminal is substantially the clock signal HC2. At the same time, when the second low frequency signal LC2 is in the high level VGH, the clock signal HC2 is switched between the plurality of periodic high level VGH and the low level VGL. In this case, as the periodic voltage of the clock signal HC2 switches, the voltage difference between the control terminal and the second terminal of the transistor T2 exhibits a periodic variation greater than zero potential and substantially zero potential. As a result, the stress behavior of the transistor T2 will exhibit a positive bias. Similarly, when the second low frequency signal LC2 is at a low level VGL, that is, its control terminal is a low level VGL, the transistor T2 is substantially in a non-conducting state, and its second end is substantially a clock signal HC2. In this case, as the periodic voltage of the clock signal HC2 switches, the voltage difference between the control terminal and the second terminal of the transistor T2 exhibits a periodic variation of less than zero potential and substantially zero potential. As a result, the stress behavior of the transistor T2 exhibits a negative bias. Referring to the above description, when the second low frequency signal LC2 is at the high level VGH, the second pull-down control circuit 230A operates to make the transistor T2 be a positive bias stress expression; and when the second low frequency signal LC2 is a low level VGL At this time, the second pull-down control circuit 230A is not actuated, so that the transistor T2 exhibits a stress of a negative bias. Therefore, the stress of the transistor T2 can be alternated between a positive bias and a negative bias, so that the stresses can cancel each other, thereby reducing the deflection of the threshold voltage of the transistor.

Please refer back to Figure 2. In some embodiments, the shift register unit 200A further includes a pull-up circuit 240, a pull-up control circuit 250, and a pull-down circuit 210. The pull-down circuit 210 is electrically coupled to the first pull-down control The path 220A is connected to the second pull-down control circuit 230A. The pull-up circuit 240 is electrically coupled to the pull-up control circuit 250 and the pull-down circuit 210. The pull-up control circuit 250 is electrically coupled to the pull-up circuit 240 and the pull-down circuit 210.

The pull-up circuit 240 receives the clock signal HC1 and outputs a gate output signal G(n) and a pull-down drive signal ST(n) at different output terminals. The pull-up control circuit 250 receives the first two stages of the gate drive signal G(n-2) and the first two stages of the pull-down drive signal ST(n-2) and outputs the pull-up control signal Q(n).

In some embodiments, the pull up control circuit 250 includes a transistor T13. The first end of the transistor T13 is for receiving the first two stages of the gate driving signal G(n-2), and the second end of the transistor T13 is for outputting the pull-up control signal Q(n), the transistor T13 The control terminal is configured to receive the pull-down drive signals ST(n-2) of the first two stages.

In some embodiments, the pull up circuit 240 includes a capacitor C1, a transistor T14, and a transistor T15. The first end of the transistor T14 and the first end of the transistor T15 receive the clock signal HC1, respectively. The second end of the transistor T15 outputs a gate drive signal G(n), and the second end of the transistor T14 outputs a pull-down drive signal ST(n). The first end of the capacitor C1 is coupled to the control end of the transistor T14 and the control end of the transistor T15, and the second end is coupled to the second end of the transistor T15.

In some embodiments, the pull-down circuit 210 includes a transistor T7, a transistor T8, a transistor T9, and a transistor T10. The control terminal of the transistor T8, the control terminal of the transistor T9, and the control terminal of the transistor T10 are electrically coupled to the first pull-down control circuit 220A and the second pull-down control circuit 220B, respectively. Specifically, the first pull-down control circuit 220A and the second pull-down control circuit 220B The pull-down signal P(n) can be output, thereby enabling the pull-down circuit 210 to receive the pull-down signal P(n). The second end of the transistor T9 and the second end of the transistor T10 are electrically coupled to each other. For example, the second end of the transistor T9 and the second end of the transistor T10 can respectively receive the low reference potential VSS. The first end of the transistor T9 and the first end of the transistor T10 are electrically coupled to the pull-up circuit 240, respectively. The second ends of the transistors T8 are electrically coupled to the pull-up control circuit 250 and the pull-up circuit 240, respectively. In detail, the first end of the transistor T9 is configured to receive the pull-down driving signal ST(n), and the first end of the transistor T10 is coupled to the gate driving signal G(n), and the first end of the transistor T8 is used to The pull-up control signal Q(n) is received.

In some embodiments, the control terminal of the transistor T7 of the pull-down circuit 210 is configured to receive the pull-up control signal Q(n), and the first end of the transistor T7 is configured to receive the pull-down signal P(n), the first of the transistor T7 The two terminals are used to receive the low reference potential VSS. The pull-up control signal Q(n) is output by the pull-up control circuit 250, and the pull-down signal P(n) is output by the first pull-down control circuit 220A and the second pull-down control circuit 220B.

Please refer to Figure 2 again. In some embodiments, the shift register unit 200A further includes a transistor T16 and a transistor T17. The control terminal of the transistor T16 is configured to receive the pull-down driving signal ST(n), the first end of the transistor T16 is coupled to the pull-up control circuit 250 or the receiving pull-up control signal Q(n), the transistor T16 The two terminals are used to receive the low reference potential VSS. The control terminal of the transistor T17 is configured to receive the gate drive signal G(n+4) of the last four stages, the first end of the transistor T17 is coupled to the pull-up circuit 240, and the second end of the transistor T16 is configured to receive the low Reference potential VSS.

Please refer to Figure 4. Figure 4 is a view of some embodiments according to the present invention Another schematic diagram of the shift register unit 200B is shown. The shift register unit 200B can be used to indicate any one of the shift register units 100_1 100 100_N in FIG. 1 . As shown in FIG. 4, the shift register unit 200B includes a pull-down circuit 210, a first pull-down control circuit 220B, a second pull-down control circuit 230B, a pull-up circuit 240, and a pull-up control circuit 250. The pull-down circuit 210, the pull-up circuit 240, the pull-up control circuit 250 of the shift register unit 200B in FIG. 4 and the pull-down circuit 210, the pull-up circuit 240, and the pull-up of the shift register unit 200A in FIG. The structure of the control circuit 250 is the same. The description will not be repeated here.

Please refer to Figure 4. In some embodiments, the first pull-down control circuit 220B includes a transistor T3 and a transistor T4. The control terminal of the transistor T3 and the second terminal thereof receive the first low frequency signal LC1. The first end of the transistor T4 receives the clock signal HC2, and the second end of the transistor T4 outputs the pull-down signal P(n). The first end of the transistor T3 is electrically coupled to the control end of the transistor T4. In some embodiments, the second pull-down control circuit 230B includes a transistor T5 and a transistor T6. The control terminal of the transistor T5 receives the second low frequency signal LC2 from its first end. The second end of the transistor T6 receives the clock signal HC2, and the first end of the transistor T6 outputs a pull-down signal P(n). The second end of the transistor T5 is electrically coupled to the control end of the transistor T6.

In some embodiments, the first pull-down control circuit 220B further includes a transistor T11, and the second pull-down control circuit 230B further includes a transistor T12. In detail, the first end of the transistor T11 and the second end of the transistor T12 can respectively receive the low reference potential VSS, so that the first end of the transistor T11 and the second end of the transistor T12 are electrically coupled to each other. The second end of the transistor T11 is electrically coupled At the control end of the transistor T4 and the first end of the transistor T3. The first end of the transistor T12 is electrically coupled to the control end of the transistor T6 and the second end of the transistor T5. The control terminal of the transistor T11 and the control terminal of the transistor T12 can receive the pull-up control signal Q(n), respectively.

Please refer to Figure 3 and Figure 4 together. In the case of the transistor T4, when the first low frequency signal LC1 is at the high level VGH, that is, the control terminal of the transistor T3 is at the high level VGH, the transistor T3 is in an on state, so that the control terminal of the transistor T4 is at the high level VGH. In this way, the transistor T4 is in an on state, and the second end of the transistor T4 is substantially the clock signal HC2. At the same time, when the first low frequency signal LC1 is in the high level VGH, the clock signal HC2 is switched between the plurality of periodic high level VGH and the bottom level VGL. In this case, as the periodic voltage of the clock signal HC2 switches, the voltage difference between the control terminal and the second terminal of the transistor T4 exhibits a periodic variation greater than zero potential and substantially zero potential. As a result, the stress behavior of the transistor T4 will exhibit a positive bias. Similarly, when the first low frequency signal LC1 is at a low level VGL, that is, its control terminal is a low level VGL, the transistor T3 is substantially non-conductive, such that the control terminal of the transistor T4 is at a low level VGL. As a result, the transistor T4 is in a non-conducting state, and the second end of the transistor T4 is substantially a clock signal HC2. In this case, with the periodic voltage switching of the clock signal HC2, the voltage difference between the control terminal and the second terminal of the transistor T4 exhibits a periodic variation of less than zero potential and substantially zero potential, thereby causing the transistor T4 to The stress performance will exhibit a negative bias. Referring to the above description, when the first low frequency signal LC1 is at the high level VGH, the first pull-down control circuit 220B operates to make the transistor T4 be a positively biased stress representation; and when the first low frequency signal When the number LC1 is a low level VGL, the first pull-down control circuit 220B is not activated, so that the transistor T4 is a negative bias stress. Therefore, the stress of the transistor T4 can be alternated between a positive bias and a negative bias, so that the stresses can cancel each other, thereby reducing the deflection of the threshold voltage of the transistor.

In the case of the transistor T6, when the second low frequency signal LC2 is at the high level VGH, that is, the control terminal of the transistor T5 is at the high level VGH, the transistor T5 is in an on state, so that the control terminal of the transistor T6 is at the high level VGH. In this way, the transistor T6 is in an on state, and the second end of the transistor T6 is substantially the clock signal HC2. At the same time, when the second low frequency signal LC2 is in the high level VGH, the clock signal HC2 is switched between the plurality of periodic high level VGH and the bottom level VGL. In this case, as the periodic voltage of the clock signal HC2 switches, the voltage difference between the control terminal and the second terminal of the transistor T6 exhibits a periodic variation greater than zero potential and substantially zero potential. Therefore, the stress behavior of the transistor T6 will exhibit a positive bias. Similarly, when the second low frequency signal LC2 is at a low level VGL, that is, its control terminal is a low level VGL, the transistor T5 is substantially non-conductive, such that the control terminal of the transistor T6 is at a low level VGL. As a result, the transistor T6 is in a non-conducting state, and the second end of the transistor T6 is substantially the clock signal HC2. In this case, as the periodic voltage of the clock signal HC2 switches, the voltage difference between the control terminal and the second terminal of the transistor T6 exhibits a periodic variation of less than zero potential and substantially zero potential. Therefore, the stress behavior of the transistor T6 exhibits a negative bias. Referring to the above description, when the first low frequency signal LC1 is at the high level VGH, the first pull-down control circuit 220B operates to make the transistor T6 be a positive bias stress expression; and when the first low frequency signal LC1 is at a low level VGL, the first pull down control The circuit 220B is not actuated such that the transistor T6 exhibits a stress with a negative bias. Therefore, the stress of the transistor T6 can be alternated between a positive bias and a negative bias, so that the stresses can cancel each other, thereby reducing the deflection of the threshold voltage of the transistor.

As described above, in the shift registers 200A and 200B of the present embodiment, the transistors in the pull-down control circuit of the shift register are made positive through the first low-frequency signal LC1, the second low-frequency signal LC2, and the clock signal HC2. The alternation of the bias voltage and the negative bias voltage allows the stresses to cancel each other, thereby reducing the deflection of the threshold voltage of the transistor.

It can be seen from the above embodiments of the present invention that the embodiment of the present invention effectively improves the problem of improving the bias stress of the transistor of the shift register by providing a shift register.

In addition, the above examples include exemplary steps in sequence, but the steps are not necessarily performed in the order shown. Performing these steps in a different order is within the scope of the present disclosure. Such steps may be added, substituted, altered, and/or omitted as appropriate within the spirit and scope of the embodiments of the present disclosure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and refinements without departing from the spirit and scope of the present case. The scope defined in the patent application is subject to change.

Claims (10)

A shift register includes: a plurality of shift temporary storage units, wherein the shift temporary storage units are connected in series, and each of the shift temporary storage units comprises: a pull-down circuit; and a first pull-down control circuit And the first pull-down control circuit includes: a first receiving end for receiving a first low frequency signal; and a second receiving end for receiving a first clock signal And a first output terminal electrically coupled to the pull-down circuit; and a second pull-down control circuit electrically coupled to the pull-down circuit, the second pull-down control circuit comprising: a third receiving end, configured to: Receiving a second low frequency signal; a fourth receiving end for receiving the first clock signal; and a second output end electrically coupled to the first output end; wherein when the first low frequency signal is high On time, the second low frequency signal is at a low level; when the first low frequency signal is at a low level, the second low frequency signal is at a high level, wherein the first low frequency signal and the second low frequency signal are periodically at a high level and a low level Conversion between the quasi-intermediaries. The shift register of claim 1, wherein one of the first low frequency signals has a period greater than one of the first clock signals, and the one The period of the second low frequency signal is greater than the period of the first clock signal. The shift register of claim 1, wherein the first pull-down control circuit of each of the shift register units comprises a first transistor, the first transistor having a first end, a second end and a control end, wherein the control end is configured to receive the first low frequency signal, the first end is for receiving the first clock signal, and the second end is for outputting a pull signal; The second pull-down control circuit includes a second transistor, and the second transistor has a first end, a second end, and a control end, and the control end is configured to receive the second low frequency signal, and the first end is The first clock signal is received, and the second end is configured to output the pull-down signal, wherein the pull-down signal is generated according to the first low frequency signal and the first clock signal. The shift register according to claim 1, wherein the first pull-down control circuit comprises: a first transistor having a first end, a second end and a control end, and the control end Receiving the first low frequency signal with the second end; and a second transistor having a first end, a second end and a control end, and the first end receives the first clock signal, The second end outputs the pull-down signal, wherein the first end of the first transistor is electrically coupled to the control end of the second transistor. The shift register of claim 4, wherein the second pull-down control circuit comprises: a third transistor having a first end, a second end and a control end, the control end and the first end receiving the second low frequency signal; and a fourth transistor having a first end, a second end and a control end, and the second end receives the first clock signal, the first end outputs the pull-down signal, wherein the second end of the third transistor is electrically coupled to The control end of the fourth transistor. The shift register according to claim 5, wherein in each of the shift register units, the first pull-down control circuit comprises a fifth transistor, and the second pull-down control circuit comprises a sixth transistor, wherein the fifth transistor and the sixth transistor respectively have a first end, a second end, and a control end, and the first end of the fifth transistor is electrically coupled to the first end The second end of the sixth transistor is electrically coupled to the control end of the second transistor, and the first end of the sixth transistor is electrically The control terminal of the fifth transistor is coupled to the control terminal of the sixth transistor, and the control terminal of the sixth transistor receives a pull-up control signal outputted by the pull-up control circuit. The shift register according to claim 1, wherein the shift register units are connected in series to form a multi-stage shift register unit, and the shift register units of each stage can output a gate drive signal and a pull drive signal, and each of the shift register units includes: a pull-up circuit electrically coupled to the pull-down circuit, and the pull-up circuit can receive a second clock signal Outputting the gate output signal and the pull-down drive letter And a pull-up control circuit electrically coupled to the pull-up circuit and the pull-down circuit, and the pull-up control circuit receives the gate drive signal of the first two stages and the pull-down drive signal of the first two stages. The shift register of claim 7, wherein the pull-down circuit of the shift register units of each stage further comprises a seventh transistor, an eighth transistor, and a ninth transistor. And a tenth transistor, wherein the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor respectively have a first end, a second end and a control end, wherein the first The first end of the seventh transistor, the control end of the eighth transistor, the control end of the ninth transistor, and the control end of the tenth transistor are electrically coupled to the first pull-down control circuit, respectively And the second end of the seventh transistor, the second end of the ninth transistor, and the second end of the tenth transistor are electrically coupled to each other, and the ninth transistor The first end of the tenth transistor is electrically coupled to the pull-up circuit, and the second end of the eighth transistor is electrically coupled to the pull-up control circuit and the pull-up circuit respectively Pick up. The shift register according to claim 7, wherein one of the first low frequency signals has a period of 1 to 5 seconds, and the period of the first clock signal is 10 to 200 microseconds. A shift register comprising a plurality of shift register units, wherein the shift register units are serially connected to each other to form a multi-level shift a temporary storage unit, wherein the shift temporary storage units of each stage respectively receive a first clock signal, a second clock signal, a first low frequency signal, a second low frequency signal and a low reference potential, and output a gate drive signal and a pull drive signal, and the shift register units of each stage further comprise: a pull-up circuit having a first output end and a second output end, and correspondingly outputting the gate a driving signal and the pull-down driving signal, wherein the pull-up circuit is configured to receive the second clock signal; the pull-down circuit is electrically coupled to the first output end and the second output end of the pull-up circuit, And receiving the low reference potential; a first pull-down control circuit electrically coupled to the pull-down circuit, and receiving the first low frequency signal and the first clock signal; and a second pull-down control circuit, electrical Is coupled to the pull-down circuit, and receives the second low frequency signal and the first clock signal; wherein the first low frequency signal and the second low frequency signal are complementary potentials, and the first low frequency signal has a period and the first One of the two low frequency signals The first clock signal is larger than one period.