CN107608264B - Simplex code generation device and method applied to optical fiber sensing - Google Patents
Simplex code generation device and method applied to optical fiber sensing Download PDFInfo
- Publication number
- CN107608264B CN107608264B CN201710810092.3A CN201710810092A CN107608264B CN 107608264 B CN107608264 B CN 107608264B CN 201710810092 A CN201710810092 A CN 201710810092A CN 107608264 B CN107608264 B CN 107608264B
- Authority
- CN
- China
- Prior art keywords
- module
- output
- clock
- simplex
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Optical Communication System (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
the invention discloses a Simplex code generating device and method applied to optical fiber sensing, the method is that a standard Hadamard matrix with a set order is obtained by calculation, the matrix is converted into a 128-order Simplex code matrix by means of replacement and zero padding, then the code matrix is stored into a double-port RAM with the data width of 128 bits, and finally the data in the double-port RAM is transferred in sequence according to bits under the triggering of a synchronous signal to complete code output; the device mainly comprises a singlechip minimum system, a key module, an LCD display module, a clock input module, an FPGA module and the like. The invention adopts low-voltage low-power consumption electronic devices to realize Simplex code output, easily meets the design requirement of intrinsically safe coal mine of a code generating device, and is suitable for special application occasions such as underground coal mines.
Description
Technical Field
The present invention relates to a method and an apparatus for generating binary codes, and more particularly, to a method and an apparatus for generating Simplex codes for optical fiber sensing.
Background
The distributed optical fiber sensing technology is widely applied to distributed measurement of parameters such as temperature, strain, pressure, vibration and the like, mainly takes pulse laser as an excitation light source, and obtains the parameter information by measuring and analyzing a Raman scattering signal, a Rayleigh scattering signal or a Brillouin scattering signal. With the increase of the optical fiber sensing distance, the scattering signal is weaker, the signal-to-noise ratio of the measurement signal is reduced, and if the laser pulse width is increased, the signal-to-noise ratio can be improved, but the measurement spatial resolution is reduced. By measuring and averaging the scattered signals for multiple times, the signal-to-noise ratio can also be improved, but the measurement time resolution is greatly reduced, which does not meet the requirements of real-time measurement. By performing Simplex encoded output on the laser pulses instead of the conventional single narrow pulse output to excite the sensing fiber, this approach can improve the signal-to-noise ratio without degrading the spatial and temporal resolution of the measurement. The distributed optical fiber sensing technology is applied to underground coal mines, such as measurement of temperature and strain distribution of a shaft, and is of great importance to coal mine safety early warning. The underground environment of the coal mine is complex, the interference factors are more, and the improvement of the signal-to-noise ratio and the increase of the measurement precision are particularly important. The existing laser pulse Simplex codes are mainly generated by computer software and a multifunctional function generator, however, the code generating devices are not suitable for underground coal mines and cannot be used for improving the measurement signal-to-noise ratio of the underground coal mine optical fiber sensing technology.
Disclosure of Invention
The invention aims to make up for the defects of the prior art and provides a Simplex code generating device and method applied to optical fiber sensing.
The invention is realized by the following technical scheme:
a Simplex code generating device applied to optical fiber sensing comprises a singlechip minimum system, a key input module, an LCD display module, a clock input module and an FPGA module, wherein the FPGA module comprises a phase-locked loop module, a frequency division module, an address generator module, a data buffer unit module, a dual-port RAM module and a parallel-serial shift register output module, the singlechip minimum system 1 obtains the set values of the Simplex code length and the time width of a single binary code through the key input module and the LCD display module, a low-frequency clock output by the clock input module is multiplied by the frequency of the phase-locked loop module to become a high-frequency clock, the high-frequency clock is divided by the frequency division module to obtain a frequency division clock with the period equal to the time width of the single binary code, the frequency division coefficient of the frequency division module is given by the minimum system, and the frequency division singlechip is used as an input clock of the parallel-serial shift register output module, the single-chip microcomputer minimum system stores all elements of the obtained Simplex coding matrix into the double-port RAM module through the data buffer unit module, the address generator module outputs Simplex coding matrix data stored in the double-port RAM module to the parallel-serial shift register output module one line by one line under the common control of the single-chip microcomputer minimum system and a synchronous signal, and the parallel-serial shift register output module outputs Simplex coding data under the control of a frequency division clock.
The minimum system of the single chip microcomputer consists of an STM32 single chip microcomputer, a reset circuit and a clock crystal oscillator circuit, and the STM32 single chip microcomputer completes calculation and storage of a Simplex coding matrix; the reset circuit provides an effective power-on reset signal for the STM32 single chip microcomputer, and the single chip microcomputer can be normally started when being powered on; the clock crystal oscillator circuit provides a working clock for the singlechip.
An input pin CLKIN of the phase-locked loop module is connected with an output pin CLK of the clock input module, a pin CLKIN clock is a low-frequency clock, an output pin CLKIOUT of the phase-locked loop module is connected with a clock input pin CLKIN of the frequency division module, and a pin CLKOUT clock is a high-frequency clock;
the frequency division coefficient of the frequency division module is determined by data of pins D7 ~ D0 of the frequency division module, GPIO pins PB15 ~ PB8 of a minimum system of the singlechip are connected with the pins D7 ~ D0 of the frequency division module, an output pin CLKOUT of the frequency division module controls an input clock CLK of an output module of the parallel ~ serial shift register, and the pin CLKOUT clock is a frequency division clock;
the method comprises the steps that address output pins A6 ~ A0 of an address generator module generate addresses 0 ~ 127, pins A6R ~ A0R of the double ~ port RAM module are controlled to select different address units of the double ~ port RAM module, a CE output pin of the address generator module controls CER of the double ~ port RAM module and is used for selecting the double ~ port RAM module to operate, an RD output pin of the address generator module controls RDR of the double ~ port RAM module and is used for reading the double ~ port RAM module, input pins of the address generator module are respectively CLR, EN and CLK, the CLR pin is connected with a GPIO pin PC10 of a minimum system of the single chip microcomputer and is used for resetting GPIO pins A6 ~ A0 of the address output pin, the EN pin is connected with a GPIO pin PC 45 of the minimum system of the single chip microcomputer and is used for enabling the address generator module to work, and when a group of Simplex codes are output, the EN pin is invalid, the address generator module does not work, the CE pin and the RD output invalid level when a frequency of a synchronizing signal is the same as a pulse 6 of the laser pulse generator module, the next address generator module reads a next address of the double ~ port RAM module, namely, and reads a next address of the address generator module;
the output combinations Q127 ~ Q0 of the data buffer unit module form a 128 ~ bit data width and are connected with data input pins D127L ~ D0L of the double ~ port RAM module, the data input pins D15 ~ D0 of each module in the data buffer unit module are connected with GPIO pins PD15 ~ PD0 of a minimum system of the single chip microcomputer, the CLK pin of each module is independently controlled and is respectively connected with the GPIO pins PB0 ~ PB7 of the minimum system of the single chip microcomputer;
The writing operation of the double-port RAM module is controlled by the minimum system of the single chip and the data buffer unit module together, and the reading operation of the double-port RAM module is controlled by the address generator module;
parallel data pins D127 ~ D0 input by the parallel ~ serial shift register output module are connected with 128 ~ bit data pins D127R ~ D0R output by the double ~ port RAM module, Simplex coding output is output from a Q0 pin of the parallel ~ serial shift register output module, and a GPIO pin PC11 of a minimum system of the single chip microcomputer controls Q0 to reset before the next group of Simplex coding output.
A Simplex code generation method applied to optical fiber sensing comprises the following steps:
(1) acquiring a Simplex coding matrix: firstly, the key input module is combined with the LCD display module 3 to set the coding length 2n-1 and time width of single binary code, the order of 2 is calculated by the minimum system of the single chip microcomputer according to the code lengthnWherein n is less than or equal to 7, replacing all-1 elements in the matrix with 0, and then removing the first row and the first column of the matrix to obtain a 2n-new matrix of order 1, reconverting the new matrix to order fixed at order 2 by zero padding7The simple coding matrix of (1) is specifically transformed by the following process: first 2 of the first row of the Simplex coding matrixn-1 element is provided by the first row element of the new matrix, the remaining elements of the first row of the Simplex coding matrix being complemented by 0; simplex coding matrix second row 2 firstn-1 element is provided by the second row element of the new matrix, the remaining elements of the second row of the Simplex coding matrix being complemented by 0; and so on until completing the 2 nd of Simplex coding matrixn-1 row; left of Simplex coding matrix [27-(2n-1)]All elements of the row are complemented by 0;
(2) Storing the Simplex coding matrix: the single-chip microcomputer minimum system firstly writes first row elements of the Simplex coding matrix into the data buffering unit module, then outputs through the GPIO pin to enable a data writing address of the double-port RAM module to be 0, controls writing signals and chip selection signals of the double-port RAM module to be effective, and accordingly completes storage of the first row elements of the Simplex coding matrix into the first address unit of the double-port RAM module;
(3) Outputting Simplex codes: the minimum system of the single chip microcomputer determines the frequency division coefficient of the frequency division module according to the set time width of a single binary code, the clock input of the frequency division module is controlled by the frequency multiplication of the output of the clock input module through the phase-locked loop module, the output clock period of the frequency division module is the set time width of the single binary code, when a first synchronous signal arrives, the address generator module generates an address 0, the minimum system of the single chip microcomputer controls the address generator module to output a first row element of a Simplex coding matrix stored in a first address unit in the dual-port RAM module to the parallel-serial shift register output module, and when the frequency division module outputs the signalUnder the action of a clock, the first row elements of the Simplex coding matrix are sequentially output according to bits, when a second synchronous signal arrives, the address generator module generates an address 1, the singlechip minimum system controls the address generator module to output the second row elements of the Simplex coding matrix stored in the second address unit in the dual-port RAM module to the parallel-serial shift register output module, under the action of an output clock of the frequency division module, the second row elements of the Simplex coding matrix are sequentially output according to bits, and the like until the 2 nd row elements are outputnand (4) 1 line of Simplex coded data, and finally controlling the address generator module to stop working by the minimum system of the single chip until another group of Simplex coded data is output.
The invention has the advantages that: (1) the invention adopts low-voltage low-power consumption electronic devices to realize Simplex code output, easily meets the design requirement of intrinsically safe coal mine of a code generating device, and is suitable for special application occasions such as underground coal mines.
(2) The invention stores Simplex coded data with different coding lengths by a data zero padding method and adopting a double-port RAM with fixed data width and fixed address unit number, so that the time sequence processing of the FPGA module is the same no matter how long the coding length is, the time sequence design of the FPGA module is simplified, and the working reliability is improved.
Drawings
FIG. 1 is a block diagram of the apparatus of the present invention;
FIG. 2 is a schematic diagram of a circuit specifically designed within an FPGA module of the apparatus of the present invention;
fig. 3 is a flow chart of the program of the single chip microcomputer in the device of the invention.
Detailed Description
as shown in fig. 1, the Simplex code generation device applied to optical fiber sensing includes a minimum system 1 of a single chip, a key input module 2, an LCD display module 3, a clock input module 4, and an FPGA module, wherein the FPGA module specifically includes a phase-locked loop module 5, a frequency division module 6, an address generator module 7, a data buffer unit module 8, a dual-port RAM module 9, and a parallel-serial shift register output module 10. The singlechip minimum system 1 obtains the set values of Simplex coding length and time width of a single binary code through the key input module 2 and the LCD display module 3. The low-frequency clock output by the clock input module 4 can be a high-frequency clock after frequency multiplication by the phase-locked loop module 5, the high-frequency clock is subjected to frequency division by the frequency division module 6 to obtain a frequency division clock with a period equal to the time width of a single binary code, the frequency division coefficient of the frequency division module 6 is given by the minimum system 1 of the single chip microcomputer, and the frequency division clock is used as an input clock of the parallel-serial shift register output module 10 to control data shift. The single-chip microcomputer minimum system 1 stores all elements of the obtained Simplex coding matrix into a double-port RAM module 9 through a data buffer unit module 8. The address generator module 7 outputs Simplex coding matrix data stored in the dual-port RAM module 9 to the parallel-serial shift register output module 10 row by row under the common control of the minimum system 1 of the single chip microcomputer and a synchronization signal, and the parallel-serial shift register output module 10 outputs Simplex coding data under the control of a frequency division clock.
The single chip microcomputer minimum system 1 consists of an STM32 single chip microcomputer, a reset circuit and a clock crystal oscillator circuit, and the STM32 single chip microcomputer completes calculation and storage of a Simplex coding matrix; the reset circuit provides an effective power-on reset signal for the STM32 single chip microcomputer, and the single chip microcomputer can be normally started when being powered on; the clock crystal oscillator circuit provides a working clock for the singlechip.
As shown in fig. 2, the pll module 5 is M12, the input terminal CLKIN of M12 is connected to the output terminal CLK of the clock input module 4, the terminal clock is a low frequency clock, and the output terminal CLKOUT of M12 is connected to the clock input terminal CLKIN of M13, the terminal clock is a high frequency clock.
the frequency division module 6 is M13, the frequency division coefficient is determined by data of pins D7 ~ D0, GPIO pins PB15 ~ PB8 of the singlechip minimum system 1 are connected with pins D7 ~ D0 of M13, an output pin CLKOUT of the M13 controls an input clock CLK of the M11, and the pin clock is a frequency division clock.
the address generator module 7 is M10, address output pins A6 ~ A0 of M10 generate addresses 0 ~ 127, control pins A6R ~ A0R of M9, and are used for selecting different address units of 0 ~ 127 of M9, a CE output pin of M10 controls CER of M9 and is used for selecting M9 for operation, an RD output pin of M10 controls RDR of M9 and is used for reading M9, input pins of M10 are respectively CLR, EN and CLK, the CLR pin is connected with a GPIO pin PC10 of the SCM minimum system 1 and is used for resetting the address output pins A6 ~ A0, the EN pin is connected with a GPIO pin PC9 of the SCM minimum system 1 and is used for enabling M10 to work, after a group of Simplex coding output, the EN pin is invalid, the M10 pin, the CE pin and the RD output pin is invalid, the CLK pin is connected with a synchronizing signal, the frequency of the synchronizing signal is the same as that of the pulse laser, when a group of Simplex coding output signals comes, the next address output pin A6356, the next address output pin is added with the next address unit, namely, the next address 0 is read.
the data buffer unit module 8 is formed by M1 ~ M1 jointly, the output combinations Q127 ~ Q1 of the M1 ~ M1 form 128 ~ bit data width, the data buffer unit module is connected with the data input pins D127 ~ D0 1 of the M1 ~ M1, the data input pins D1 ~ D1 of each module in the M1 ~ M1 are connected with GPIO pins PD1 ~ PD1 of a minimum system 1 of the single chip microcomputer, the CLK pin of each module is controlled independently, the GPIO pins PB1 ~ PB7 of the minimum system 1 of the single chip microcomputer are connected respectively to store the first row elements of the Simplex coding matrix to the first address unit of the M1 as an example to explain the operation process of the data buffer unit module 8 by the minimum system 1 of the single chip microcomputer, the number of the elements in each row of the Simplex coding matrix is 128, the 128 ~ bit data are divided into a group from left to right, the 16 ~ bit data group is marked as 7 ~ 0, the 16 ~ bit data group is sent to the PB1 PD1 PB, the PB7 ~ PB data buffer unit PB1 controls the invalid data elements connected with the first row of the first effective data coding matrix to be equal to the invalid PC, the invalid data write process of the first row of the invalid data elements of the first row of the PCL 1, the PCL coding matrix, the PCL 1 is connected with the PCL 1, the PCL 1 is connected with the PCL 1.
The dual-port RAM module 9 is M9, and as described above, the write operation to M9 is controlled by the single-chip microcomputer minimal system 1 and the data buffer unit module 8, and the read operation to M9 is controlled by the address generator module 7.
the parallel ~ serial shift register output module 10 is M11, parallel data pins D127 ~ D0 input by M11 are connected with 128 ~ bit data pins D127R ~ D0R output by M9, Simplex coding output is output from a pin Q0 of M11, and a GPIO pin PC11 of the minimum system 1 of the singlechip controls Q0 to reset before the next group of Simplex coding output.
A Simplex code generation method applied to optical fiber sensing comprises the following steps:
Firstly, the key input module 2 is combined with the LCD display module 3 to set the coding length 2n-1 and time width of single binary code, the order of 2 is calculated by the SCM minimum system 1 according to the code lengthnReplacing all-1 elements in the matrix with 0, and then removing the first row and the first column of the matrix to obtain a 2n-new matrix of order 1, reconverting the new matrix to order fixed at order 2 by zero padding7The simple coding matrix of (= 128) is specifically transformed by the following steps: first 2 of the first row of the Simplex coding matrixn-1 element is provided by the first row element of the new matrix, the remaining elements of the first row of the Simplex coding matrix being complemented by 0; simplex coding matrix second row 2 firstn-1 element is provided by the second row element of the new matrix, the remaining elements of the second row of the Simplex coding matrix being complemented by 0; and so on until completing the 2 nd of Simplex coding matrixn-1 row; left of Simplex coding matrix [27-(2n-1)]All elements of a row are complemented by 0. Next, the minimum system 1 of the single chip microcomputer writes the first row elements of the Simplex coding matrix into the data buffer unit module 8, then outputs the data write address of the dual-port RAM module 9 to be 0 through the GPIO pin, and controls the write signal and the chip select signal of the dual-port RAM module 9 to be effective, thereby completing the storage of the first row elements of the Simplex coding matrix into the first address unit of the dual-port RAM module 9. Similarly, the minimum system 1 of the single chip microcomputer writes the second row elements of the Simplex coding matrix into the data buffer unit module 8, then the data write address of the dual-port RAM module 9 is made to be 1 through the output of the GPIO pin, the write signal and the chip select signal of the dual-port RAM module 9 are controlled to be effective, and therefore the second row elements of the Simplex coding matrix are stored into the dual-port RAM modulein the second address unit of the RAM module 9, the storage of all row elements of the coding matrix is completed by analogy with the minimum system 1 of the single chip microcomputer. Finally, the single chip microcomputer minimum system 1 firstly determines the frequency division coefficient of the frequency division module 6 according to the set time width of the single binary code, the clock input of the frequency division module 6 is controlled by the output of the clock input module 4 after frequency multiplication through the phase-locked loop module 5, and the output clock period of the frequency division module 6 is the set time width of the single binary code. When a first synchronous signal arrives, the address generator module 7 generates an address 0, the single-chip microcomputer minimum system 1 controls the address generator module 7 to output a first row element of the Simplex coding matrix stored in a first address unit in the dual-port RAM module 9 to the parallel-serial shift register output module 10, and the first row element of the Simplex coding matrix is sequentially output according to bits under the action of an output clock of the frequency division module 6. When a second synchronous signal arrives, the address generator module 7 generates an address 1, the single-chip microcomputer minimum system 1 controls the address generator module 7 to output a second row element of the Simplex coding matrix stored in a second address unit in the dual-port RAM module 9 to the parallel-serial shift register output module 10, under the action of an output clock of the frequency division module 6, the second row element of the Simplex coding matrix is sequentially output according to bits, and the rest is done until a 2 nd element is outputnAnd 1 line of Simplex coded data, and finally the singlechip minimum system 1 controls the address generator module 7 to stop working until another group of Simplex coded data is output.
the minimum system 1 of the single chip computer coordinates the work of each component. As shown in fig. 3, after the system is powered on, initialization operations are first performed, including setting a single chip system operating clock, a timer operating mode, GPIO configuration, and the like. After initialization operation, the single chip microcomputer starts to wait for the keys to set output coding parameters, determines according to the set time width parameter of a single binary code and outputs a frequency division coefficient to the frequency division module 6 through a GPIO pin, calculates a standard Hadamard matrix according to the set coding length, and converts the standard Hadamard matrix into a 128-order Simplex coding matrix through means of zero padding and the like. Next, all elements in the Simplex coding matrix are stored in rows into the dual port RAM module 9. And then, waiting for a synchronous signal to trigger the code output operation. When the Simplex coded data with the set coding length are all output, the singlechip prohibits the address generator module 7 from working, and simultaneously resets the coded output to prepare for the next group of Simplex coded output.
The invention has not been described in detail and is part of the common general knowledge of a person skilled in the art.
Claims (4)
1. A Simplex code generating device applied to optical fiber sensing is characterized in that: the system comprises a singlechip minimum system, a key input module, an LCD display module, a clock input module and an FPGA module, wherein the FPGA module comprises a phase-locked loop module, a frequency division module, an address generator module, a data buffer unit module, a dual-port RAM module and a parallel-serial shift register output module, the singlechip minimum system obtains the set values of Simplex coding length and time width of a single binary code through the key input module and the LCD display module, a low-frequency clock output by the clock input module is multiplied by the phase-locked loop module to form a high-frequency clock, the high-frequency clock is divided by the frequency division module to obtain a frequency division clock with the period equal to the time width of the single binary code, the frequency division coefficient of the frequency division module is given by the singlechip minimum system, the frequency division clock is used as an input clock of the parallel-serial shift register output module to control data shift, and the singlechip minimum system stores all elements of the obtained Simplex coding matrix In the dual-port RAM module, an address generator module outputs Simplex coding matrix data stored in the dual-port RAM module to a parallel-serial shift register output module one line by one line under the common control of a minimum system and a synchronous signal of a single chip microcomputer, and the parallel-serial shift register output module outputs Simplex coding data under the control of a frequency division clock.
2. the apparatus for generating Simplex code applied to optical fiber sensing according to claim 1, wherein: the minimum system of the single chip microcomputer consists of an STM32 single chip microcomputer, a reset circuit and a clock crystal oscillator circuit, and the STM32 single chip microcomputer completes calculation and storage of a Simplex coding matrix; the reset circuit provides an effective power-on reset signal for the STM32 single chip microcomputer, and the single chip microcomputer can be normally started when being powered on; the clock crystal oscillator circuit provides a working clock for the singlechip.
3. The apparatus for generating Simplex code applied to optical fiber sensing according to claim 2, wherein: an input pin CLKIN of the phase-locked loop module is connected with an output pin CLK of the clock input module, a pin CLKIN clock is a low-frequency clock, an output pin CLKIOUT of the phase-locked loop module is connected with a clock input pin CLKIN of the frequency division module, and a pin CLKOUT clock is a high-frequency clock;
the frequency division coefficient of the frequency division module is determined by data of pins D7-D0, GPIO pins PB 15-PB 8 of the minimum system of the singlechip are connected with pins D7-D0 of the frequency division module, an output pin CLKOUT of the frequency division module controls an input clock CLK of an output module of the parallel-serial shift register, and the pin CLKOUT clock is a frequency division clock;
the address generator module comprises an address generator module, a CE output pin, a RD output pin, a first control module and a second control module, wherein the address generator module generates addresses 0-127 through address output pins A6-A0, controls pins A6R-A0R of the dual-port RAM module and is used for selecting different address units of the dual-port RAM module from 0 to 127, the CE output pin of the address generator module controls CER of the dual-port RAM module and is used for selecting the dual-port RAM module to operate, and the RD output pin of the address generator module controls RDR of the dual-port RAM module and is used for reading the dual-port RAM module; the input pins of the address generator module are respectively CLR, EN and CLK, the CLR pin is connected with a GPIO pin PC10 of the minimum system of the single chip microcomputer and is used for resetting address output pins A6-A0, the EN pin is connected with a GPIO pin PC9 of the minimum system of the single chip microcomputer and is used for enabling the address generator module to work, when a group of Simplex codes are output, the EN pin is invalid, the address generator module does not work, and the pins CE and RD output invalid levels; the CLK pin is connected with a synchronous signal, the frequency of the synchronous signal is the same as the repetition frequency of the pulse laser, when the next synchronous signal arrives, the values of the address output pins A6-A0 are added with 1, and the reading operation of the next address unit is carried out on the dual-port RAM module;
The output combination Q127-Q0 of the data buffer unit module forms a 128-bit data width and is connected with the data input pins D127L-D0L of the double-port RAM module, the data input pins D15-D0 of each module in the data buffer unit module are connected with the GPIO pins PD 15-PD 0 of the minimum system of the singlechip, the CLK pin of each module is independently controlled and is respectively connected with the GPIO pins PB 0-PB 7 of the minimum system of the singlechip;
the writing operation of the double-port RAM module is controlled by the minimum system of the single chip and the data buffer unit module together, and the reading operation of the double-port RAM module is controlled by the address generator module;
Parallel data pins D127-D0 input by the parallel-serial shift register output module are connected with 128-bit data pins D127R-D0R output by the double-port RAM module, Simplex coding output is output from a pin Q0 of the parallel-serial shift register output module, and a GPIO pin PC11 of a minimum system of the single chip microcomputer controls Q0 to reset before the next group of Simplex coding output.
4. a Simplex code generation method applied to optical fiber sensing is characterized in that: the method comprises the following steps:
(1) Acquiring a Simplex coding matrix: firstly, the key input module is combined with the LCD display module 3 to set the coding length 2n-1 and time width of single binary code, the order of 2 is calculated by the minimum system of the single chip microcomputer according to the code lengthnWherein n is less than or equal to 7, replacing all-1 elements in the matrix with 0, and then removing the first row and the first column of the matrix to obtain a 2n-new matrix of order 1, reconverting the new matrix to order fixed at order 2 by zero padding7The simple coding matrix of (1) is specifically transformed by the following process: first 2 of the first row of the Simplex coding matrixn-1 element is provided by the first row element of the new matrix, the remaining elements of the first row of the Simplex coding matrix being complemented by 0; simplex coding matrix second row 2 firstn-1 element is provided by the second row element of the new matrix, the remaining elements of the second row of the Simplex coding matrix being complemented by 0; and so on until completing the 2 nd of Simplex coding matrixn-1 row; left of Simplex coding matrix [27-(2n-1)]All elements of the row are complemented by 0;
(2) storing the Simplex coding matrix: the single-chip microcomputer minimum system firstly writes first row elements of the Simplex coding matrix into the data buffering unit module, then outputs through the GPIO pin to enable a data writing address of the double-port RAM module to be 0, controls writing signals and chip selection signals of the double-port RAM module to be effective, and accordingly completes storage of the first row elements of the Simplex coding matrix into the first address unit of the double-port RAM module;
(3) Outputting Simplex codes: the method comprises the steps that a singlechip minimum system determines a frequency division coefficient of a frequency division module according to the set time width of a single binary code, the clock input of the frequency division module is controlled by the frequency multiplication of the output of a clock input module through a phase-locked loop module, the output clock period of the frequency division module is the set time width of the single binary code, when a first synchronous signal arrives, an address generator module generates an address 0, the singlechip minimum system controls the address generator module to output a first row element of a Simplex coding matrix stored in a first address unit in a dual-port RAM module to a parallel-serial shift register output module, under the action of the output clock of the frequency division module, the first row element of the Simplex coding matrix is sequentially output according to bits, when a second synchronous signal arrives, the address generator module generates an address 1, and the singlechip minimum system controls the address generator module to output a second row element of the Simplex coding matrix stored in a second address unit in the dual-port RAM module to a parallel-serial shift register output The output module of the bit register outputs the second row elements of the Simplex coding matrix in bit-by-bit sequence under the action of the output clock of the frequency division module, and so on until the 2 nd element is outputnAnd (4) 1 line of Simplex coded data, and finally controlling the address generator module to stop working by the minimum system of the single chip until another group of Simplex coded data is output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710810092.3A CN107608264B (en) | 2017-09-11 | 2017-09-11 | Simplex code generation device and method applied to optical fiber sensing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710810092.3A CN107608264B (en) | 2017-09-11 | 2017-09-11 | Simplex code generation device and method applied to optical fiber sensing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107608264A CN107608264A (en) | 2018-01-19 |
| CN107608264B true CN107608264B (en) | 2019-12-13 |
Family
ID=61063295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710810092.3A Active CN107608264B (en) | 2017-09-11 | 2017-09-11 | Simplex code generation device and method applied to optical fiber sensing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107608264B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110619166B (en) * | 2019-09-09 | 2023-02-10 | 中国人民解放军国防科技大学 | Design method of low-power-consumption clock tree |
| CN111786723A (en) * | 2020-06-29 | 2020-10-16 | 安徽理工大学 | PPM code generating device for VLC system for detecting miner signs |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5353110A (en) * | 1991-07-12 | 1994-10-04 | Tektronix, Inc. | Method and apparatus for carrying out optical time domain reflectometry using weighing techniques |
| CN101162398A (en) * | 2006-10-12 | 2008-04-16 | 东莞理工学院 | Arbitrarily signal generating device |
| CN101852627A (en) * | 2009-04-01 | 2010-10-06 | 西南交通大学 | Coding technique for improving detection performance of distributed fiber sensor and application thereof |
| CN103453921A (en) * | 2013-09-18 | 2013-12-18 | 电子科技大学 | Brillouin distributed optical fiber sensing system |
| CN106953687A (en) * | 2017-01-19 | 2017-07-14 | 中铁第四勘察设计院集团有限公司 | Method is determined based on the Simplex POTDR systems encoded and its signal |
-
2017
- 2017-09-11 CN CN201710810092.3A patent/CN107608264B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5353110A (en) * | 1991-07-12 | 1994-10-04 | Tektronix, Inc. | Method and apparatus for carrying out optical time domain reflectometry using weighing techniques |
| CN101162398A (en) * | 2006-10-12 | 2008-04-16 | 东莞理工学院 | Arbitrarily signal generating device |
| CN101852627A (en) * | 2009-04-01 | 2010-10-06 | 西南交通大学 | Coding technique for improving detection performance of distributed fiber sensor and application thereof |
| CN103453921A (en) * | 2013-09-18 | 2013-12-18 | 电子科技大学 | Brillouin distributed optical fiber sensing system |
| CN106953687A (en) * | 2017-01-19 | 2017-07-14 | 中铁第四勘察设计院集团有限公司 | Method is determined based on the Simplex POTDR systems encoded and its signal |
Non-Patent Citations (2)
| Title |
|---|
| 分布式光纤温度传感系统的设计及优化;张正文;《中国优秀硕士学位论文全文数据库信息科技辑（月刊）》;20160815(第08期);I140-270：P72 * |
| 采用Simplex编码光外调制的拉曼散射分布式光纤传感器;宋牟平;《中国激光》;20100630(第6期);P1462-1466 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107608264A (en) | 2018-01-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107608264B (en) | Simplex code generation device and method applied to optical fiber sensing | |
| US20100049882A1 (en) | Hotkey processing method and computer system | |
| EP2791809B1 (en) | Unified data masking, data poisoning, and data bus inversion signaling | |
| JP4471901B2 (en) | Random number generator | |
| TW200602848A (en) | Computer readable storage medium comprising a program product, recording medium, method, and information processing apparatus for controlling an execution mode of a CPU | |
| CN111426946B (en) | System chip for full speed testing of logic circuits and method of operating the same | |
| CN112765082B (en) | Multi-host arbitration method, device and readable storage medium | |
| CN109256172B (en) | Memory device including a detection clock pattern generator | |
| JPH10303993A (en) | Method for transmitting and receiving asynchronous serial data of digital signal processing processor | |
| JP2683093B2 (en) | Optical coordinate input device | |
| CN109906609B (en) | Method and apparatus for monitoring an image sensor | |
| US11442575B2 (en) | Touch display driving apparatus and operation method thereof | |
| CN102411892A (en) | Display control chip | |
| JP6848559B2 (en) | Time measuring device and distance measuring device | |
| CN103944546A (en) | Device and method for preventing reset signal inside chip from losing efficacy | |
| KR100507272B1 (en) | Circuit of generation start pulse signal in tft-lcd | |
| US20100169697A1 (en) | Control Device Having Output Pin Expansion Function and Output Pin Expansion Method | |
| KR20210153407A (en) | Electronic device for executing error correction operation and error check operation | |
| RU2420788C1 (en) | Data output control system | |
| CN202205437U (en) | Display and control chip | |
| US11960319B2 (en) | Memory device with real-time monitoring | |
| US11080020B2 (en) | Information processing device and random number generating method | |
| JP2785092B2 (en) | Flat panel display | |
| RU2406111C1 (en) | Execution unit | |
| SU693408A1 (en) | Pseudorandom number generator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |